528 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 10, NO. 3, MAY 2011

MOSFET Nonvolatile Memory with High-DensityCobalt-Nanodots Floating Gate and HfO2

High-k Blocking DielectricYanli Pei, Chengkuan Yin, Toshiya Kojima, Ji-Cheol Bea, Hisashi Kino, Takafumi Fukushima,

Tetsu Tanaka, and Mitsumasa Koyanagi, Fellow, IEEE

Abstract—We report high-performance MOSFET nonvolatilememory with high-density cobalt-nanodots (Co-NDs) floating gate(the density is as high as 4–5 × 1012 /cm2 and the size is ∼2 nm)and HfO2 high-k blocking dielectric. The device is fabricated us-ing a gate-last process. A large memory window, high-speed pro-gram/erase (P/E), long retention time, and excellent endurance till106 P/E cycles are obtained. In addition, the discrete Co-NDs makedual-bit operation successful. The high performance suggests thathigh work-function Co-NDs combined with high-k blocking di-electric have a potential as a next-generation nonvolatile-memorycandidate.

Index Terms—Cobalt nanodots, high-k, MOSFET, nonvolatilememory.

I. INTRODUCTION

M ETAL nanodots memories attract the most attentionas promising candidates for next-generation-nonvolatile

memory (NVM) [1], [2]. Comparing with semiconductornanocrystals [3], metal nanodots show some advantages, suchas high density of states around Fermi level, strong couplingwith the conductions, and smaller energy perturbation of met-als. In addition, the most important characteristic is that metalhas a wide range of available work functions, which providesone more degree to design freedom to engineer the tradeoff be-tween program/erase (P/E) and charge retention. As is known,

Manuscript received July 26, 2009; accepted April 30, 2010. Date of pub-lication May 18, 2010; date of current version May 11, 2011. This work wassupported in part by a grant-in-aid for Scientific Research on Priority Area fromthe Ministry of Education, Culture, Sports, Science and Technology of Japanunder Grant 18063002. The review of this paper was arranged by AssociateEditor E. T. Yu.

Y. Pei is with the International Advanced Research and Educa-tion Organization, Tohoku University, Sendai 980-0876, Japan (e-mail:peiyanli@sd.mech.tohoku.ac.jp).

C. Yin was with Graduate School of Engineering, Tohoku University, Sendai980-0876, Japan. He is now with SanDisk Limited, Yokohama 222-0033, Japan(e-mail: Cheng-Kuan.Yin@sandisk.com).

T. Kojima and H. Kino are with Graduate School of Engineering, TohokuUniversity, Sendai 980-0876, Japan (e-mail: kojima-t@tech.eng.tohoku.ac.jp;kino@sd.mech.tohoku.ac.jp).

J.-C. Bea, T. Fukushima, and M. Koyanagi were with the Gradu-ate School of Engineering, Tohoku University, Sendai 980-0876, Japan.They are now with the New Industry Creation Hatchery Center, TohokuUniversity, Sendai 980-0876, Japan (e-mail: beatrix@sd.mech.tohoku.ac.jp;fukusima@sd.mech.tohoku.ac.jp; koyanagi@sd.mech.tohoku.ac.jp).

T. Tanaka is with the Graduate School of Biomedical Engineering, TohokuUniversity, Sendai 980-0876, Japan (e-mail: ttanaka@ibc.mech.tohoku.ac.jp).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TNANO.2010.2050331

the work function of nanocrystal affects both the depth of thepotential well at the storage node and the density of states avail-able for tunneling in the substrate. However, they will face somechallenges. First, it is the formation of high-density metal nan-odots in the floating gate in order to overcome the electricalfluctuation between memory cells [4], [5]. The main critical is-sue that limits the scaling of nanodots memory is attributed tothe variability in dot size and dot density between devices [4].Second, it is required to prevent metal diffusion and metal/oxidereaction, which potentially worsen device performance [6]–[8].Third, the increase of Fermi level caused by quantum size effectis another important concern, which will degrade the retentioncharacteristics [9], [10]. The metal nanodots with a large workfunction can compensate the increase of Fermi level. Of allmetal nanodots applied to NVM, cobalt is a good candidate.It has work function as high as 5.0 eV, which is higher thantungsten with middle work function of 0.5 eV. In addition, theenthalpy of Co–O bond (384 kJ/mol) is much lower than that ofSi–O (799 kJ/mol), suggesting the formation of high metallic-cobalt nanodots (Co-NDs) in silicon oxide easily.

Moreover, in order to improve further the device performanceof nanocrystal memory, it has been studied to use high-k ma-terials replacing traditional SiO2-blocking dielectric [11], [12].The high-k dielectric provides a small equivalent oxide thickness(EOT) with a thicker physical thickness. Therefore, it can sup-press the leakage current to improve the retention time, mean-while enhance the coupling effect of gate to channel to decreasein the P/E operation voltage.

In our previous study, high-density Co-NDs with highmetallic-crystallized structure were formed by self-assemblednanodot deposition (SAND) successfully [13]. The Co-NDmetal-oxide-semiconductor (MOS) capacitor shows a relativelonger retention time due to the high work function of cobalt[13]. However, the memory characteristics were not explainedin details. In order to investigate the memory characteristicsclearly, fabrication of MOSFET is necessary. In this paper, theMOSFET nonvolatile memory was fabricated with high-densityCo-NDs floating gate and HfO2 high-k gate blocking dielectric.The gate-last process was used in the fabrication. The memorycharacteristics were investigated in detail.

II. MOSFET NONVOLATILE-MEMORY FABRICATION

Co-ND MOSFET memory was fabricated by gate-last pro-cess, which allows the activation of source/drain (S/D) dopants

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PEI et al.: MOSFET NONVOLATILE MEMORY WITH HIGH-DENSITY Co-NDs FLOATING GATE AND HfO2 HIGH-k BLOCKING DIELECTRIC 529

Fig. 1. (a) Schematic of Co-ND MOSFET memory, (b) fabrication processflow, and (c) SEM image of etched gate stack structure.

at high temperature without affecting the formation of gate stack.The schematic of Co-ND MOSFET memory and fabricationprocess flow were shown in Fig. 1(a) and (b). The devices werefabricated on p-type (1 0 0) Si wafers. After the formation oflocal oxidation of silicon (LOCOS) isolation, the S/D regionswere formed by arsenic (As) ion implantation, followed by anactivation annealing at 1000 ◦C for 5 min in N2 ambient. A2-nm thick Co-NDs film was deposited on a 5-nm thick ther-mal silicon oxide by SAND, and then 800 ◦C post-depositionannealing (PDA) was applied. The Co-NDs density is 4–5 ×1012 /cm2 , and the size is ∼2 nm. The detailed preparation andphysical characteristics of Co-NDs have been reported else-where [13]. Subsequently, a SiO2 (1 nm)/HfO2 (40 nm) stackoxide was sputtered as a blocking oxide, followed by 600 ◦CPDA, in N2 ambient for 30 min. Here, the 1-nm thick SiO2 wasused to prevent the interdiffusion between HfO2 and Co-NDslayer. After Ta electrode deposition, the gate was patterned us-ing electron cyclotron resonance (ECR) argon (Ar) ion milling.The excellent gate etching was confirmed by SEM image shownin Fig. 1(c). After passivation-film deposition, the contact holesin source, drain, and gate regions were opened, and then filledwith metal. Finally, aluminum (Al) pad was patterned, followedby post-metallization annealing at 400 ◦C in hydrogen ambient.The memory characteristics were analyzed at room temperatureby Agilent B1500A with pulse generator.

III. RESULTS AND DISCUSSION

Fig. 2 shows the drain current–gate voltage (Id–Vg ) curvesof Co-ND MOSFET memory. In this measurement, the bidi-rectional sweeping gate voltages are applied. The holding timeis 1 s and the Vds sets on 0.1 V. The small-applied drain volt-

Fig. 2. Id –Vg characteristics of Co-ND MOSFET memory measured withdifferent bi-direction gate voltage sweeps. The holding time is 1 s and Vds is0.1 V.

Fig. 3. Retention characteristics of Co-ND MOSFET memory at room temper-ature and zero bias of drain, source, and gate. This device was programmed anderased by gate voltage of +8 V/−8 V and +10 V/−10 V, for 1 s, respectively.

age suggests that the memory device is programmed or erasedby tunneling current under positive or negative gate voltagespredominantly. The counterclockwise hysteresis loops were ob-served, which attributed to the charge trapping and distrappinginto or from Co-NDs. The hysteresis memory window appearedat sweep-gate voltage of +5 V/−5 V, and then it is positivelyrelated to the sweep-gate voltage. We found that at low sweep-gate voltage of +6 V/−6 V, the memory window of 1 V wasobtained. The extremely large memory window of 6.5 V wasobserved at +10 V/−10 V. In addition, the humps were observedwhen the sweep-gate voltage is larger than +8 V. It indicates thegeneration of gate-induced-drain-leakage (GIDL) current. It ispresumably due to the gate-edge damage, which occurs duringthe plasma-etch process [14].

Fig. 3 shows the data-retention characteristics at zero biases ofgate, source, and drain after P/E by gate voltages of +8 V/−8 Vand +10 V/−10 V for 1 s, respectively. For the case with P/Eof +8 V/−8 V, at 104 s retention, a memory window of 2.8 Vremained with a charge loss of 15%. By linear extrapolation,it is estimated roughly that after 10 years’ retention, a memorywindow of 1.78 V remained with a charge loss of 46% [15],[16]. In contrast, for the case with P/E of +10 V/−10 V for 1 s,a memory window of 4.6 V remained with a charge loss of 29%at 104 s retention time. After ten years’ retention, a memory

530 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 10, NO. 3, MAY 2011

Fig. 4. Retention time at charges loss of 20% as a function of device-bakingtemperatures. The P/E of Co-ND MOSFET was performed by +8 V/−8 V for1 s.

window of 1.95 V and a charge loss of 70% were estimated.According to the earlier results, we found that the memorywindow and retention behavior are similar with MOS memorycapacitor reported in [13]. The large memory window at 10years’ retention indicates the advantage of high work-functionCo-ND (5.0 eV) for nonvolatile-memory application. We havealso checked the temperature dependence of data retention attemperature range of room temperature to 100 ◦C. The P/E wasperformed by +8 V/−8 V for 1 s. Fig. 4 shows the retentiontime at charge loss of 20% as a function of baking tempera-tures. Using Arrhenius equation fitting, the activation energyof ∼0.56 eV was obtained. The coulomb-blockage effect willmake the increase of electron storage energy level. Accordingto that, for 2 nm Co-ND, the change of energy for one electronstorage is about 0.37 eV, e.g., the energy level of 4.63 eV. Onthe other hand, considering the thick-blocking dielectric (1 nmSiO2 / 40 nm HfO2), it is assumed that the thin-tunneling ox-ide (∼5 nm thermal SiO2) dominates the discharge process ofretention state. Therefore, two discharge models were exposed.The first is electron tunneling into the Si/SiO2 interface stateslined in silicon band. For this model, it has smaller tempera-ture dependence. The second decaying mechanism involves thethermal excitation of storage electrons from Co-NDs to inter-face states at Co-ND/silicon oxide matrix interface and thentunnels to silicon substrate conduction band. According to theearlier experimental results, the second model was suggested.The energy level of interface state at Co-ND/silicon oxide ma-trix is higher than the energy level of stored electron in Co-NDby ∼0.56 eV. In such condition, how to reduce the interfacestates at Co-ND/silicon oxide matrix becomes more critical forimproving the data-retention characteristics.

To study the P/E characteristics of the Co-ND MOSFETmemory, single P/E pulses were applied. Fig. 5 presents the P/Echaracteristics under pulses of +8 V/−8 V and +10 V/−10 V,respectively. The threshold-voltage shifts of 1.5 (programmedstate) and 1.9 V (erased state) are attained with pulse of+8 V/−8 V for 10 ms whereas 4.5 (programmed state) and 4.2 V(erased state) are attained with +10 V/−10 V for 10 ms, respec-tively. The speed of P/E is faster than other group [17]. Fur-thermore, the endurance characteristics with 106 P/E cycles areshown in Fig. 6. The P/E were performed using +10 V/−10 Vpulses for 10 ms and +8 V/−8 V pulses for 10 ms on gate,

Fig. 5. P/E characteristics of Co-ND MOSFET memory at gate voltages of+8V/−8V and +10V/−10V, respectively.

Fig. 6. Endurance characteristics of Co-ND MOSFET memory. The P/Epulses are +10V/−10V and +8V/−8V, for 10 ms, respectively.

Fig. 7. Dual-bit per cell characteristics of Co-ND MOSFET memory. Thedevice was programmed by hot electron channel injection (Vg = +6 V, Vs =0 V, Vd = +8 V, for 1 s, respectively).

respectively. The relative stable-threshold voltage (Vth ) till 106

cycles presents the excellent endurance characteristics. Evenwith the increase in the number of the pulse cycles, the Vth indi-vidual shifts to positive direction slightly. It indicates the smallamount of residual charges in Co-NDs after cycling.

Localized storage of charge obtained through channel hotelectron injection coupled with a reverse reading allows a sin-gle memory cell with discrete traps to operate as a dual-bitdevice [18]. This operation has been successfully demonstratedin the Co-ND MOSFET memory, as shown in Fig. 7. The pro-gram of Co-ND MOSFET was done by hot-electron-channelinjection using Vg of +6 V, Vs of 0 V, and Vd of +8 V for1 s, respectively. Because the electron was trapped close to thedrain region, when reading the device in forward and reverse

PEI et al.: MOSFET NONVOLATILE MEMORY WITH HIGH-DENSITY Co-NDs FLOATING GATE AND HfO2 HIGH-k BLOCKING DIELECTRIC 531

directions, the different Vth were observed. The difference ofVth between forward and reverse read is ∼0.9 V. The result indi-cates the excellent dual-bit operation, which makes the possibil-ity of ultra high-density memory capacity in further. However,the dot number involved in data storage is decreased. Therefore,the higher density nanodots formation is a challenge to realizethe dual-bit operation with scaling [4], [5].

IV. CONCLUSION

In this paper, gate-last process was used to fabricate MOS-FET memory with high-density Co-NDs floating gate and HfO2high-k blocking dielectric. A memory window as large as 6.5 Vwas obtained at sweep-gate voltage of +10 V/−10 V. At tenyears’ retention for room temperature, a memory window of1.78 V with a charge loss of 46% was estimated. Moreover, thefast P/E speed (ΔVth of 1.5 V at +8 V, 10 ms and 1.9 V at−8 V, 10 ms, respectively), excellent endurance 106 > cycles)and dual bit per cell were obtained. Those results show that theCo-NDs memory with HfO2 high-k blocking dielectric hasa good application prospect for next-generation-nonvolatilememory.

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Authors’ photographs and biographies not available at the time of publication.