Mps Ref Lect 03 Crystal Growth

54 CHAPTER 1 SEMICONDUCTOR ELECTRONICS

TABLE 1.4 Additional Properties of Silicon (Lightly Doped, at 300 K Unless Otherwise Noted)

Property

Tetrahedral radius

Pressure coefficient of energy gap

Intrinsic carrier densitya

Bandgap

Temperature coefficient of lattice mobility

Electron

Hole

Diffusion coefficient

Electron

Hole

Hardness Elastic constants

Young's modulus «111> direction)

Surface tension (at 1412°C)

Latent heat of fusion

Expansion on freezing

Cut-off frequency of lattice vibrations

Symbol Units

nm

tlEg! tlp eV (atm)-1

nj (Tin K)

tlJ.Ln/ tl T cm 2(V s K)-1

tlJ.Lp/ tl T cm2(V s K)-1

On cm2 5-1

Op cm2 5- 1

H Mohs C 11 dyne cm 2 C12

C44

Y dyne cm-2

Vo

dyne cm-2

eV

%

Hz

Values

0.117

-1.5 X 10-6

3.87 X 1016 T 3/ 2 exp [ -7~14] 4.73 x 10-4 T2

1.17- T -

-11.6

-4.3

34.6

12.3

7.0 1.656 X 1012

0.639 X 1012

0.796 x 1012

1.9 X 1012

720

0.41

9.0

1.39 X 1013

+ 651

Main Source: H. F. Wolf, Semiconductors, Wiley, New York (1971), p. 45.

Energy Levels of Elemental Impurities in Sib

Li Sb P As Bi Ni S Mn

0~033 (f039 0.044 0.049 0.069 0.18

0.35 0.37

A

0.54

Ag Pt Hg

0.33 0.33 0.37

Gap center - 0-,-5i5 0.53 S i -------------- -----------------------------------------------------------A --------------------------------------------------------------------

0.55 0.52 D

0.40 0.34 0.36

0.39 0.31 0.37 0.35 D -

D

0.26 0.24 0.22 0.16

0.065

0.045 0.057 0.03

B AI Ga In TI Co Zn Cu Au Fe 0 a a plot of n; versus T at higher temperatures is given in Figure 2.10. bThe levels below the gap center are measured from the top of the valence band and are acceptor levels unless indicated by 0 for donor level. The levels above the gap center are measured from the bottom of the conduction band and are donor levels unless indicated by A for acceptor level [10J.

2.1

2.2

2.3

2.4

2.5

2.6

2.7

THE SILICON PLANAR PROCESS

CRYSTAL GROWTH

THERMAL OXIDATION Oxidation Kinetics

LITHOGRAPHY AND PATTERN TRANSFER

DOPANT ADDITION AND DIFFUSION Ion Implantation Diffusion

CHEMICAL VAPOR DEPOSITION Epitaxy Nonepitaxial Films

INTERCONNECTION AND PACKAGING Interconnections Testing and Packaging

2.8 COMPOUND-SEMICONDUCTOR PROCESSING

2.9 NUMERICAL SIMULATION Basic Concept of Simulation Grids Process Models Device Simulation Simulation Challenges

2.10 DEVICE: INTEGRATED-CIRCUIT RESISTOR

SUMMARY

PROBLEMS

Successful engineering rests on two foundations. One is a mastery of

underlying physical concepts; a second foundation, at least of equal importance, is a

perfected technology-a means to translate engineering concepts into useful structures.

In Chapter 1 we reviewed the physical principles needed for integrated-circuit electron

ics. In this chapter we discuss the technology to produce devices in silicon, a technol

ogy now so powerful that the entire modem world has felt its impact. In addition to de

scribing IC technology as it is now practiced, we attempt to provide a perspective on

continuing developments in this fast-moving area.

Technological evolution toward integrated circuits began with development of an

understanding of diode action and the invention of the transistor in the late 1940s. At

55

56 CHAPTER 2 SILICON TECHNOLOGY

that time the semiconductor of greatest interest was germanium. Experiments with ger

manium produced important knowledge about the growth of large single crystals having

chemical purity and crystalline perfection that were previously unachievable.

Gennanium is an element that crystallizes in a diamond-like lattice structure, in which each atom forms covalent bonds with its four nearest neighbors. The crystal

structure is shown in Figure 1.8. Germanium has a band gap of 0.67 eV and an intrinsic

carrier density equal to 2.5 X 1013 cm-3 at 300 K. Because of the relatively small band

gap in germanium, its intrinsic-carrier density increases rapidly with increasing temperature, growing roughly to lOIS cm- 3 at 400 K (see Figure 1.9).

Because most devices are no longer useful when the intrinsic-carrier concentra

tion becomes comparable to the dopant density, germanium devices are limited to

operating temperatures below about 70°C (343 K). As early as 1950, the temperature

limitations of germanium devices motivated research on several other semiconductors

that crystallize with similar lattice structures but can be used at higher temperatures. In

the intervening decades technological development for integrated circuits has focused

on the elemental semiconductor silicon (Eg = 1.12 eV) and the compound semiconduc

tor gallium arsenide (Eg = 1.42 eV). Silicon is used in the overwhelming majority of integrated circuits, while compound semiconductors, such as gallium arsenide, find

application in specialized, high-performance circuits. Compound semiconductors are

especially useful in optical devices that rely on the efficient light emission from directbandgap compound semiconductors.

Most of this chapter deals with silicon technology, but the technology associated

with compound semiconductors will be briefly discussed later in this chapter. Properties

of germanium, silicon, gallium arsenide, and several other useful electronic materials

are summarized in Table 1.3 (page 52-53). Table 1.4 (page 54) lists some additional properties of silicon.

2.1 THE SILICON PLANAR PROCESS

In addition to the good semiconducting properties of silicon, the major reason for its widespread use is the ability to form on it a stable, controllable oxide film (silicon dioxide Si02) that has excellent insulating properties. This capability, which is not matched by any other semiconductor-insulator combination, makes it possible to introduce controlled amounts of dopant impurities into small, selected areas of a silicon sample while the oxide blocks the impurities from the remainder of the silicon. The ability to dope small regions of the silicon is the key to producing dense arrays of devices in integrated circuits.

Two chemical properties of the Si-Si02 system are of basic importance to silicon technology. First, selective etching is possible using liquid or gaseous etchants that attack only one of the two materials. For example, hydrofluoric acid dissolves silicon dioxide but not silicon. Second, silicon dioxide can be used to shield an underlying silicon crystal from dopant impurity atoms brought to the surface either by high-energy ion beams or from a high-temperature gaseous diffusion source.

p

b

2.1 THE SILICON PLANAR PROCESS 57

Using these features, dopant atoms can be introduced into areas on the silicon that are not shielded by thick silicon dioxide. The shielded regions can be accurately defined by using photosensitive polymer films exposed with photographic masks. The polymer pattern protects selected oxide regions on the silicon surface when it is immersed in a hydrofluoric-acid bath, or exposed to a gas-phase etchant, forming a surface consisting of bare silicon windows in a silicon-dioxide layer. This selective etching process, originally developed for lithographic printing applications, permits delineation of very small patterns. When the silicon sample is placed in an ambient that deposits dopant atoms on the surface, these atoms enter the silicon only at the exposed silicon windows.

Proper sequencing and repetition of the oxidation, patterning, and dopant-addition operations just described can be used to introduce p- and n-type dopant atoms selectively into regions having dimensions ranging down to the few hundred nanometer range. These steps are the basic elements of the silicon planar process, so called because it is a process that produces device structures through a sequence of steps carried out near the surface plane of the silicon crystal.

In addition to providing a means of limiting the area of dopant introduction, a wellformed oxide on silicon improves the electrical properties at the surface of the silicon substrate. Because of the termination of the crystal lattice of the silicon substrate, uncompleted or dangling bonds exist at an ideal free surface. As we will see in Chapter 4, these broken bonds can introduce allowed states into the energy gap of the silicon substrate at its surface and degrade the electrical behavior of device regions near the surface. However, a well-formed silicondioxide layer on the silicon surface electrically passivates almost all of these surface states, allowing nearly ideal behavior of the surface region of the silicon. Although the area density of bonds at the silicon surface is about 1015 cm-2, the number of electrically active bonds can be reduced to less than lOll cm - 2 by properly growing a silicon-dioxide layer on the surface. The ability to remove virtually all the electrically active states at the silicon surface allows the successful operation of the ubiquitous silicon metal-oxide-semiconductor (MOS) transistor, which is the basis of most large-scale integrated circuits today.

The silicon crystals used for the planar process consist of slices (called wafers) that are made from a large single crystal of silicon. Dopant atoms are typically added to the silicon by depositing them in selected regions on or near the wafer surface, and then diffusing them into the silicon. Because dopant atoms are introduced from the surface and typical diffusion dimensions are very small, the active regions of the planar-processed devices are themselves within a few micrometers* of the wafer surface. The remaining thickness (generally several hundred micrometers) serves simply as a mechanical support for the important surface region.

A major advantage of the planar process is that each fabrication step (prior to packaging) is typically applied to the entire wafer. Hence, it is possible to make and interconnect many devices with high precision to build an integrated circuit (1C). At present, individual ICs typically measure up to 20 mm on a side, so that a wafer (most often 20-30 em in diameter) can contain many ICs. There is clear economic advantage to increasing the area of each wafer and, at the same time, reducing the area of each integrated circuit built on the wafer.

The most important steps in the planar process, shown in Figure 2.1, include (a) formation of a masking oxide layer, (b) its selective removal, (c) deposition of dopant atoms on or near the wafer surface, and (d) their diffusion into the exposed silicon regions. These processes determine the location of the dopants which, in tum, detennines the electrical characteristics of the devices and ICs.

* 1 micrometer = 1 [Lm. sometimes called a micron, equals 10-4 em = 103 nm = 104 A (angstrom).

----------------------------------------,. .. ----------------------------------------------~ 58 CHAPTER 2 SILICON TECHNOLOGY

(a)

(b)

(e)

(d)

Si02 selectively removed

Dopant atoms deposited on exposed surfaces

FIGURE 2.1 Basic fabrication steps in the silicon planar process: (a) oxide formation, (b) selective oxide removal, (c) deposition of dopant atoms on wafer, (d) diffusion of dopant atoms into exposed regions of silicon.

Refinements of the planar process and, along with it, the growth of silicon-based electronics has been amazingly rapid and continuous. Figure 2.2 gives some perspective to the development of silicon integrated-circuit technology over the past 40 years.

The minimum feature size on an integrated circuit has continued to evolve at a rapid rate, decreasing from 8 /-Lm in 1969 to 130 nm* today. The rate of evolution can be appreciated by plotting the minimum feature size (on a logarithmic scale) versus year of first commercial production, as shown in Figure 2.2j. The straight line on this plot indicates the exponential decrease in the minimum feature size. The exponential change was first quantified by Gordon Moore of Intel Corporation and is known as "Moore's Law." (Moore's law is so well recognized and frequently cited that it has even been mentioned in the cartoon "Dilbert" [1]. Along with the rapid decrease in minimum feature size, the size of the IC chip continues to increase, although less rapidly than the minimum feature size decreases. Because of the combination of smaller features and larger chips, the number

* 1 nanometer (nm) = 10-9 m = 10-7 cm = 10-1 fLm.

hr


FIGURE 2.2 Evolution of Ie technology. (a) First commercial silicon planar transistor (1959) (outer diameter 0.87 mm). (b) Diode-transistor logic (DTL) circuit (1964) (chip size 1.9 mm square). (c) 256-bit bipolar random access memory (RAM) circuit (1970) (chip size 2.8 x 3.6 mm). (d) VLSI central-processor computer chip containing 450,000 transistors (1981). The different functions carried out by the IC are labeled on the figure (chip size 6.3 mm square). [(a), (b)' (c) courtesy of B.E. Deal-Fairchild Semiconductor, (d) Courtesy of Hewlett-Packard Co.l (e) Block diagram of Pentium 4 processor with 42 million transistors (2000); the corresponding chips photo is shown on the book cover. (Courtesy of Intel Corporation.) (f) Minimum feature size versus year of first commercial production. (g) Another embodiment of Moore's law shows that the number of transistors per chip has doubled every 18-24 months for approximately 30 years. (h) Along with decreasing feature size, the number of electrons in each device decreases. [(f}-(h) adapted from Mark Bohr, Intel; Howard Huff, Sematech;

Joel Birnbaum, Hewlett-Packard; Motorola.l

t' II ;; '1, '~

II"


(e)

10 11m

OJ N

'u; 111m ~

" ;;; ~

E " .5 100nm c

::§

10nmL-____ L_ ____ L_ ____ L_ __ ~ ______ L_ ____ L_ ________ ~

1964 1970 1976 1982 1988 1994 2000 2006 2012

Year

(j)

FIGURE 2.2 (continued)

of transistors on an Ie chip increases even more rapidly--doubling every 18-24 months (Figure 2.2g). This rapid increase is made possible by continuing technological development, while the basic physics of the transistors remains relatively constant. (However, secondary effects that were less important in large transistors can dominate the behavior of smaller transistors.)

Because different manufacturing equipment is often needed to produce circuits with smaller features, the decrease of feature size is not continuous. Rather, the area of a transistor for each device "generation" decreases by a ratio that provides enough benefit to justify the cost of new equipment. Typically the area decreases by a factor of two, so the linear dimension decreases by a factor of 1.4 (i.e., the dimension "scales" by 0.7). Device features of 60 nm are produced today. and features of 20-30 nm have been demonstrated [2].

hn


109~-----------------------------------------------=~

.~ 107~-------------------------------.~--------------~ -5 g, ~ 106

.~ § ~ 105~------------~~--------------------------------~

<l) u .;;: OJ

"'" '" OJ 0..

l!l g u

cll

lif~----~~----------------------------------------~

1972 1976 1980 1984 1988 1992 1996 2000 2004 2008

Year

(g)

104

103

102

101

~ . T . I h' ranslstors per C lp

~6M~ 256M

~ ... IG

~ ~ ~ =--- - ~ .... ....

10° :1 10-1

1988 1992 1996 2000 2004 2008 2012

Year

(h)

-

-

.... .... .... .,.

2016 2020

FIGURE 2.2 (continued)

Once Moore's law was well accepted, it became almost a self-fulfilling prophecy. By extrapolating from the past evolution of feature size shown in Figure 2.2f, a target value for minimum feature size is determined for each future year. Projections for feature size and other physical and electrical characteristics have been quantified in an "International Technology Roadmap for Semiconductors" (ITRS) [3], which is updated frequently. Semiconductor manufacturers then devote the resources needed to develop the technology required to produce features of the predetermined size. In fact, the changes can sometimes exceed the predicted rate of improvement. If the predetermined size is typical for the industry, then each company tries to develop the technology more rapidly than predicted to give it a competitive advantage in the market.

Device scaling cannot continue indefinitely, however. It will be limited by two factors. First, as the device features scale to smaller dimensions, the number of electrons within each transistor decreases, as shown in Figure 2.2h. As the number of electrons n


decreases, the statistical fluctuations in the number (~vn) becomes an increasing fraction of the total, limiting circuit performance and making circuit design more difficult. Several years ago, these statistical fluctuations began to impact the performance of analog circuits. Within a few years, similar fluctuations will influence digital circuit design. Considerably after statistical fluctuations become important, we will reach the time at which each transistor contains only one electron (perhaps about 2015). At that point, the entire concept of electronic devices must change. A number of different alternatives are being investigated in advanced research laboratories, but no favored approach has yet emerged.

Second, even in the shorter term with conventional devices, each generation of technology becomes more difficult and more expensive. The lithography needed to define increasingly small dimensions is often limiting. Eventually, the cost of technology development and manufacturing equipment is likely to limit the further evolution of IC technology. A modern IC manufacturing facility can cost several billion U.S. dollars today, and the cost is continuing to increase. The high cost of the manufacturing facilities limits the number of companies that can afford to manufacture ICs. In fact, many companies have the circuits they design manufactured by "foundries" that specialize in high-volume manufacturing of ICs for other companies.

However, even with these future limitations, the planar process will continue to dominate electronics for a number of years. The benefits it has provided for computers, communications, and consumer products have led to the continuing huge investment in research and development and manufacturing facilities. The planar process is the foundation for the production of silicon integrated circuits and continually evolves to allow production of increasingly complex circuits. Making the best use of its many degrees of freedom in understanding and designing devices requires a fairly thorough understanding of the basic elements of silicon technology. Much of the remainder of this chapter is directed toward providing such an understanding and a basis for the discussion of devices in the following chapters.

2.2 CRYSTAL GROWTH

Silicon used for the production of integrated circuits consists of large, high-quality, single crystals [4]. What is meant by "high quality" can be better understood from a brief consideration of the ultimate requirements placed on the silicon.

Typical IC applications require dopant concentrations ranging from roughly 1015 to 1020 atoms cm - 3• To control device properties, any unintentional or background concentrations of electrically active impurity atoms should be at least two orders of magnitude lower than the minimum intentional dopant concentration-that is, about 1013 cm-3 or lower. Because silicon contains roughly 5 X 1022 atoms cm- 3, the presence of only about one unintentional, electrically active, impurity atom per billion silicon atoms can be tolerated. This high purity is well beyond that required for the raw material in virtually any other industry; the routine production of material of this quality for the manufacture of integrated circuits demonstrates the extraordinary refinement of silicon technology.

High-purity silicon is obtained from two common materials: silicon dioxide (found in common sand) and elemental carbon. In a high-temperature (~2000°C) electric-arc furnace, the carbon reduces the silicon dioxide to elemental silicon, which condenses as about 90% pure, metallurgical-grade silicon-still not pure enough for use in semiconductor devices. The metallurgical-grade silicon is purified by converting it into liquid trichlorosilane (SiHCI3), which can be purified. Selective distillation (fractionation) separates the

...

2.2 CRYSTAL GROWTH 63

trichlorosilane from any other chloride complexes. The purified trichlorosilane is then reduced by hydrogen to form high-purity, semiconductor-grade, solid silicon. At this point, the silicon is polycrystalline, composed of many small crystals with random orientations. This elemental poly crystalline silicon, also called polysilicon, is usually deposited on a high-purity rod of semiconductor-grade silicon to avoid contamination.

The silicon is then formed into a large (about 20-30 cm diameter), nearly perfect, single crystal because grain boundaries and other crystalline defects degrade device performance. Sophisticated techniques are needed to obtain single crystals of such high qUality. These crystals can be formed-by either the Czochralski (CZ) technique or the float-zone (FZ) method.

Czochralski Silicon. In the Czochralski technique, which is most widely used to form the starting material for integrated circuits, pieces of the polysilicon rod are first melted in a fused-silica crucible in an inert atmosphere (typically argon) and held at a temperature just above 1412°C, the melting temperature of silicon (Figure 2.3).

A high-quality seed crystal with the desired crystalline orientation is then lowered into the melt while being rotated, as indicated in Figure 2.3a. The crucible is simultaneously turned in the opposite direction to induce mixing in the melt and to minimize temperature nonunifornlities. A portion of the seed crystal is dissolved in the molten silicon to remove the strained outer portions and to expose fresh crystal surfaces. The seed is then slowly raised (or pulled) from the melt. As it is raised, it cools, and material from the melt solidifies on the seed, forming a larger crystal, as shown in Figure 2.3b. Under the carefully controlled conditions maintained during growth, the new silicon atoms continue the crystal structure of the already solidified material. The desired crystal diameter is obtained by controlling the pull rate and temperature with automatic feedback mechanisms. In this manner cylindrical, single-crystal ingots of silicon can be fabricated. As crystal-growing technology has developed, the diameter of the cylindrical crystals has increased progressively from a few mm to the 20 or 30 cm common today.

0

0

0

0

0 Molten silicon

0

(al

Seed crystal

o

o

o Heating coils o

o

o

0

0

0

0

0 Molten silicon

0

Solid-liquid interface

(b)

Solid silk:on

FIGURE 2.3 Formation of a single-crystal semiconductor ingot by the Czochralski process: (a) initiation of the crystal by a seed held at the melt surface, (b) withdrawal of the seed "pulls" a single crystal.

o

o

o

o

o

o


For many integrated-circuit processes, an initial dopant density of about 10 15 cm - 3

is desired in the silicon. This dopant concentration is obtained by incorporating a small, carefully controlled quantity of the desired dopant element, such as boron or phosphorus, into the melt. Typically, dopant impurities weighing about one-tenth milligram must be added to each kilogram of silicon. For accurate control, small quantities of heavily doped silicon, rather than the elemental dopant, are usually added to the undoped melt. The dopant concentration in the pulled crystal of silicon is always less than that in the melt because dopant is rejected from the growing crystal into the melt as the silicon solidifies. This segregation causes the dopant concentration in the melt to increase as the crystal grows, and the seed end of the crystal is less heavily doped than is the tail end. Slight dopant-concentration gradients can also exist along the crystal radius in Czochralski silicon.

Czochralski silicon contains a substantial quantity of oxygen, resulting from the slow dissolution of the fused-silica (silicon dioxide) crucible that holds the molten silicon. Oxygen does not contribute significantly to the net dopant density in the moderately doped wafers used for silicon integrated circuits. However, the typical inclusion of about 1018 cm-3 oxygen atoms (the solid solubility of oxygen in silicon at the solidification temperature) in silicon crystals produced by the Czochralski process can be used to control the movement of unintentional impurities (typically metals) in IC wafers. At the temperatures used in integrated-circuit processing, oxygen can precipitate, forming sites on which other impurities tend to accumulate. If the oxygen precipitates are located within an active device, they degrade its performance. However, if they are remote from active devices, precipitates can function as gettering sites for unwanted impurities, attracting them away from electrically active regions and improving device properties. Control of the location and size of the oxygen precipitates is important in determining the uniformity of device properties in high-density integrated circuits.

Convective flow of the molten silicon accelerates erosion of the crucible, increasing the oxygen content in the melt and in the solidifying crystal. The convective flow can also contribute to instabilities in the crystal growth process, degrading the structure of the growing crystal. The convective flow can be suppressed by superposing magnetic fields on the melt. This magnetically confined Czochralski growth technique offers the possibility of improved control over the crystal-growth process and increased purity of the resulting crystal.

A small fraction of the included oxygen, about 0.01 % of the total, can act as donors after moderate-temperature heat treatments. This small concentration (about 10 14 cm-3)

does not appreciably alter the resistivity of most integrated-circuit silicon. However, for the high-resistivity (20-100 O-cm) silicon used to produce power devices and for other specialized applications, oxygen can become a problem. For this reason, high-resistivity silicon is usually formed by the float-zone process.

Float-Zone Silicon. In the float-zone process, a rod of cast polycrystalline silicon is held in a vertical position and rotated while a melted zone (between I and 2 cm long) is slowly passed from the bottom of the rod to the top, as shown in Figure 2.4. The melted region is heated [usually by a radio-frequency (RF) induction heater] and moved through the rod starting from a seed crystal that initiates crystallization. The impurities tend to segregate in the molten portion so that the solidifying silicon is purified. In contrast to Czochralski-processed silicon, oxygen is not introduced into float-zone silicon because the silicon is not held in an oxygen-containing crucible. Although it is a more costly process and limited to smaller-diameter ingots, the silicon produced by the float-zone process typically contains about 1 % as much oxygen as that produced by the Czochralski

f

b

Polycrystalline cast rod --+--

Molten zone

Holder

Heating coil

Single-crystal silicon

Seed crystal

Holder

2.2 CRYSTAL GROWTH 65

FIGURE 2.4 The float-zone process. A molten zone passes through a polycrystalline-silicon rod, and a single crystal grows from a seed at the bottom end.

method, and other impurity concentrations are also reduced. Multiple passes of the molten zone can be used to produce silicon with resistivities above 104 O-cm.

Wafer Production. Once the single-crystal ingot is grown and ground to a precise diameter, it is sliced with a diamond saw into thin, circular wafers. The wafers are chemically etched to remove sawing damage and then polished with successively finer polishing grits and chemical etchants until a defect-free, mirror-like surface is obtained. The wafers are then ready for device fabrication.

Before slicing, index marks are placed on the wafer to facilitate the orientation of processed circuits along specific crystal directions. In particular, edges of an area on the wafer called a die or a chip are typically aligned in directions along which the wafer readily breaks so that the dice can be separated from one another after planar processing is completed. This separation is often accomplished by scribing between them with a sharp stylus and breaking them apart, so the orientation of the easy cleavage planes is important. On smaller wafers the crystal directions are indicated by grinding aflat on the wafer, usually perpendicular to an easy cleavage direction. In most cases, the primary flat is formed along a (110) direction. A smaller secondary flat is sometimes added to identify the orientation and conductivity type of the wafer, as shown in Table 2.1. On larger wafers, using wafer flats would appreciably decrease the wafer area and the number of chips on the wafer. Therefore, the wafer flats are omitted on larger wafers, and the crystal axes are indicated by a small notch placed at the edge of the wafer.


TABLE 2.1 Location of Secondary Wafer Flat

Secondary Flat Crystal Conductivity (Relative to Orientation Type Primary Flat)

(100) n 1800

(100) P 90°

(111 ) n 45°

(111 ) P No secondary flat

After slicing, a unique wafer number is often marked on the wafer surface by vaporizing small spots of silicon with a laser. The marks identify the manufacturer, ingot, dopant species, and crystal orientation. Other digits are unique to a wafer, allowing each wafer to be identified at any point in the wafer-fabrication process. The laser marks can be read both manually by equipment operators and also by automated process equipment. The laser marks are added before the wafer is etched and polished so that strain from the marking process can be removed by chemical etching and stray spattered material does not contaminate the fine surface finish after polishing.

2.3 THERMAL OXIDATION

An oxide layer about 2 nm thick quickly forms on the surface of a bare silicon wafer in room-temperature air. The thicker (typically 8 nm to 1 ,um) silicon dioxide layers used to protect the silicon surface during dopant incorporation can be formed either by thermal oxidation or by deposition. When silicon dioxide is formed by deposition, both silicon and oxygen are conveyed to the wafer surface and reacted there (Sec. 2.6). In thermal oxidation, however, there is a direct reaction between atoms near the surface of the wafer and oxygen supplied in a high-temperature furnace. Thermally grown oxides are generally of a higher quality than deposited oxides. Although their structure is amorphous, they typically have an exact stoichiometric ratio (Si02), and they are strongly bonded to the silicon surface. The interface between silicon and thermally grown Si02 has stable and controllable electrical properties. As we will see in Chapter 8, the quality of this excellent semiconductor-insulator interface is fundamental to the successful production of metal-ox ide-semiconductor (MaS) transistors.

To form a thermal oxide, the wafer is placed inside a quartz tube that is set within the cylindrical opening of a resistance-heated furnace. This furnace can be oriented horizontally, as shown in Figure 2.5, or vertically. The wafer surface is usually perpendicular to the main gas tlow. Temperatures in the range of 850 to 1100°C are typical, the reaction proceeding more rapidly at higher temperatures. Silicon itself does not melt until the temperature reaches 1412°C, but oxidation temperatures are kept considerably lower to reduce the generation of crystalline defects and the movement of previously introduced dopant atoms. In addition, the quartz furnace tube and other fixtures start to soften and degrade above 1150°C.

The oxidizing ambient can be dry oxygen, or it can contain water vapor, which is generally produced by reaction of oxygen and hydrogen in the high-temperature furnace. Use of such pyrogenic steam requires careful safety procedures to handle explosive hydrogen gas, and a slight excess of oxygen is generally introduced to avoid having unreacted

2.3 THERMAL OXIDATION 67

~~--~~-------------------------------Silicon wafers

lJJJJJJ))} ~-~-----------------------/-------

Quartz carrier

Furnace

I I I J

J

\ \ \ Quartz

tube

FIGURE 2.5 An insulating layer of silicon dioxide is grown on silicon wafers by exposing them to oxidizing gases in a high-temperature furnace.

hydrogen in the furnace. A steam environment can also be formed by passing high-purity, dry oxygen or nitrogen through water heated almost to its boiling point. The overall oxidation reactions are

(2.3.1 a)

and

(2.3.lb)

Oxidation proceeds much more rapidly in a steam ambient, which is consequently used for the formation of thicker protective layers of silicon dioxide. Growth of a thick oxide in the slower, dry-oxygen environment can lead to undesirable movement (redistribution) of impurities introduced into the wafer during previous processing.

Oxidation takes place at the Si-Si02 interface so that oxidizing species must diffuse through any previously formed oxide and then react with silicon at this interface (Figure 2.6). At lower temperatures and for thinner oxides, the surface reaction rate at the Si-Si02 interface limits the growth rate, and the thickness of the oxide layer increases linearly with increasing oxidation time.

At higher temperatures and for thicker oxides, the oxidation process is limited by diffusion of the oxidizing species through the previously formed oxide. In this case the grown oxide thickness is approximately proportional to the square root of the oxidation time. This square-root dependence is characteristic of diffusion processes and sets a practical upper limit on the thickness that can be conveniently obtained.

Gas stream I .F(l)

t F (2) Silicon dioxide film

Silicon wafer

FIGURE 2.6 Three fluxes that characterize the oxidation rate: F{ 1)

the flow from the gas stream to the surface, F(2) the diffusion of oxidizing species through the already formed oxide, and F(3) the reaction at the Si-Si02 interface. The concentration of the oxidizing species varies in the film from Co near the gas interface to Ci near the silicon interface.

51

Chapter

3Crystal Growth and

Silicon Wafer Preparation

Overview

In this chapter, the preparation of semiconductor-grade silicon fromsand, its conversion into crystals and wafers (material preparationstage), and the processes required to produce polished wafers (crystalgrowth and wafer preparation) are explained.

Objectives

Upon completion of this chapter, you should be able to:

1. Explain the difference between crystalline and noncrystalline ma-terials.

2. Explain the differences between a polycrystalline and a singlecrystalline material.

3. Draw a diagram of the two major wafer crystal orientations usedin semiconductor processing.

4. Explain the Czochralski, float zone and liquid crystal encapsulatedCzochralski methods of crystal growing.

5. Draw a flow diagram of the wafer preparation process.

6. Explain the use and meaning of the flats or notches ground on wa-fers.

7. Describe the benefits in the wafer fab process that come from edge-rounded wafers.

52 Chapter 3

8. Describe the benefits in the wafer fab process that come from flatand damage-free wafer surfaces.

Introduction

The evolution of higher-density and larger-size chips has requiredthe delivery of larger diameter wafers. Starting with 1-in diameterwafers in the 1960s, the industry is now introducing 300-mm (12-in)diameter wafers into production lines. According the InternationalTechnology Roadmap for Semiconductors, 300-mm wafers will be thestandard diameter until about 2007, and 400- or 450-mm diameterwafers are predicted for the far future (Figure 3.1). Larger-diameterwafers are necessary to accommodate increasing chip sizes with costeffective wafer fabrication processes (see Chaps. 6 and 15). The chal-lenges in wafer preparation are formidable. In crystal growth, the is-sues of structural and electrical uniformity and contaminationbecome challenges. In wafer preparation, flatness, diameter control,and crystal integrity are issues. Larger diameters are heavier, whichrequires more substantial process tools and, ultimately, full automa-tion. A production lot of 300-mm diameter wafers weighs about 20 lb(7.5 kg) and can have a production value of half a million dollars ormore.1 These challenges coexist with ever tightening specificationsfor almost every parameter. Keeping abreast of these challenges andproviding ever larger diameter wafers is a key to continued micro-chip evolution.

Semiconductor Silicon Preparation

Semiconductor devices and circuits are formed in and on the surface ofwafers of a semiconductor material, usually silicon. Those wafersmust have very low levels of contaminants, be doped to a specified re-sistivity level, have a specific crystal structure, be optically flat, andmeet a host of other mechanical and cleanliness specifications. Manu-facture of IC grade silicon wafers proceeds in four stages.

Figure 3.1 Wafer diameters. (Courtesy ofSIA.)

Year of production 2001 2006 2012

Wafer diameter (mm) 300 300 450

Crystal Growth and Silicon Wafer Preparation 53

Silicon wafer preparation stages

■ Conversion of ore to a high-purity gas

■ Conversion of gas to polysilicon silicon

■ Conversion of polysilicon silicon to a single crystalline, doped crystalingot

■ Preparation of wafers from the crystal ingot

The first stage of semiconductor manufacturing is the extraction andpurification of the raw semiconductor material(s) from the earth. Puri-fication starts with a chemical reaction. For silicon, it is the conver-sion of the ore to a silicon-bearing gas such as silicon tetrachloride ortrichlorosilane. Contaminants, such as other metals, are left behind inthe ore remains. The silicon bearing gas is then reacted with hydrogen(Fig. 3.2) to produce semiconductor grade silicon. The silicon producedis 99.9999999 percent pure, one of the purist materials on Earth.2 Ithas a crystal structure known as polycrystalline or polysilicon.

Crystalline Materials

One way that materials differ is in the organization of their atoms. Insome materials, such as silicon and germanium, the atoms are ar-ranged into a very definite structure that repeats throughout the ma-terial. These materials are called crystals.

Materials without a definite periodic arrangement of their atomsare called noncrystalline or amorphous. Plastics are examples ofamorphous materials.

Unit cells

There are actually two levels of atomic organization possible for crys-talline materials. First is the organization of the individual atoms.The atoms in a crystal arrange themselves at specific points in astructure known as a unit cell. The unit cell is the first level of orga-nization in a crystal. The unit cell structure is repeated everywherein the crystal.

Figure 3.2 Hydrogen reduction of trichlorosilane.

54 Chapter 3

Another term used to reference crystal structures is lattice. A crys-talline material is said to have a specific lattice structure and that theatoms are located at specific points in the lattice structure.

The number of atoms, relative positions, and binding energies be-tween the atoms in the unit cell gives rise to many of the characteris-tics of the material. Each crystalline material has a unique unit cell.Silicon atoms have 16 atoms arranged into a diamond structure(Fig. 3.3). GaAs crystals have 18 atoms in a unit cell configurationcalled a zincblend (Fig. 3.4).

Poly and single crystals

The second level of organization within a crystal is related to the orga-nization of the unit cells. In intrinsic semiconductors, the unit cellsare not in a regular arrangement to each other. The situation is simi-lar to a disorderly pile of sugar cubes, with each cube representing aunit cell. A material with such an arrangement has a polycrystallinestructure.

The second level of organization occurs when the unit cells (sugarcubes) are all neatly and regularly arranged relative to each of theothers (Fig. 3.5). Materials thus arranged have a single (or mono-)crystalline structure.

Figure 3.3 Unit cell of silicon.

Figure 3.4 GaAs crystal struc-ture.


Single-crystal materials have more uniform and predictable proper-ties than polycrystalline materials. The structure allows a uniformand predictable electron flow in semiconductors. At the end of the fabprocess, crystal uniformity is essential for separating the wafer intodie with non-ragged edges (see Chapter 18).

Crystal Orientation

In addition to the requirement of a single-crystal structure for a wafer,there is the requirement of a specific crystal orientation. This conceptcan be visualized by considering slicing the single crystalline block inshown in Fig. 3.5. Slicing it in the vertical plane would expose one setof planes, while slicing it corner-to-corner would expose a differentplane. Each plane is unique, differing in atom count and binding ener-gies between the atoms. Each has different chemical, electrical, andphysical properties that are imparted to the wafers. Specific crystalorientations are required for the wafers.

Crystal planes are identified by a series of three numbers known asMiller Indices. Two simple cubic unit cells nestled into the origin of aXYZ coordinate system are shown in Fig. 3.6. The two most commonorientations used for silicon wafers are the ⟨100⟩ and the ⟨111⟩ planes.The plane designations are verbalized as the one-oh-oh plane and theone-one-one plane. The brackets indicate that the three numbers areMiller indices.

⟨100⟩ oriented wafers are used for fabricating MOS devices and cir-cuits, while the ⟨111⟩ oriented wafers are used for bipolar devices andcircuits. GaAs wafers are also cut along the ⟨100⟩ planes of the crystal.

Note that the ⟨100⟩ plane in Fig. 3.6 has a square shape, while the⟨111⟩ plane is triangular in shape. These orientations are revealedwhen wafers are broken as shown in Fig. 3.7. The ⟨100⟩ wafers break

Figure 3.5 Poly- and single-crystal structures.

56 Chapter 3

into quarters or with right angle (90°) breaks. The ⟨111⟩ wafers breakinto triangular pieces.

Crystal Growth

Semiconductor wafers are cut from large crystals of the semiconduct-ing material. These crystals, also called ingots, are grown from chunksof the intrinsic material, which have a polycrystalline structure andare undoped. The process of converting the polycrystalline chunks to alarge crystal of single-crystal structure, with the correct orientationand the proper amount of N- or P-type, is called crystal growing.

Three different methods are used to grow crystals: the Czochralski,liquid encapsulated Czochralski, and float zone techniques.

Figure 3.6 Crystal planes.

Figure 3.7 Wafer orientation in-dicators.


Czochralski (CZ) method

The majority of silicon crystals are grown by the CZ method (Fig. 3.8).The equipment consists of a quartz (silica) crucible that is heated bysurrounding coils that carry radio frequency (RF) waves or by electricheaters. The crucible is loaded with chunks of polycrystalline of thesemiconductor material and small amounts of dopant. The dopant ma-terial is selected to create either an N-type or P-type crystal. First, thepoly and dopants are heated to the liquid state at 1415°C (Fig. 3.9).Next, a seed crystal is positioned to just touch the surface of the liquidmaterial (called the melt). The seed is a small crystal that has thesame crystal orientation required in the finished crystal. Seeds can be

Figure 3.8 Czochralski crystal-growing system.

Figure 3.9 Crystal growth from a seed.

58 Chapter 3

produced by chemical vapor techniques. In practice, they are pieces ofpreviously grown crystals and are reused.

Crystal growth starts as the seed is slowly raised above the melt.The surface tension between the seed and the melt causes a thin filmof the melt to adhere to the seed and then to cool. During the cooling,the atoms in the melted semiconductor material orient themselves tothe crystal structure of the seed. The net effect is that the crystal ori-entation of the seed is propagated in the growing crystal. The dopantatoms in the melt become incorporated into the growing crystal, creat-ing an N- or P-type crystal.

To achieve doping uniformity, crystal perfection, and diameter con-trol, the seed and crucible (along with the pull rate) are rotated in op-posite directions during the entire crystal-growing process. Processcontrol requires a complicated feedback system integrating the pa-rameters of rotational speed, pull speeds, and melt temperature.

The crystal is pulled in three sections. First a thin neck is formed,followed by the body of the crystal ending with a blunt tail. The CZmethod is capable of producing crystals several feet in length and withdiameters up to 12 or more inches. A crystal for 200-mm wafers willweigh some 450 lb (168 kg) and take three days to grow.

Liquid encapsulated Czochralski (LEC)

LEC crystal growing3 is used for the growing of gallium arsenide crys-tals. It is essentially the same as the standard CZ process but with amajor modification for gallium arsenide. The modification is requiredbecause of the evaporative property of the arsenic in the melt. At thecrystal growing temperature, the gallium and arsenic react, and thearsenic can evaporate, resulting in a nonuniform crystal.

Two solutions to the problem are available. One is to pressurize thecrystal growing chamber to suppress the evaporation of the arsenic.The other is the LEC process (Fig. 3.10). LEC uses a layer of boron tri-oxide (B2O3) floating on top of the melt to suppress the arsenic evapo-ration. In this method, a pressure of about one atmosphere is requiredin the chamber.

Float zone

Float zone crystal growth is one of several processes explained in thistext that were developed early in the history of the technology and arestill used for special needs. A drawback to the CZ method is the inclu-sion of oxygen from the crucible into the crystal. For some devices,higher levels of oxygen are intolerable. For these special cases, the


crystal might be grown by the float zone technique, which produces alower oxygen content crystal.

Float zone crystal growth (Fig. 3.11) requires a bar of the polysiliconand dopants that have been cast in a mold. The seed is fused to oneend of the bar and the assemblage placed in the crystal grower. Con-version of the bar to a single-crystal orientation starts when an RF coilheats the interface region of the bar and seed. The coil is then movedalong the axis of the bar, heating it to the liquid point a small sectionat a time. Within each molten region, the atoms align to the orienta-tion started at the seed end. Thus, the entire bar is converted to a sin-gle crystal with the orientation of the starting seed.

Float zone crystal growing cannot produce the large diameters thatare obtainable with the CZ process, and the crystals have a higher dis-location density. But the absence of a silica (silicon) crucible yieldshigher-purity crystals with lower oxygen content. Lower oxygen al-lows crystals with higher that find use in semiconductor devices suchas power thyristors and rectifiers. The two methods are compared inFig. 3.12.

Crystal and Wafer Quality

Semiconductor devices require a high degree of crystal perfection. Buteven with the most sophisticated techniques, a perfect crystal is unob-tainable. The imperfections, called crystal defects, result in processproblems by causing uneven silicon dioxide film growth, poor epitaxialfilm deposition, uneven doping layers in the wafer, and other prob-lems. In finished devices, the crystal defects cause unwanted current

Figure 3.10 LEC system of crys-tal growth.

60 Chapter 3

leakage and may prevent the devices from operating at required volt-ages. There are three major categories of crystal defects:

1. Point defects

2. Dislocations

3. Growth defects

Figure 3.11 Float zone crystal-growing system.

Figure 3.12 Comparison of CZand float crystal-growing meth-ods.


Point defects

Point defects come in two varieties. One comes when contaminants inthe crystal become jammed in the crystal structure, causing strain.The second is known as a vacancy. In this situation, there is an atommissing from a location in the structure (Fig. 3.13).

Vacancies are natural phenomena that occur in every crystal. Unfor-tunately, vacancies occur whenever a crystal or wafer is heated andcooled, such as in the fabrication process. The minimization of vacan-cies is one of the driving forces behind the desire for low-temperatureprocessing.

Dislocations

Dislocations are misplacements of the unit cells in a single crystal.They can be imagined as a orderly pile of sugar cubes with one of thecubes slightly out of alignment with the others.

Dislocations occur from growth conditions and lattice strain in thecrystal. They also occur in wafers from physical abuse during the fabprocess. A chip or abrasion of the wafer edge serves as a lattice strainsite that can generate a line of dislocations that progresses into thewafer interior with each subsequent high-temperature processing ofthe wafer. Wafer dislocations are revealed by a special etch of the sur-face. A typical wafer has a density of 200 to 1000 dislocations persquare centimeter.

Etched dislocations appear on the surface of the wafer in shapes in-dicative of their crystal orientation. ⟨111⟩ wafers etch into triangulardislocations, and ⟨100⟩ wafers show “squarish” etch pits (Fig. 3.7).

Growth defects

During crystal growth, certain conditions can result in structural de-fects. One is slip, which refers to the slippage of the crystal alongcrystal planes (Fig. 3.14). Another problem is twinning. This is a sit-uation in which the crystal grows in two different directions from thesame interface. Both of these defects are cause for rejection of thecrystal.

Figure 3.13 Vacancy crystal de-fect.

62 Chapter 3

Wafer Preparation

End cropping

After removal from the crystal grower, the crystal goes through a se-ries of steps that result in the finished wafer. First is the cropping offof the crystal ends with a saw.

Diameter grinding

During crystal growth, there is a diameter variation over the length ofthe crystal (Fig. 3.15). Wafer fabrication processing, with its variety ofwafer holders and automatic equipment, requires tight diameter con-trol to minimize warped and broken wafers.

Diameter grinding is a mechanical operation performed in a center-less grinder. This machine grinds the crystal to the correct diameterwithout the necessity of clamping it into a lathe-type grinder with afixed center point—although lathe-type grinders are used.

Crystal orientation, conductivity, and resistivity check

Before the crystal is submitted to the wafer preparation steps, it isnecessary to determine whether it meets orientation and resistivityspecifications.

The crystal orientation (Fig. 3.16) is determined by either X-ray dif-fraction or collimated light refraction. In both methods, an end of thecrystal is etched or polished to remove saw damage. Next, the crystalis mounted in the refraction apparatus and the X-rays or collimatedlight reflected off the crystal surface onto a photographic plate (X-rays) or screen (collimated light). The pattern formed on the plate or

Figure 3.14 Crystal slip.

Figure 3.15 Crystal diametergrinding.


screen is indicative of the crystal plane (orientation) of the grown crys-tal. The pattern shown in Fig. 3.16 is representative of a ⟨100⟩ orienta-tion.

Most crystals are purposely grown several degrees off the major⟨111⟩ or ⟨100⟩ plane. This off-orientation provides several benefits inwafer fabrication processing, particularly ion implantation. The rea-sons are covered in the applicable process chapters.

The crystal is positioned on a slicing block to ensure that the waferswill be cut from the crystal in the correct orientation.

Because each crystal is doped, an important electrical check is theconductivity type (N or P) to ensure that the right dopant type wasused. A hot-point probe connected to a polarity meter is used to gener-ate holes or electrons (depending on the type) in the crystal. The con-ductivity type is displayed on the meter.

The amount of dopant put into the crystal is determined by a resis-tivity measurement using a four-point probe. See Chapter 13 for a de-scription of this measurement technique. The curves presented inChapter 2 (Fig. 2.7) show the relationship between resistivity and dop-ing concentration for N- and P-type silicon.

The resistivity is checked along the axis of the crystal due to dopantvariation during the growing process. This variation results in wafersthat fall into several resistivity specification ranges. Later in the pro-cess, the wafers will be grouped by resistivity range to meet customerspecifications.

Grinding orientation indicators

Once the crystal is oriented on the cutting block, a flat is ground alongthe axis (Fig. 3.17). This flat will show up on each of the wafers and iscalled the major flat. The position of the flat is along one of the majorcrystal planes, as determined by the orientation check.

In the fabrication process, the flat functions as a visual reference tothe orientation of the wafer. It is used to place the first pattern maskon the wafer so that the orientation of the chips is always to a majorcrystal plane.

Figure 3.16 Crystal orientationdetermination.

64 Chapter 3

On most crystals, there is a second, smaller, secondary flatground on the edge. The position of the secondary flat to the majorflat is a code that tells the wafer fabrication department both theorientation and conductivity type of the wafer. The code is shown inFig. 3.18.

For larger wafer diameters, a notch is ground on the crystal to in-dicate the wafer crystal orientation (Fig. 3.17). In some cases, a sim-ple notch is ground into the crystal to act as a production orientationlocator.

Wafer Slicing

The wafers are sliced from the crystal with the use of diamond-coatedinside diameter saws (Fig. 3.19). These saws are thin circular sheetsof steel with a hole cut out of the center. The inside of the hole is thecutting edge and is coated with diamonds. An inside diameter saw hasrigidity, but without being very thick. These factors reduce the kerf(cutting width) size which in turn prevents sizable amounts of thecrystal being wasted by the slicing process.

For 300-mm diameter wafers, wire saws are used to ensure flatsurfaces with little tapering and with a minimal amount of “kerf”loss.

Figure 3.17 Crystal flat grind-ing.

Figure 3.18 Wafer flat locations.


Wafer Marking

Large-area wafers represent a high value in the wafer fabrication pro-cess. Identifying them is necessary to prevent misprocessing and tomaintain accurate tracking. Laser marking, using bar codes and adata matrix code4 (Fig. 3.20), is used. Laser dots are the agreed uponmethod for 300-mm wafers.

Rough Polish

The surface of a semiconductor wafer has to be free of irregularitiesand saw damage and must be absolutely flat. The first requirementcomes from the very small dimensions of the surface and subsurfacelayers making up the device. They have dimensions in the 0.5 to 2 mi-cron range. To get an idea of the relative dimensions of a semiconduc-tor device, imagine the cross section in Fig. 3.21 as tall as a house

a. Inside Diameter Diamond Saw

b. Wire Saw

CrystalWire

Spools

Rollers

Figure 3.19 Inside-diameter saw wafer slicing.

66 Chapter 3

wall, about 8 ft (2.4 m). On that scale, the working layers on the topof the wafer would all exist within the top 1 or 2 in (25 or 50 mm) orless.

Flatness is an absolute requirement for small dimension patterning(see Chapter 11). The advanced patterning processes project the re-quired pattern image onto the wafer surface. If the surface is not flat,the projected image will be distorted just as a film image will be out offocus on a non-flat screen.

The flatting and polishing process proceeds in two steps: roughpolish and chemical/mechanical polishing (Fig. 3.22). Rough polish-ing is a conventional abrasive slurry lapping process, but it is finetuned to semiconductor requirements. A primary purpose of therough polish is to remove the surface damage left over from the wa-fer slicing process.

Wafer center

Solid alignment bar

Reference Point 2.00 ± 0.053.88 ± 0.05

0.88

±0.

05

Figure 3.20 Laser dot coding. (Reprinted from the Jan. 1998edition of Solid State Technology, copyright 1998 by Penn-Well Publishing Company.)

Figure 3.21 Cross section of a MOS tran-sistor.

Figure 3.22 Abrasive and chemi-cal-mechanical surface polish-ing.


Chemical Mechanical Polishing (CMP)

The final polishing step is a combination of chemical etching and me-chanical buffing. The wafers are mounted on rotating holders and low-ered onto a pad surface rotating in the opposite direction. The padmaterial is generally a cast and sliced polyurethane with a filler or aurethane coated felt. A slurry of silica (glass) suspended in a mildetchant, such as potassium or ammonium hydroxide, is dropped ontothe polishing pad.

The alkaline slurry chemically grows a thin layer of silicon dioxideon the wafer surface. The buffing action of the pad mechanically re-moves the oxide in a continuous action. High points on the wafer sur-face are removed until an extremely flat surface is achieved. If asemiconductor wafer surface was extended to 10,000 ft (3,048 m—thelength of a typical airport runway), it would vary about plus or minus2 in (50 mm) over its entire length.

Achieving the extreme flatness requires the specification and con-trol of the polishing time, the pressure on the wafer and pad, thespeed of rotation, the slurry particle size, the slurry feed rate, thechemistry (pH) of the slurry, and the pad material and conditions.

Chemical/mechanical polishing is one of the techniques developedby the industry that has allowed production of larger wafers. CMP isused in the wafer fabrication process to flatten wafer surfaces afterthe buildup of new layers creates uneven surfaces. In this application,CMP is the abbreviation for chemical mechanical planarization. A de-tailed explanation of this use of CMP appears in Chapter 10.

Backside Processing

In most cases, only the front side of the wafer goes through the exten-sive chem/mech polishing. The backs may be left rough or etched to abright appearance. For some device use, the backs may receive a spe-cial process to induce crystal damage, called backside damage. Back-side damage causes the growth of dislocations that radiate up into thewafer. These dislocations can act as a trap of mobile ionic contamina-tion introduced into the wafer during the fab process. The trappingphenomenon is called gettering (Fig. 3.23). Sandblasting of the back-

= Contamination= Dislocation line

Wafer

Figure 3.23 Trapping.

68 Chapter 3

side is another standard technique. Other methods include the deposi-tion of a polysilicon layer or silicon nitride layer on the back.

Double-Sided Polishing

One of the many demands on larger diameter wafers is flat and paral-lel surfaces. Most manufacturers of 300-mm diameter wafers employdouble-sided polishing to achieve flatness specifications of 0.25 to0.18 μm over 25 × 25 mm sites.5 A downside is that all further process-ing must employ handling techniques that do not scratch or contami-nate the backside.

Edge Grinding and Polishing

Edge grinding is a mechanical process that leaves the wafer with arounded edge (Fig. 3.24). Chemical polishing is employed to furthercreate an edge that minimizes edge chipping and damage during fab-rication that can result in wafer breakage or serve as the nucleus fordislocation lines.

Wafer Evaluation

Before packing, the wafers (or samples) are checked for a number ofparameters as specified by the customer. Figure 3.25 illustrates a typ-ical wafer specification.

Primary concerns are surface problems such as particulates, stain,and haze. These problems are detected with the use of high-intensitylights or automated inspection machines.

Figure 3.24 Wafer edge grinding.

Figure 3.25 Typical 200-mm wa-fer specification.


Oxidation

Silicon wafers may be oxidized before shipment to the customer. Thesilicon dioxide layer serves to protect the wafer surface from scratchesand contamination during shipping. Most companies start the waferfabrication process with an oxidation step, and buying the wafers withan oxide layer saves a manufacturing step. Oxidation processes areexplained in Chapter 7.

Packaging

While much effort goes into producing a high-quality and clean wafer,the quality can be lost during shipment to the customer or, worse,from the packaging method itself. Therefore, there is a very stringentrequirement for clean and protective packaging. The packaging mate-rials are of nonstatic, nonparticle-generating materials, and theequipment and operators are grounded to drain off static charges thatattract small particles to the wafers. Wafer packaging takes place incleanrooms.

Engineered Wafers (Substrates)

Increasingly, wafer fabrication companies are asking for wafer manu-facturers to supply wafers with deposited top-side layers, such as epi-taxial silicon. Other wafer products include silicon deposited oninsulators (SOI and SOS) such as sapphire or diamond (Chapter 12).

Review Questions

1. In a polycrystalline structure, the atoms are not arranged (true orfalse).

2. In a single-crystal structure, the unit cells are not arranged (trueor false).

3. Draw a cubic unit cell and identify the ⟨100⟩ plane.

4. ⟨111⟩ oriented wafers are used for (bipolar, MOS) devices.

5. What is the orientation of a semiconductor crystal if the seed has a⟨100⟩ orientation.

6. Draw a diagram of a CZ crystal grower and identify all the majorparts.

7. During crystal growth, the molten material is changed from singlecrystal structure to a polycrystal structure (true or false).

8. Why are wafers edge rounded?

70 Chapter 3

9. Draw a flow diagram of the wafer preparation process.

10. Give two reasons why semiconductor wafers require a flat surface.

References

1. Russ Arensman, “One-Stop Automation,” Electronic Business, July 2002, p. 54. 2. Sumitomo Sitix product brochure.3. R. E. Williams, Gallium Arsenide Processing Techniques, Artech House Inc.,

Dedham MA, 1984, p. 37.4. S. J. Brunkhorst and D. W. Sloat, “The impact of the 300-mm transition on silicon

wafer suppliers,” Solid State Technology, January 1998, p. 87.5. Ibid.

Documents

Mps Ref Lect 03 Crystal Growth