Nanosystems Design and Tools

© INS-UoU 2015 All rights reserved

University of Utah | P.-E. Gaillardon | 1

Architecture Reading Group February 12th, 2016 – Salt Lake City, UT, USA

Nanosystems Design and Tools

Pierre-Emmanuel Gaillardon Department of Electrical and Computer Engineering – University of Utah



A Novel Offer for Microelectronics

Technology Push

Market Pull

Keeping the pace towards more functionality “Increase the numbers of devices per area unit”

“Increase the device capabilities for a given area” Functionality-Enhanced Devices

“Increase the circuit capabilities for a given area” Functionality-Enhanced Circuits

Novel EDA

Inspired from

Inspiring



A Transversal Research Methodology

Local optimization One-way development

IEDM’11,’12,’14, EDL’14, TED’14, TNANO’14, MNE’14

DAC’11,’13,’14, DATE’13,’14,’15 ASP-DAC’13,’14,’15, NANOARCH’11,’12,’13,’14

JETCAS12,’14, JETC’14, Phil. Trans. A’14 FPGA’14,’15, FPL’14, FPT’14

ISCAS’11,’13,’14, TCAS-I’14, TCAS-II’13, CASM’13 ATS’14, ISVLSI’14, NEWCAS’13, VLSI-SoC’12

Technology

Circuits

Architectures Applications

Fast feedback loop Global optimization across the traditional design boundaries



Outline

•  Introduction •  Functionality-enhanced Devices

–  Controllable-polarity transistors: concept and fabrication –  Circuit design and associated physical design

•  Emerging Electronic Design Automation techniques –  Biconditional Binary Decision Diagrams (BBDDs) –  Majority Inverter Graphs (MIGs) –  Application to reconfigurable logic architectures

•  Functionality-enhanced Circuits –  RRAM: A low-power system enabler –  RRAM-based FPGA design

•  Conclusion



Outline





•  Conclusion



What is hidden behind Doped S/D CMOS ?

Ultimate Devices

Novel Conduction Properties

Ambipolar Conduction

n-type and p-type carriers

CONTROL IT

Gate Source Drain

Tri-gate aka FinFET

Source Drain Gate

1D Transistors Vertical Stacked Nanowires Gate-All-Around Structures

Source Drain

Polarity gate

Control gate

Enhanced Functionality In-field reconfiguration



Multiple-Independent-Gate SiNWFET •  3-independent gate regions •  Schottky barriers at S and D •  Polarity and Threshold control 40

30

20

10

0

I D [u

A]

1.21.00.80.60.40.20.0 VG [V]

Solid lines: Low Vt configurationDash lines: High Vt configurationVDS=1.2V

VPGS=VPGD=1.2VVCG=[0,1.2V]

'1'

'0'

'1'

'1'G

LVT NMOS

'1'

'0'

'1'

G'1'

'1'

'0'

'1'

'1'G

LVT NMOS HVT NMOS

40

30

20

10

0

I D [u

A]

1.21.00.80.60.40.20.0 VG [V]



VCG=VPGD=1.2VVPGS=[0,1.2V]

'1'

'0'

'1'

'1'G

LVT NMOS'1'

'0'

'0'

'0'G

LVT PMOS

40

30

20

10

0

I D [u

A]

1.21.00.80.60.40.20.0 VG [V]



VPGS=VPGD=0VCG=[0,1.2V]


'1'

'0'

'1'

G'1'

HVT NMOS'1'

'0'

G

'0''0'

HVT PMOS

40

30

20

10

0

I D [u

A]

1.21.00.80.60.40.20.0 VG [V]


VPGS=VCG=0VPGD=[0,1.2V]




'1'

'0'

'1'

'1'G

LVT NMOS'1'

'0'

'0'

'0'G

LVT PMOS

'1'

'0'

'1'

G'1'

HVT NMOS

Same ION ! Limited performance compromise

40

30

20

10

0

I D [u

A]

1.21.00.80.60.40.20.0 VG [V]


��

'1'

'0'

G

'0''0'

HVT PMOS

40

30

20

10

0

I D [u

A]

1.21.00.80.60.40.20.0 VG [V]






'1'

'0'

'1'

'1'G

LVT NMOS'1'

'0'

'0'

'0'G

LVT PMOS

'1'

'0'

'1'

G'1'

HVT NMOSHVT '1'

'0'

G

'0''0'

HVT PMOS

40

30

20

10

0

I D [u

A]

1.21.00.80.60.40.20.0 VG [V]






'1'

'0'

'1'

'1'G

LVT NMOS'1'

'0'

'0'

'0'G

LVT PMOS

'1'

'0'

'1'

G'1'

HVT NMOSLVT NMOS

'1'

'0'

G

'0''0'

HVT PMOS

40

30

20

10

0

I D [u

A]

1.21.00.80.60.40.20.0 VG [V]






'1'

'0'

'1'

'1'G

LVT NMOS'1'

'0'

'0'

'0'G

LVT PMOS

'1'

'0'

'1'

G'1'

HVT NMOS

LVT PMOS

'1'

'0'

G

'0''0'

HVT PMOS

40

30

20

10

0

I D [u

A]

1.21.00.80.60.40.20.0 VG [V]






'1'

'0'

'1'

'1'G

LVT NMOS'1'

'0'

'0'

'0'G

LVT PMOS

'1'

'0'

'1'

G'1'

HVT NMOS

HVT

J. Zhang et al, TED’14



DG#SiNWFET+logic+ CMOS+logic+Area = 4 Area = 18

3/2 3/2

3/2 3/2

3 3

3 3

B=1

B=0 CTRL gate

More Expressive Device Switching Functions

CG PG

S

D

CG S

D

PG = 0

p-FET

PG = 1 CG

S

D n-FET

Polarity gate

2-input XOR

Increase the functionality of the device rather than scaling it!



These are not “Castles in the Air” ! M. De Marchi et al, IEDM’12



1.  Nanowires etching •  Bosch DRIE process

2.  Polarity Gate deposition 3.  Control Gate deposition

•  Self-alignment 4.  Ni/Si formation

•  S/D and gates

Fabricated Device Overview

M. De Marchi et al, IEDM’12

IOFF in the range of 100 fA Ultra Low Standby Power

Technology

350nm

100nm

d<20nm

100nm100nm

NWstack

GateOxide

PolySi

NWstack

!2 3 4

VCG [V]

ID [A

]

Vpg = 0V

70mV/dec

VDS = 2V

ION/IOFF > 106 S~64mV/Dec



Outline





•  Conclusion



A B C

(a) (b)

A AB

BA B

A

BA B

A AB

BA B

A

B

C

C3#input+XOR+

A. Zukovski et al., DAC’11

Gnd

Vdd

Gnd

Vdd

A B

A

B

A B

(a)2#input+NAND+

Nega>ve+Unate+func>ons+NAND,%NOR,%AOI,%OAI,..%

Bias+the+polarity+gates!+(unipolar%behavior)%

2#input+XOR+

A B C

(a) (b)

A AB

BA B

A

BA B

A AB

BA B

A

B

C

CH. Ben Jamaa et al., DATE’09

Binate+func>ons+XOR,%XNOR,..%

Inputs+to+the+polarity+gates!+(Exploit%the%device%behavior)%

Circuit Design with Controllable-Polarity Transistors



(a) (b)

A AB

BA B

A

B

A

outC

Cin

A AB

BA B

A

B

C

Sum

in

CinSUM+

Sum = A⊕ B⊕CIN COUT =MAJ(A,B,CIN )

8 Transistors

Area saving (smaller gates)

Delay saving

(smaller stacks)

CARRY+(a) (b)

A AB

BA B

A

B

A

outC

Cin

A AB

BA B

A

B

C

Sum

in

Cin

O. Turkyilmaz et al., ISCAS’13

Compact computation primitives XOR - MAJ

Compact Full-Adder implementation



Fewer transistors for XOR operation Every transistor has two gate terminals to route�

Mitigating the wiring complexity



Dumbbell#s>ck++

Control'gates'connected'together'

Polarity'gates'connected'together'

Con

trol

Polarity

Sour

ce

Dra

in

S. Bobba et al, DAC’12

Layout regularity with Tiles

Simplified%rouAng%

CMOS+style+layout+t1 t2

t4 t3

Novel+approach+t4 t2

t1 t3

2#input+XOR+gate+

t1 t2

t3 t4

Complex%rouAng%

No doping!

TILE



Sea-of-Tiles (SoT)



Outline

•  Introduction

•  Functionality-enhanced Devices –  Controllable-polarity transistors: concept and fabrication –  Circuit design and associated physical design



•  Conclusion



Logic Synthesis (Optimization) Challenges

•  Logic Synthesis is a technology supporter –  LS techniques derive from CMOS abilities -NAND/NOR/

MUX –  Many real-life applications contains different type of

functions intertwined (AND/OR, XOR) together –  LS heuristics target only one type of function for pragmatic

reasons

•  Logic Synthesis as a design enabler

BBDDs L. Amarù et al., DATE’13, DATE’14

Path1: Model comparator primitives (rather than switches)

MIG L. Amarù et al., DAC’13, DAC’14

Path2: Exploit more generic data structures

Can we derive novel architectures from these techniques?



f (x, y,.., z) = (x⊕ y) f (y ', y,.., z)+ (x⊕y) f (y, y,.., z)

Path1: Model the Comparator Primitive

•  Comparator behavior captured in the biconditional expansion:

"  Each BBDD node: "  Has 2 branching variables "  Implements the biconditional expansion "  Can reduce to Shannon’s expansion

PV=x SV=y

PV=SV PV≠SV

f(x,y,...,z)

f(y,y,...,z) f(y,y,…,z)

A?B A?B

A=B on

A≠B off

Biconditional Binary Decision Diagrams

Ability to still model efficiently general logic Arithmetic-intensive representation form

Comparator primitive

L. Amarù et al., DATE’13, DATE’14



Elementary Properties of BBDDs •  BBDDs are canonical!

–  Reduction and Ordering rules extended from standard BDDs –  Variable reordering and sifting operations still efficient

•  BBDDs can support efficient logic manipulation –  Traditional DD algorithms can be extended –  BBDD software package available at: http://lsi.epfl.ch

•  BBDDs are compact for arithmetic functions –  n-bit adder: 40% nodes reduction

–  n-bit majority: 4× for large enough n

BBDD Package BBDD

18n2 + 1

2n + 11

8n2

⎡⎢⎢

⎤⎥⎥(n − n

2⎡⎢⎢

⎤⎥⎥+1)+1BBDDs:% BDDs:%

3n +1 5n + 2BBDDs:% BDDs:%




"  One-to-one correspondence between the BBDD nodes and XOR-MUX structure:

"  DD performances (MCNC, opencores and hard arithmetic circuits):

"  BBDDs are frequently more compact than BDDs (1.1× to 5×) "  BBDDs build faster than standard DDs (1.4× to 4.4×)

"  EDA impact (Telecom circuit testcase) "  BBDD restructuration reduces by 20% the critical path delay as

compared to a vanilla synthesis performed by Design Compiler

BBDD superiority over standard BDDs in ASICs

PV=x SV=y

PV=SV PV≠SV

f(x,y,...,z) = F

f(y,y,...,z) = G f(y,y,…,z) = H

Transistor level

xy

F

0 1

GH




Outline

•  Introduction



•  Functionality-enhanced Circuits –  RRAM: A Low-Power system Enabler –  RRAM-based FPGA design

•  Conclusion



Path 2: Exploit more generic data structures •  Majority logic is a powerful generalization of AND/ORs. Ex1: MAJ(a,b,c)=ab+ac+bc Ex2: MAJ(a,b,1)=a+b Ex3: MAJ(a,b,0)=ab

•  Unlocks optimization opportunities not apparent before.

AND

AND OR AN

D OR

OR

OR

OR

x0 x1

x2

x3 x4

f

MAJ

MAJ

x0 x1 x2

x3 x4

f

L. Amarù et al., DAC’14



How to exploit MAJ logic?: Majority-Inverter Graph

Definition: An MIG is a logic network consisting of 3-input majority nodes and regular/complemented edges.

MAJ

MAJ

MAJ

MAJ

MAJ

AND

OR

OR

x0 x1 x3 x4

f MAJ

MAJ

MAJ

x0 x1 x3 x4

f

1

1

1

From AOIG to MIG by direct transposition

Theorem: MIGs include AOIGs MIGs include AIGs

MIGs are at least as compact as AOIGs Exploiting the MAJ functionality unlock better representations




MIG Manipulation through an efficient Boolean Algebra

•  MIG Axiomatic System%Ω:%–  Commutativity: M(x, y, z) = M(y, x, z) = M(z, y, x) –  Majority: if(x = y), M(x, y, z) = x = y if(x = yʹ), M(x, y, z) = z –  Associativity: M(x, u, M(y, u, z)) = M(z, u, M(y, u, x)) –  Distributivity: M(x, y, M(u, v, z)) = M(M(x, y, u), M(x, y, v), z) –  Inverter Propagation: Mʹ(x, y, z) = M(xʹ, yʹ, zʹ)

•  Theorem: (B,M,’,0,1)%subject%to%axiom%in%Ω%is%a%Boolean%algebra.%•  Theorem: It is possible to transform any MIG α into any

other logically equivalent MIG β, by a sequence of transformations in Ω. In%pracAce,%it%is%always%possible%to%reach%a%desired%MIG,%i.e.,%an%

op>mized%MIG,%starAng%from%an%iniAal%MIG.%Area%=%MIG%size%–%Delay%=%MIG%depth%–%Power%=%MIG%SWacAvity%




Superiority of MIG w.r.t. Standard Techniques

Post Tech. Mapping (ASIC) Logic%Synthesis%results%in%22Xnm%

CMOS%–%MCNC%suite%

Cells%=%{MIN,%XOR,%XNOR,%NAND,%NOR,%INV}%

#(22%,+14%,+11%)+delay,+area,+power+

w.r.t.%AOIGXbased%synthesis%

Novel LS techniques promising to push design efficiency! Let’s go to FPGAs and see how to exploit them (focus on BBDDs)!


#(15%,+5%,+2%)+delay,+area,+power+

w.r.t.%commercial%flow%++

Post P&R



Outline

•  Introduction




•  Conclusion



FPGAs: Where to play?

CLB

SB

SB

CLB

SB

SB

CLB CLB

CLB

CLB

CLB CLB CLB

…

…

…

…

…

…

…

…

…

…

…

… …

…

…

…

…

…

…

…

…

…

…

…

N BLEs I

BLE

BLE

N

.. ..

.. ..

.. ..

.. ..

DFF

Clk

...

LUT

K

Memories (Routing)

Memories (Logic) Routing resources inN

outW inS inE

inW

14% 8% 43% 35% Logic Memory Interconnects + buffers + MUXs Memory

Logic Block (LB) Routing Resources (RR)

20% 80%

40% 60%

M. Lin et al, TVLSI’07

Routing Costs

(Local & Global)

Area ↓ Delay ↓ Power ↓



Exploiting the biconditional expansion in LUTs

F

A

B

B,B,0,1A=BA≠B

F

(b)(a)

B,B,0,1

BBDD node

B A

BBDD representation

A B

F

A

B

B,B,0,1A=BA≠B

F

(b)(a)

B,B,0,1

B

Hardware support

What is the advantage w.r.t. a standard LUT? Strong power advantage •  1st level of MUXes are statically configured •  2nd level of MUXes activity is reduced thanks to the XORs •  MUX tree is not driven by SRAMs ! Buffering requirements reduced!

f(A,B)= A⊕B . f(B,B)+A⊕B . f(B,B)B,B,0,1 B,B,0,1

Let’s consider 2-input LUTs

P.-E. Gaillardon et al., FPGA’14, FPGA’15



MCNC big20 Suite

tseng

alu4apex2

apex4bigkey

clma

desdiffeq

dsipellip

ticex5p

ex1010fris

c

misex3

pdcs298

s38417

s38584.1 seqsp

la-6

-4

-2

0

2

4

Norm

alize

d gain

tseng

alu4apex2

apex4

bigkeyclm

ades

diffeqdsip

elliptic

ex5p

ex1010fris

c

misex3

pdcs298

s38417

s38584.1 seqsp

la-15

-10

-5

0

5

10

15

20

Norm

alize

d gain

tseng

alu4apex2

apex4

bigkeyclm

ades

diffeqdsip

elliptic

ex5p

ex1010fris

c

misex3

pdcs2

98

s38417

s38584.1 se

qsp

la

-10

0

10

20

30

40

50No

rmali

zed g

ain

tseng

alu4apex2

apex4bigkey

clma

desdiffeq

dsipellip

ticex5p

ex1010fris

c

misex3

pdcs298

s38417

s38584.1 seqsp

la0.0

2.0E6

4.0E6

6.0E6

8.0E6

1.0E7

1.2E7

1.4E7

1.6E7

1.8E7

2.0E7

2.2E7

2.4E7

Tota

l are

a - Lo

gic +

Rout

ing (M

in. Tr

ans. s

ize)

tseng

alu4apex2

apex4

bigkeyclm

ades

diffeqdsip

elliptic

ex5p

ex1010fris

c

misex3

pdcs298

s38417

s38584.1 seqsp

la0

1

2

3

4

5

6

7

8

Critic

al pa

th de

lay (n

s)

tseng

alu4apex2

apex4

bigkeyclm

ades

diffeqdsip

elliptic

ex5p

ex1010fris

c

misex3

pdcs2

98

s38417

s38584.1 se

qsp

la0

10

20

30

40

50

60

70

80

90

Tota

l pow

er co

nsum

ption

(mW

)

Standard LUT BBDDm - Freq2

BBDDm - Freq3 BBDDm - Freq5

2% Area loss

2% Delay reduction

29% Power reduction

Power reduction at no ADP compromises!

Biconditional expansion-based LUTs performances

P.-E. Gaillardon et al., FPGA’14, FPGA’15

Tools: VTR7.0 flow – Perf. post layout in 45nm Arch: Frac. LUT6, 10 LUTs/CLB, 40 inputs/CLB



Outline





•  Conclusion



RRAM: A Low-Power System Enabler

•  MIM structures –  Different switching mechanisms –  Different physical origins

•  Back-End-of-Line integration process

•  Interesting device properties –  Non-volatile storage (1-bit or multi-bit) –  The properties can be engineered according to the application

(Thresholds, resistance levels, aging, data retention, …) –  Radiation tolerant

Low-Power Logic-in-memory Applications Can we find an unconventional killer application that goes beyond the simple notion of storage?

Merge them with the data path of reconfigurable logic to achieve 5× ⬇︎power and 1.5× ⬇︎ ADP

V

I



RRAM Technological Developments

•  Material%InnovaAons:%Pt/TaOx/CrOy/Cr/Cu,'Pt/Ti/HfO2/Pt%•  Structural%InnovaAons:%Fences%(be^er%scalability)%•  CMOSXRRAM%coXintegraAon%

D. Sacchetto et al., CASM’13

BE TE

Fences

J. Sandrini et al., MNE’14, JME’15, JETCAS’15

CMOS chip

notch Carrier wafer

ReRAM arrays

Controlling the technology and its CMOS co-integration opens a path towards innovative low-power circuits and systems



Outline




•  Functionality-enhanced Circuits –  RRAM: A low-power system Enabler –  RRAM-based FPGA design

•  Conclusion



FPGA Non-Volatile Routing Multiplexer

Multi-stage Multiplexers are based on transmission-gates

Y

D0

D1

a) b)

S0

SN0

D2

D3

SN0

S0

S0

SN1

S1

S1

Y

D0

D1

D2

D3

1st stage

2nd stage 1st stage

2nd stage

Y

D0

D1

a) b)

S0

SN0

D2

D3

SN0

S0

S0

SN1

S1

S1

Y

D0

D1

D2

D3

1st stage

2nd stage 1st stage

2nd stage

P.-E. Gaillardon et al, VLSI-SoC’12

RRAM elements = Non-Volatile Switches Replacement of all the Transmission-Gates

Non-Volatile Routing MUX Performance improvement

FPGAs rely on Routing Multiplexers



Towards Faster FPGAs?

•  Area reduction up to 8%: Slight reduction – programming circuits

•  Delay reduction up to 73%: Low On-resistance in data paths

Toolflow

VTR Toolflow 40-nm tech. node

MCNC Benchmarks

P.-E. Gaillardon et al, VLSI-SoC’12

Low-on Resistance Routing Structures Faster FPGAs Nominal Vdd

alu4apex2apex4

C1355

C1908

C2670

C3540

C5315

C6288

C7552dalu de

s

ex1010ex5p i10 i8

misex3 pd

cseqsplat481

0

5

10

15

20

25

30

35

40

45

50

55

60

65

70

Crit

ical

Pat

hDel

ay (n

s)

SRAM ReRAM

Room for architectural innovations



Towards%LowXPower%FPGAs?%High#Performance+Low#Power+Rou>ng+Structures+ Ultra#low+Power+FPGAs+

NearXVT%power%supply%

0.4 0.6 0.8 1 1.2 1.4 1.6 1.80

0.5

1

1.5

2

Del

ay(n

s)

Vdd(V)

0.4 0.6 0.8 1 1.2 1.4 1.6 1.80

12.5

25

37.5

50

Ener

gy(p

J)

0.4 0.6 0.8 1 1.2 1.4 1.6 1.80

50

SRAM 32−input MUX DelaySRAM 32−input MUX EnergyRRAM 32−input MUX DelayRRAM 32−input MUX Energy

In+CMOS,+Vdd+reduc>on+leads+to+low+energy+consump>on+but+large+delay+(reducAon%of%Ion%current%and%increase%of%parasiAc%capacitances)%%

In%ReRAM%MUX,%passXgates%are%

replaced%by%RRAMs%%

No+Ron+degrada>on+%

Limited'delay'degrada=on'but'

similar'energy'gains'RRAM#based+MUX+can+operate+at+low+voltage+without+delay+degrada>on+

X.+Tang!et!al.,+FPT’14!


University of Utah | P.-E. Gaillardon | 38 alu4 apex2apex4bigkey clma des diffeq dsip elliptic ex5pex1010 frisc misex3 pdc s38417s38584.1s298 seq spla tseng

0

1

2

3

4

5

Pow

er (

W)

SRAM FPGARRAM FPGANear−Vt SRAM FPGANear−Vt RRAM FPGA

0

10

20

30

Del

ay (n

s)


alu4 apex2apex4bigkey clma des diffeq dsip elliptic ex5pex1010 frisc misex3 pdc s38417s38584.1s298 seq spla tseng

0

0.5

1

1.5

2 x 107

Are

a (#

of t

ran.

)


alu4 apex2apex4bigkey clma des diffeq dsip elliptic ex5pex1010 frisc misex3 pdc s38417s38584.1s298 seq spla tseng

RRAM-based FPGA Architectural Exploration

UMC 0.18 µm2 VDD=1.2V

MCNC Benchmarks VTR Flow 7

12% Area reduction

26% Delay reduction

81% Power reduction

At Near-Vt, compared to nominal VDD

P.-E. Gaillardon et al., DATE’15



Outline





•  Conclusion



Take-away Messages�

#  Better devices do not mean smaller devices $  Exploit the functionality rather than the density

$  Trigger many innovations at the circuit level (arithmetic, routing, …)

#  Novel EDA techniques are promising sources of inspiration $  Biconditional expansion shows great quality

$  Majority logic even more promising!

#  The architecture/application should lead the game



Acknowledgments

Physical Design

EDA Tools

Funding ERC-Nanosys

Swiss NSF

Pr. Nanni De Micheli

Technology

Modeling Mr. Zhendong Guo

Architecture Design

Mr. Luca Amarù Mr. Winston Haaswijk

Ms. Somayyeh Rahimian Mr. Hassan Ghasemzadeh Mr. Xifan Tang Mr. Gain Kim

Mr. Michele De Marchi Mr. Jian Zhang Mr. Maxime Thammasack

Mr. Jury Sandrini



Integrated Nanosystems Research Group Department of Electrical and Computer Engineering

MEB building – University of Utah – Salt Lake City – UT – USA

Thank you for your attention

Questions?

Documents

Nanosystems Design and Tools