MAITHIL PACHCHIGAR

Next Generation SAR ADC Simplifies Precision Measurement

1©2016 Analog Devices, Inc. All rights reserved.

Agenda

Introduction

AD400X Ease of Use System-Level Benefits

Ease of Drive

Internal Overvoltage Clamp

Span Compression

Efficient Digital interface

Performance Benefits

Key Attributes and End Applications

Design Resources

ADI’s First 20-bit Precision SAR ADC

Conclusion

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Enables low power precision data acquisition

Signal conditioning can be optimized for frequency bandwidth of interest

Easy to achieve datasheet performance

Reduces design time, debug, risk

Ease of Drive

High-Z mode plus long acquisition phase enables the use of low power precision ADC drive amplifier when the bandwidth of interest is low

Reduces signal chain power consumption

Ease-of-Digital interface

Low SPI clock rate requirements reduce IO power consumption and simplifies the requirements on digital Isolation

Reduced sensitivity to external circuitry

Reduced performance sensitivity to resistor values in RC filter

Key Benefits

AD400X: Next Generation of Industry Leading 16/18/20-Bit Precision SAR ADC Family

4

SIN

AD

(d

B)

1

98

100

Throughput (MSPS)

20.4

101.5

AD79827mW

AD769017mW

AD400316mW

Resolution VREF VDD Interface Input Package

18 Bits 2.4V to 5.1V 1.8VSPI

1.8V/2.5V/3V/5VDifferential

±VREF

10-ld MSOP 3x4.9mm

10-ld LFCSP 3x3mm

AD4003: 18-Bit, 2MSPS Precision SAR ADC

Portfolio Positioning Pin-For-Pin Compatible (10- Lead)

Benefits and Features

Ease of Use

High Performance

Throughput: 2 MSPS

DNL: 18-bit No Missing Codes

INL: ±1.0LSB (± 3.8ppm) Max

SNR: 100.5dB typ @ 1Khz

THD: -123dB typ @ 1Khz

True differential analog input range: ±VREF

0 V to VREF with VREF between 2.4 V to 5.1 V

Low Power: Scales linearly with throughput

80 µW typ @ 10kSPS

16 mW typ @ 2MSPS (Total)

Small Form Factor

Guaranteed Operation: - 40°C to +125°C

GND

IN+

IN–

SDI

SCK

SDO

CNV

AD40XX

3/4-WIREINTERFACE

V+ = +5V

DIGITALHOST

(uP/FPGA)

AIN+

AIN-

C

R

AMP

AMP

18-BITSAR ADC

SERIALINTERFACE

HIGH-Z(OPTIONAL)

VIOREF VDD

4.096V

100nF

1.8V10µF

REF

C

R

AMP

CLAMP

LDO

HOST

SUPPLY

1.8V TO 5V

Ease of Drive

Internal Overvoltage

Clamp

Efficient Digital Interface

Span Compression

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AD400X: Ease of Use Features

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CNV

CONVERSION ACQ/ TRACKPHASE

SCK

SDO

ADC INPUT

Traditional SAR

DATA

ADC INPUT HIGH-Z ENABLED

AD4003

CONV ACQUISITION/ TRACK

DATA

ADC

ADCDRIVER VREF

CDAC

CDAC+

_

VREF

+

_R

R

C

C

C

Ease of Drive

AD4003 Input Current vs Input Voltage

7

-15

-12

-9

-6

-3

0

3

6

9

12

15

-5 -4 -3 -2 -1 0 1 2 3 4 5

Inp

ut

Cu

rren

t (µ

A)

Input Differential Votlage (V)

25C High-Z Enabled

25C High-Z Disabled

Reducing the input current change versus input voltage change to ±1.5µA, which is 40x

smaller versus previous SAR ADC products (AD7982 and AD7960 ±30µA/MSPS)

Reduces the nonlinearity error source from the external RC filter

Improves the signal chain INL and THD performance

When high-Z mode is enabled, the ADC consumes ~2 mW/MSPS extra power

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Ease of Drive: High-Z Mode

Enables low input current and improved THD with low power/BW amplifiers.

ADC can be driven directly with precision amplifiers or signal conditioning stage.

Eliminates the need of using dedicated high speed ADC driver when the input frequency of interest is low (<10kHz).

SENSORSJFET/INAMP RC FILTER

DRIVERSTAGE ADC

REF

FPGA/µC

REFBUF

Typical Customer’s Signal Chain

Signal Conditioning

Stage

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Ease of Drive: High-Z Mode Benefits

Ease of Drive: AD4003 vs AD7982 Driver Comparison

9

©2016 Analog Devices, Inc. All rights reserved.

High-Z Mode Disabled High-Z Mode Enabled

Higher performance

with lower RC BW

2.5x Lower Power

SIN

AD

(dB

)

SIN

AD

(dB

)

C(F), R (Ω) and RC Bandwidth(Hz) C(F), R (Ω) and RC Bandwidth(Hz)

(Fs = 1MSPS, fin = 1kHz)

Eliminates the need for external protection diodes and protects the ADC inputs against DC over voltage.

When the clamp turns on, it can sink up to 50mA of current and current will flow through clamp into ground.

NO current is pushed into the REF pin causing a disturbance on the reference. This is important if the reference is shared among multiple ADCs.

10

VIN Voltage (V)

IN+

/-P

in V

olt

ag

e (

V)

CEXT

REXT

VIN

REF

D1

IN+/IN–

GND

+_ CLAMP

0V to 15V 0V to 5.5V RIN CIN

D2CPIN

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Internal Overvoltage Clamp

Enables single positive supply rail to power the driver amplifier

Simplifies the power supply design. Lowers power consumption

ADC performs a digital scaling function that maps zero-scale code from 0V to 0.1 • VREF and full-scale code from VREF to 0.9 • VREF.

SNR takes about ~1.9dB hit for the reduced input range 20*log(8/10)

11

0.1 ×VRE = 0.41V

0.9 ×VREF = 3.69V

ANALOG INPUT

DIGTAL OUTPUT

+FSR

-FSR

ALL 2 CODES!ADC

+5V

N

VREF = 4.096V

Span Compression

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Features System Benefit

Turbo modeLower interface clock rates

Register programmability and Status bits Option

Broadens selection of processors including lower end processors.Allows 2.5x slower SPI clock rate than AD798x when running at 1MSPS. Simplify isolation solution.Higher throughput with existing components.Error/status checking for functional safety.

SDI=1

tCNVH

tCYC

CNV

AQUISITION AQUISITION

tACQ

tSCK

tSCKL

CONVERSION

SCK

0D1D51D61D71DODS

tEN

tHSDO

1 2 3 16 17 18

tDSDO tDIS

tSCKH

tQUIET1

tQUIET2

tCONV

Turbo Mode12 © Analog Devices, Inc. 2016, all rights reserved.

Digital Interface– BenefitsEfficient Digital Interface

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1.0

0.8

0.4

0

0.6

0.2

–0.2

–0.6

–0.4

–0.8

–1.00 32768 65536 131072 19660898304 163840 229376 262144

INL

(L

SB

)

CODE

+125°C+25°C–40°C

100k

100

10k

1

10

1k

0.1

0.01P

OW

ER

DIS

SIP

AT

ION

(µ

W)

10 1M100k10k1k100

THROUGHPUT (Hz)

VDDVIOVREFTOTAL POWER

INL: ±1.0 LSB (± 3.8ppm) Max Guaranteed Power: 80µW @10kSPS; 8mW @ 1MSPS

Performance - BenefitsPerformance Benefits

Key Attributes and End Applications

14 ©2016 Analog Devices, Inc. All rights reserved.

AD4000/3 Key Attributes High Precision Data Acquisition Applications

Easy to UseReduces Design

Time

High Precision18-Bit

INL ±1.52ppmSNR 100.5dB

Small Footprint3mm x 3mm

High Throughput2MSPS

Low Power16mW @ 2MSPS80µµµµW @ 10kSPS

Overvoltage Robust

Automated Test

Electrical Test and MeasurementMachine Automation

AvionicsMeasurement and Control

Medical Imaging CT and Digital X-Ray

Optical Communications

Instrumentation Applications

15

Signal Condition & Buffer

SAR ADC

Functional & Dynamic Performance Tests

Opportunity to Improve Density & Power Efficiency

of Signal Chain

Improvements Realized with the AD400x Family

Enables wider bandwidth high precision instrumentation equipment

Enables higher performing battery powered instrumentation devices

Hi-Z mode allows for lower power conditioning circuitry

ADC power scales linearly with throughput Simplify signal chain BOM Small footprint for handheld devices

80

83

86

89

92

95

98

101

1 10 100 1000

SIN

AD

dB

Frequency KHz

SINAD vs Frequency for AD4003 and AD7982

AD4003

AD7982

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EVAL-AD400xFMCZ EVAL-SDP-CH1Z

Go Beyond Silicon: Design Resources

16

Data Sheet

EVAL-AD400xFMCZ Boards Needs EVAL-SDP-CH1Z controller board

Companion Products ADC Drivers: ADA4807-1, ADA4805-1,

ADA4897-1, ADA4940-1 Reference Buffer: ADA4807-1 Instrumentation Amplifier:AD825x Reference: ADR45XX, ADR43X, ADR345X Multiplexer: ADG5207, ADG120x Isolator: ADuM141E LDO: ADP7118

CN-0385: 18-bit, 2MPS Isolated Multiplexed Data

Acquisition System

IBIS Model

FPGA Code

Technical Article on Analog Dialogue (To be published in

Dec 2016)

Engineer Zone: Precision ADCs

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17

Preliminary Results: Typical Linearity Plot

© Analog Devices, Inc. 2016, all rights reserved.

AD4020: 20-Bit, 1MSPS Precision SAR ADC

Resolution VREF VDD Interface Input Package

20 Bits 2.4V to 5.1V 1.8VSPI

1.8V/2.5V/3V/5VDifferential

±VREF

10-ld MSOP 3x4.9mm

10-ld LFCSP 3x3mm

DNL: +/- 0.66 ppm

INL: +1.62/-1.05 ppm

Benefits and Features

Ease of Use

High Performance

INL: ± 3 ppm Max Guaranteed

DNL: 20-bit No Missing Codes

Throughput: 1 MSPS

SNR: 101dB typ @ 1Khz

THD: -123dB typ @ 1Khz

True differential analog input range: ±VREF

0 V to VREF with VREF between 2.4 V to 5.1 V

Low Power

12 mW typ @ 1MSPS (Total)

Small Form Factor

Guaranteed Operation: - 40°C to +125°C

Structural Health Monitoring Demo

AD4003 is used within a high precision data acquisition solution to sequentially digitise multiple sensor types that monintor vitals of railway tracks.

Accelerometer (ADXL354), AMR Magnetic Sensor (ADA4571), Force/Pressure Sensor

Results sent to Cloud, displayed on Dashboard

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FSR SENSOR (x2)

ADXL354 (x2)

XY

MEMS

ADA4571

AMR

..

..

AD4003MUX DRIVER

Conclusion

The AD400x family

16/18/20-bits SAR ADCs

Pin-for-pin compatible with AD798x/AD769x ADC Family

Pseudo-differential / Differential analog inputs

AD4000: 16-bit, 2MSPS Pseudo-Differential Precision SAR ADC (Released)

Different sample rate grades

Ease of Use Features

High input impedance mode and span compression reduces the design challenge associated with the ADC driver stage and increases the flexibility in amplifier selection.

Low SPI clock rate reduces latency requirements on digital isolators

High Performance Improves measurement accuracy, sensitivity and repeatability High throughput improves control loop response time

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QUESTIONS

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