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Overview of Digital IC Design Flow
Qiuzhong Wu
Phases of Design Flow• Phase 1: Design Planning
– From application requirements to specifications• Phase 2: Design Implementation and Verification
– From SPEC to layout (GDSII)• Phase 3: Design Review and Tape-out
– Function, timing etc.
2
Phase 1 Tasks
• Define Specifications Based on the Application Requirements
• HW/SW Partition• Algorithm Design• Architecture Design• Design Partition (Clock, Power etc)• Define the SPEC of Sub-blocks• Effort Estimation and Resources Allocation
3
Phase 2 Tasks
• Design Implementation and Verification– Logic design and verification– Physical design and verification
• Timing Closure• Power Optimization• Area Refinement
4
Phase 3 Tasks
• Design Review• ECO (Engineering Change Order)• Tape-out
5
Phase 1: Design Planning
Flow chart of Phase 1
7
Specifications
• Function Specification• IO Specification• Interface Protocol Specification• Characteristics Specification
– Speed– Power– Area
8
Algorithm Design
• Model the system in high-level language– MATLAB– C/C++– SystemC– SystemVerilog
• Purposes– Understanding of the system– Algorithm design and comparison– Test-Bench and golden files generation
9
Architecture Design
• Computation Architecture• Data Path Architecture• Control Path Architecture• Operation Reuse• Clock and Reset Strategy
10
Design Partition
• Function Partition• Clock Domain Partition• Power Domain Partition• Full custom design versus standard cell
based design
11
Module SPEC Definition
• After design partition, the system is divided into separate modules with determinate functions.
• Define specification of each module– To carry out implementation in parallel– Design and verification should be done module by
module– Easy to implement and debug
12
Phase 2: Design Implementation
Flow Chart of Phase 2
14
RTL Design
15
RTL Coding• RTL: Register Transfer Level • Verilog-HDL/VHDL (Hardware Description Language)
are the two mainstream hardware description languages• Behavior Description VS. Architecture Description
module mux_beh(out, a, b, sel)
output outp
input a, b, sel,
assign out=(sel==0)?a:b;
endmodule
module mux_str(out, a, b, sel)
output outp
input a, b, sel,
not gate1(net1,sel);
and gate2(net2, a, net1);
and gate3(net3, b, sel);
or gate4(out, net2, net3);
endmodule 16
RTL Purification• Find out code defects in RTL level• Make the code more readable and predictable• Assure compatibility with most tools• Find out some possible timing problems in RTL level
17
RTL Code
Coding Rules Checking
violation
To Next Step
Coding RulesCode Revising
Yes
No
RTL Simulation
• For function verification (No timing Information)– Check points– Compare the simulation
result with golden behavior model
• Debug• Coverage
– Function coverage– Code coverage
RTL Code
Simulation
Pass
To Next Step
Test BenchesDebug
Meet
Coverage Analysis
No
No
Yes
Yes
18
FPGA Verification• FPGA: Field-Programmable Gate Array• Basic FPGA verification Flow
– Design Input (HDL, Schematic etc.)– Compile and Synthesis– Place and Route– Function Checking
• Advantages:– Easy to implement (Comparing to manufacturing)– Easy to verify (Comparing to Simulation)
• Disadvantages:– Can’t cover timing issue 19
Logic Synthesis
• Logic synthesis is the process of converting a high level description of design into an optimized gate level representation
• Logic synthesis uses standard cell libraries which have simple cells, such as basic logic gates like and, or, and nor, or macro cells, such as adder, mux, memory, and special flip-flops.
• The designer would first understand the architectural description. Then he/she would consider design constraints such as timing, area, testability, and power
20
Formal Verification• Formal verification is the use of mathematical
techniques to ensure that a design conforms to some precisely expressed notion of functional correctness.
• A particular formal verification problem of great interest in EDA is equivalence checking.
• Why “Formal Verification”– Find more bugs– Find bugs faster– Find bugs earlier
21
Formal Verification in Design Flow
22
DFT Synthesis• DFT
– Design For Testability– Assures high-quality integrated circuits by screening out
devices with manufacturing defects• Function Testing VS. Manufacturing Testing
– Functional testing verifies that your circuit performs as it is intended to perform.
– Manufacturing testing verifies that your circuit does not have manufacturing defects by focusing on circuit structure rather than functional behavior.
23
Manufacturing Defects and Modeling
• Manufacturing defects– Power or ground shorts– Open interconnect on the die caused by dust
particles– Short-circuited source or drain on the transistor
caused by metal spike-through• Modeling of manufacturing defects
– Stuck-at Fault Models– State Table Models
24
Scan Design Techniques• Internal Scan Design
– Scan Cell– Scan Chain
The modified sequential cells are chained together to form one or more large shift registers. These shift registers are called scan chains or scan paths. The sequential cells connected in a scan chain are scan controllable and scan observable.
25
Scan Insertion
26
Place and Route
27
Static Timing Analysis• STA
– Static Timing Analysis is a method of validating the timing performance of a design by checking all possible paths for timing violations.
• STA VS Dynamic Simulation– Static timing analysis is much faster– Static timing analysis is also more thorough– static timing analysis can only check the timing, not the
functionality
28
Timing Paths (1)• The first step of timing analysis is to break the
design down into a set of timing paths. Each path has a startpoint and an endpoint.
• The startpoint of a path is a clock pin of a sequential element, or possibly an input port of the design (because the input data can be launched from some external source). The endpoint of a path is a data input pin of a sequential element, or possibly an output port of the design
29
Timing Paths (2)
30
Special Timing Paths (1)• Special timing paths
– Clock path (a path from a clock input port or cell pin, through one or more buffers or inverters, to the clock pin of a sequential element) for data setup and hold checks
– Clock-gating path (a path from an input port to a clock-gating element) for clock-gating setup and hold checks
– Asynchronous path (a path from an input port to an asynchronous set or clear pin of a sequential element) for recovery and removal checks
31
Special Timing Paths (2)
32
Delay Calculation• SDF
– The Standard Delay Format (SDF) file stores the timing data generated by EDA tools for use at any stage in the design process. The data in the SDF file is represented in a tool-independent way and can include Delays, Timing checks and Timing constraints etc.
• Cell delay– the amount of delay from input to output of a logic gate in a path.
(CELL(CELLTYPE "HDAND3D1")
(INSTANCE I_BMI_PACKET/U321)(DELAY
(ABSOLUTE(IOPATH A1 Z (0.1015:0.1015:0.1015) (0.0979:0.0979:0.0979))
(IOPATH A2 Z (0.0982:0.0982:0.0982) (0.1063:0.1063:0.1063))(IOPATH A3 Z (0.1195:0.1195:0.1195) (0.1371:0.1371:0.1371))
))
))
)
• Net delay– amount of delay from the output of a cell to the input of the next cell in a
timing path.(INTERCONNECT I_BMI_PACKET/U493/Z I_BMI_PACKET/U34/A1 (0.021:0.021:0.021) (0.0204:0.0204:0.0204)) 33
Setup and Hold Checking for Flip-Flops
34
Setup and Hold Checking for Latches
35
Timing Exceptions• False path – A path that is never sensitized due to the logic
configuration, expected data sequence, or operating mode.• Multicycle path – A path designed to take more than one
clock cycle from launch to capture.• Minimum/maximum delay path – A path that must meet a
delay constraint that you specify explicitly as a time value.
36
STA FlowRead the design data
Constrain the design
Specify the environment and analysis conditions
Check the design and analysis setup
Perform a full analysis and examine the results
37
Post-layout Simulation
• Post-layout simulation—simulate the netlist after place and route with the delay timing information (SDF), use the same test-benches for RTL simulation.
• Purpose– Function checking– Timing checking
• Post-layout simulation is slow compared to RTL simulation.
38
Phase 3: Design Review and Tape-out
39
Design Review
• After the P&R, review the whole design to make sure– Function– Timing– Area – Power– ….
40
Engineering Change Order• In chip design, ECO is the process of inserting a
logic change directly into the Netlist/Layout after they have already been processed by an automatic tool.
• Before the chip masks are made, ECOs are usually done to save time by avoiding to run the whole design procedure.
• After masks have been made, ECOs may be done to save money by changing the layers as least as possible.
41
ECO ExampleModule ABC();….Y=A&&B;……endmodule
Module ABC();….NAND2X1 gate1(Y,A,B);……endmodule
Module ABC();….Y=A||B;……endmodule
Module ABC();….NOR2X1 gate1(Y,A,B);……endmodule
42
Tape Out• The process of transmitting the data to a foundry
who will build your device is called “tape-out”…you are sending your magnetic tape out.
• Standard format is GDSII (“Gerber Data Stream Information Interchange”). It includes information on the layers of your design and the 2D geometries.
• Other file formats:– CIF (Caltech Interchange Format)– DXF (Drawing Exchange Format…AutoCAD)– …
43
Design Abstract (1)
44
Design Abstract (2) Design Abstract (3)
EDA Tools Grouped by FunctionsFunctions Tools Vendors
HDL Simulation Modelsim, NCSIM, VCS Mentor, Cadence, Synopsys
HDL Purification nLint Novas
Code Coverage Analyses ICT, Covermeter Cadence, Synopsys
Logic Synthesis Design Compiler, Encounter RTL Compiler, Synplify
Synopsys, Cadence, Synplicity
Power Analysis PrimePower, VoltageStorm, Blast Rail
Synopsys, Cadence, Magma
DFT and ATPG Tools Fastscan, Flextest, Tetramax Mentor, Mentor, Synopsys
Static Timing Analysis PrimeTime, Encounter Timing Synopsys, Cadence
Dynamic Timing Analysis Nanosim, Mach TA Synopsys, Mentor
IC Layout Virtuoso, ADS Cadence, Agilent
IC Layout Verification Calibre, Diva/Assura, Hercules Mentor, Cadence, Synopsys
RC Extraction Calibre, Diva, Star-RCXT Mentor, Cadence, Synopsys
IC Auto Place/Route Encounter, Astro, Blast Fusion Cadence, Synopsys, Magma
Signal Integrity Analysis Celtic, Blast Noise, PrimeTime Cadence, Magma, Synopsys
Formal Verification Formality Synopsys