PCIe - Samtec Microelectronicssuddendocs.samtec.com/ebrochures/pcie_user_manual.pdf · 4 DESCRIPTION PCIe® Active Optical Cable Assemblies are standard compatible cables for PCIe

SEPTEMBER 2013

PCIe®

Active Optical Cable AssemblyUSER’S MANUAL

COVERING:PCIEO Series

http://www.samtec.com

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COPYRIGHTS, TRADEMARKS AND PATENTS

Product names used herein are trademarks of their respective owners. All information and material in this publication are property of Samtec, Inc. All related rights are reserved. Samtec, Inc. does not authorize customers to make copies of the content for any use.

Terms of UseUse of this publication is limited to viewing the pages for evaluation or purchase. No permission is granted to the user to copy, print, distribute, transmit, display in public, or modify the contents of this document in any way.

DisclaimerThe information in this publication may change without notice. All materials published here are “As Is” and without implied or express warranties. Samtec, Inc. does not warrant that this publication will be without error, or that defects will be corrected. Samtec, Inc. makes every effort to present our customers an excellent and useful publication, but we do not warrant or represent the use of the materials here in terms of their accuracy, reliability or otherwise. Therefore, you agree that all access and use of this publication’s content is at your own risk.

PatentsPatents pending on technologies used within this product.

NEITHER SAMTEC, INC. NOR ANY PARTY INVOLVED IN CREATING, PRODUCING, OR DELIVERING THIS PUBLICATION SHALL BE LIABLE FOR ANY DIRECT, INCIDENTAL, CONSEQUENTIAL, INDIRECT, OR PUNITIVE DAMAGES ARISING OUT OF YOUR ACCESS, USE OR INABILITY TO ACCESS OR USE THIS PUBLICATION, OR ANY ERRORS OR OMISSIONS IN ITS CONTENT.

Copyright © 2013 Samtec, Inc.

FILE NO. E357212 I.T.E.

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TABLE OF CONTENTS

PCIe® is a registered trademark of PCI-SIG®.

Note: Samtec PCIe® over Fiber systems have successfully passed the PCI-SIG® Compliance Workshop #85; however as with all PCIe® based systems, there is a risk of interoperability issues with specific systems. Samtec recommends discussing your system with our Optical Group prior to final design. Please contact [email protected].

DESCRIPTION

PCIe® Active Optical Cable Assemblies.......................................... 4

Fiber Cable ..................................................................................... 5

Cable Connector ............................................................................ 5

SYSTEM REQUIREMENTS

Power ..............................................................................................6

Clock ................................................................................................6

Constant Clock (CC)

Spread-spectrum Clock (SSC)

Pre-emphasis ..................................................................................7

Extended Sync .................................................................................7

Detect ..............................................................................................7

Adaptor Cards ..................................................................................8

Auxiliary (Sideband) Signals.......................................................... 8

Equivalent Sideband IO Circuit ...................................................... 9

INSTALLATION

Connecting the AOC ...................................................................... 9

Power Sequence ............................................................................ 9

TECHNICAL INFORMATION

Specifications ......................................................................... 10-11

Connector Pin Assignment .................................................... 12, 14

Mechanical Dimensions ......................................................... 13, 15

ORDERING INFORMATION

PCIe® Active Optical Cable ..................................................... 13, 15


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DESCRIPTION

PCIe® Active Optical Cable Assemblies are standard compatible cables for PCIe® Gen 2 external cabling applications. PCIe® x4 trans-mits data on four independent, full-duplex optical channels and mates to a standard PCIe® x4 port. PCIe® H8 combines a bidirectional x4 channel device in a x8 form factor housing, mates to a standard PCIe® x8 port and links as an optical x4 link enabling longer run lengths with existing PCIe® Expansion and Extension systems. Each lane is capable of transmitting PCIe® signaling at Gen 1 (2.5 GT/s) and Gen 2 (5 GT/s). Although the cable theoretically supports Gen 3 (8 GT/s) data rates, the current Samtec PCIEA adaptor cards do not yet support it. Pre-standard external cabling support for Gen 3 has been successfully demonstrated with third party cards, please contact [email protected] for further details.

Cables are available up to a distance of 300 m. However, depending on PCIe® chipset capabilities, link throughput for very long distances may be reduced due to increased link round trip time. Some motherboards may fail to link at distances above 250 m. Please contact [email protected] about very long link length support.

PCIe® x4

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DESCRIPTION

The electrical to optical conversion circuitry is fully integrated into the connector housing at each end of the assembly, and the optical signal is transmitted over a small diameter optical fiber. The cable auxiliary signals (CPWRON, CPERST#, CPRSNT# and CWAKE#) are also transmitted over the optical link.

Fiber Cable used in the PCIe® AOC is a nonconductive, plenum rated cable with a 3 mm cable diameter and 30 mm minimum bend radius. OM2 fiber is used for cables of length <50 m. OM3 fiber is used for cables of length ≥50 m.

Cable Connector attached at each end of the fiber cable is a metalized housing that contains the electrical to optical components.

Note: Unlike traditional copper cable, active optical PCIe® cables are directional. One end must be connected to the host system (upstream direction), and the other to the target system (downstream direction). The ends of the cable are labeled as “host” and “target” and are not interchangeable.

PCIe® H8


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SYSTEM REQUIREMENTS

PowerThe PCIe® AOC requires the host and target system to provide 3.3 volts to connector pins B14 and B15 (and B16 for PCIe® H8 AOCs) at both ends of the cable assembly as described in the PCIe® cabling specification (optional feature). See the connector pin assignment on page 12 and 14.

Note: The PCIe® cabling specification specifies power as an “option,” and therefore, not all PCIe® systems provide power to the connector ports.

In systems that use the sideband signal “CWAKE#,” both ends of the Active Optical Cable assembly must be powered at all times, and therefore, they must be powered by Vaux. In systems that do not use CWAKE#, the cable ends may be powered by Vmain.

ClockConstant Clock (CC): Active Optical Cables require the use of a constant clocking scheme. The PCIe® AOC provides 100 MHz constant clock to the target end of the link as specified in the standard. Cables with a clock frequency of 100.3 MHz are also available, but this must be specified at the time of purchase.

Spread-spectrum Clock (SSC) is used in many systems running PCIe®. However, due to signaling technology limitations, the PCIe® standard cannot support SSC beyond 7 m of link length. In order to use a PCIe® Active Optical Cable assembly (of any length) in a system that uses SSC clocking, the SSC must be completely disabled at the host. If disabling the SSC is not possible, then a clock isolation adaptor card will be required to isolate the spread-spectrum clock.

Note: Some motherboard BIOS allow SSC to be disabled; however, in some cases, the disable function does not take effect until after enumera-tion. In other cases, disabling the SSC will only reduce its amplitude and will not force a change to constant clock operation. If SSC cannot be fully disabled, adaptor cards such as Samtec’s PCIEA Series that provide clock isolation must be used.

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Pre-emphasisTransmitter pre-emphasis is a SERDES setting used to pre-distort a signal to enable it to run longer distances over traditional copper cables. Optical cables do not have the same loss/degradation mechanisms as copper cables and will accurately represent the electrical signal input at the output. As a result, for best results, the pre-emphasis must be reduced to the minimum required to provide good signal quality at the connector.

Extended SyncThe extended sync bit in the link control register must be enabled to allow a minimum of 1,024 TS1 ordered sets to be sent during training. This is partially to compensate for the longer cable lengths used, as well as the methods used, to allow electrical idle over optical links.

DetectThe PCI Express® Base Specification defines a Detect circuit as part of the transmit that uses a common mode pulse to determine whether a receiver is connected. Since there is no electrical continuity over the optical fiber, a resistor network on the Tx data channel is used to simulate the response of a connected receiver. As a result, care should be taken to ensure that Detect is not used as a mechanism to determine whether a downstream port is connected.

SYSTEM REQUIREMENTS

Resistor Network

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Adaptor CardsA host adaptor card and a target adaptor card that are compatible with Active Optical Cables should be installed at each end of the link. The Samtec PCIEA Series adaptor cards have been optimized for both copper and optical interconnects and are available. Please contact [email protected] for further information.

SYSTEM REQUIREMENTS

Table 2: Minimum Sideband Implementation Requirements

Sideband Signal1 Driving End Function End State

CPERST# Host Reset High

CPRSNT# Target Cable Present Low

CPWRON Host Power On High

CWAKE# Target Host Wake-up High1 A “no sidebands” cable is available as an option for applications where sidebands are not required.

Auxiliary (Sideband) SignalsSignals (CPWRON, CPERST#, CPRSNT# and CWAKE#) are transmitted over the optical link. If sideband signals are not required, a “no side-bands” option is also available but requires callout at time of ordering.

Note: Auxiliary sideband signal usage and implementation over copper cable varies widely between systems. For Active Optical Cable assemblies, sideband signals should preferably be implemented following the PCIe® 2.0 standard. Table 2 shows the required states of the sidebands before enumeration/data transfer. If some of these are not used in a design, the signal should be pulled to the final end state to ensure compliance with Table 2.

Table 1: Compatible Adaptor Cards

Samtec Part Number Host / Target Cable Mate

PCIEA-4G2-H-01 Host PCIEO-4G2

PCIEA-4G2-T-01 Target PCIEO-4G2

PCIEA-8G2-H-01 Host PCIEO-H8G2

PCIEA-8G2-T-01 Target PCIEO-H8G2

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SYSTEM REQUIREMENTS

Equivalent Sideband IO CircuitThe sideband input signals are pulled high using an internal pull-up resistor of 20-50 kΩ. Refer to Table 3 to determine which sideband signals are inputs to the host end of the cable and which signals are inputs to the target end of the link.

Table 3: Sideband Signal Input / Output Reference

Sideband Signal Host Side Pull-up Target Side Pull-up

CPWRON Input Yes Output N/A

CPERST# Input No Output N/A

CPRSNT# Output N/A Input Yes

CWAKE# Output N/A Input Yes

INSTALLATION

Connecting the AOCPower to either the adaptor card or motherboard should be in the off state prior to installing the cable assembly (This is to ensure that the link is enumerated and not to prevent damage to the cable).

Refer to the label on the connector shell to identify the host end and the target end. Insert the host end of the assembly into the host card and the target end into the target card ensuring the connector is fully seated and the latching mechanism is fully engaged with the host connector. Incorrectly inserting the host into the target port and vice versa will prevent the cable from operating but should not cause electrical damage to the cable.

Power SequencePCIe® Active Optical Cables do not require a special powering sequence. But whether using an Active Optical Cable or a passive copper cable, it is critical that the target be powered prior to the PCIe® controller on the motherboard enumerates (searches and detects) all the PCIe® devices. There is a short delay from when the host is powered and then starts to enumerate, but to ensure that the target is powered prior to the host beginning enumeration it is good practice to apply power to the target side and then to the host side.


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Electrical Characteristics

Specifications Symbol Unit Min Typ. Max Notes

Data Rate (channel) GT/s 1 2.5/5.0/8.0 8.0 Gen 1 / Gen 2 / Gen 3

Differential Input Amplitude

VDI mV 300 1200 Peak-to-peak differential

Differential Output VDO mV 340 700 Peak-to-peak differential

Power Supply Voltage VCC1 V 3.15 3.3 3.45 Supplied through pins B14, B15 and B16

Power Supply Current ICC1 mA 230 Per connector end

Power Consumption PDISS W 0.75* 1.0** Per connector end

Bit Error Rate BER 10-15 For AOC

* Nominal supply voltage, room temperature ** Maximum supply voltage

General Characteristics

Specifications Symbol Unit Min Max

Operating Case TCASE °C 0 70

Operating Humidity %RH 5 90**

Storage Temperature Range TSTO °C -40 85

Link Distance m 5 300*

*Some motherboards may fail to link at distances above 250 m. See page 4.** Noncondensing

Specifications

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Specifications

Table 4: Regulatory and Compliance

Feature Test Method Performance

Electrostatic Discharge (ESD) to the electrical contact

JEDEC Human Body Model (HBM)(JESD22-A114-B)

JEDEC Machine Model (MM)(JESD22-A115-A)

1 kV

TBD

Electrostatic Discharge (ESD) to module case Variation of IEC 61000-4-2 15 kV

Electromagnetic Interface (EMI) FCC part 14 CENELEC EN55022 (CISPR 22A) VCCI class 1 TBD

EMI Immunity Variation of IEC 61000-4-3 10 V/m, 80-1000 Mz

Laser eye safety IEC 60835-1 amendment 2 CFR 21 section 1040 Class 1

RoHS compliance RoHS 6/6 directive 2002/95/EC amendment 4054 (2005/747/EC)

Class 1 LASER PRODUCTper IEC 60825-1 Ed. 2 (2007)

Complies with FDA performance standards for laser products except for deviations pursuant to Laser Notice No. 50, dated June 24, 2007.

Manufacturing Location: Samtec, 520 Park East Blvd., New Albany, IN 47150

Caution - Use of controls or adjustments or performance of procedures other than those specified herein may result in hazardous radiation exposure.


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PCIe® x4 Connector Pin Assignment

GND A1 B1 GND

PET p0 A2 Transmitter Lane 0 Receiver Lane 0 B2 PER p0

PET n0 A3 Transmitter Lane 0 Receiver Lane 0 B3 PER n0

GND A4 B4 GND



GND A7 B7 GND



GND A10 B10 GND



GND A13 B13 GND

CREFCLK+ A14 See Notes 1, 2 See Note 3 B14 3.3 V PWR

CREFCLK- A15 See Notes 1, 2 See Note 3 B15 3.3 V PWR

GND A16 See Note 4 B16 PWR RTN

SB_RTN A17 See Note 4 B17 PWR RTN

CPRSNT# A18 See Note 1 See Note 1 B18 CWAKE#

CPWRON A19 See Note 1 See Note 1 B19 CPERST#

1 Propagation of the reference clock is directional. Target side of AOC is an input and host side is an output. The clock is not passed through the cable and is instead recreated in the target end. 2 Standard product produces a 100 MHz clock; 100.3 MHz and no clock AOCs can be ordered (see Ordering Information).3 Must be connected to 3.3 V (+/-5%) Vaux or Vmain4 Must be connected to Power Ground

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PCIEO - 4G2 - XXX.X - XX

Product CategorySpeedx4 channel device 4G2

Fiber Length (m)Length in meters = 5.0 to 300.0(5 m to 300 m. See www.samtec.com?PCIEO)

Specific Product VariantClock Frequency Sidebands

11 100 MHz Standard12 100 MHz No Sidebands13 100.3 MHz Standard14 100.3 MHz No Sidebands15 No CK Standard16 No CK No Sidebands

PCIe® x4 Active Optical Cable

Row B, Pin 19

Row A, Pin 1

PCIe® x4 Connector Pin Assignment

PCIe® x4 Mechanical Dimensions

(21,94).864

(5,54).218

(71,30) 2.807

Male or female MTP end termination also available. Call Samtec.

Front View - Adaptor Card Port


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PCIe® H8 Connector Pin AssignmentGND A1 GND GND B1 GND

PETp0 A2 Transmit Lane 0+ Receive Lane 0+ B2 PERp0

PETn0 A3 Transmit Lane 0- Receive Lane 0- B3 PERn0

GND A4 GND GND B4 GND










CREFCLKp A14 Reference Clock + (1) 3.3 V Power Supply B14 PWR

CREFCLKn A15 Reference Clock - (1) 3.3 V Power Supply B15 PWR

GND A16 GND 3.3 V Power Supply B16 PWR

RSVD A17 Not Connected Power Supply GND B17 PWR_RTN

RSVD A18 Not Connected Power Supply GND B18 PWR_RTN

SB_RTN A19 Sideband Return Power Supply GND B19 PWR_RTN

CPRSNT# A20 Cable Present Cable Wake B20 CWAKE#

CPWRON A21 Cable Power On Reset B21 CPERST#


PETp4 A23 Not Connected (2) Not Connected B23 PERp4

PETn4 A24 Not Connected (2) Not Connected B24 PERn4










GND A34 GND GND B34 GND1 Propagation of the reference clock is directional. Target side of AOC is an input and host side is an output. The clock is not passed through the cable and is instead recreated in the target end. Standard product produces a 100 MHz clock; 100.3 MHz and no clock AOCs can be ordered (see Ordering Information).

2 No through data connection. Signals are connected to ground through Detect Attenuator Network shown on page 7.

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PCIEO - H8G2 - XXX.X - XX

Product CategorySpeedx4 channel device in a x8 form factor

H8G2

Fiber Length (m)Length in meters = 5.0 to 300.0(5 m to 300 m. See www.samtec.com?PCIEO)

Specific Product VariantClock Frequency Sidebands

11 100 MHz Standard12 100 MHz No Sidebands13 100.3 MHz Standard14 100.3 MHz No Sidebands15 No CK Standard16 No CK No Sidebands

PCIe® H8 Active Optical Cable

Row B, Pin 34

Row A, Pin 1

PCIe® H8 Connector Pin Assignment

PCIe® H8 Mechanical Dimensions

(5,54).218

(71,30) 2.807

(33,94)1.336

Male or female MTP end termination also available. Call Samtec.

Front View - Adaptor Card Port


SUDDEN SERVICE

For more information visit www.samtec.com/active-optics or contact

Samtec’s Optical Group at [email protected]

All designs, specifications and components are preliminary and subject to change without notice.


Documents

PCIe - Samtec Microelectronicssuddendocs.samtec.com/ebrochures/pcie_user_manual.pdf · 4 DESCRIPTION PCIe® Active Optical Cable Assemblies are standard compatible cables for PCIe