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A Quick User Guide on

Peking University Resistive Random Access Memory (RRAM)

SPICE Model Version: 2.1

Patent Pending.

Copyright Peking University 2019

All rights reserved.

March 19th, 2019

Contributors: Prof. Jinfeng Kang, Prof. Xiaoyan Liu,

Dr. Peng Huang, Dr.Yudi Zhao

Weijie Xu, Haitong Li

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Terms of Use Peking University and the authors provide these model files to you subject to the Terms of Use, which may be updated by us from time to time without notice to you. By using the Peking University RRAM SPICE Model (“Model”), you acknowledge that you have read the most up-to-date Terms of Use and agree to abide by the Terms of Use (“Terms”). These Terms include, but are not limited to, the following: License Agreement Peking University grants you a non-transferable license to use this Model on a single computer for a single user (You). This license may not be sub-leased, sub-licensed, sold or otherwise transferred to another individual, company, or third party. Peking University reserves the right to revoke this license at any time, at which point you must stop using the Model and delete all Model files. Acceptable Usage This Model shall be used solely for non-commercial academic and industrial research by the individual to whom this Model, and its license, is granted. The Model and its files may not be used, in part or in whole, by another individual, institution, or third party other than the original individual to whom this Model, and its license, is granted without prior written approval from Peking University. The Model and its files may not be copied, redistributed, or otherwise transferred, in part or in whole, to a third party without prior written approval from Peking University. You agree not to disclose the ideas and inventions inherent in this Model to other individuals, institutions, or third parties. You further agree not to decompile or otherwise reverse-engineer this Model, in part or in whole; not to decompose the Model and its files; and not to misrepresent the Models and its files through modifications and add-ons. Additional Terms You agree to appropriately acknowledge and reference the Model work by Peking University in all publications, presentations, and/or other works derived from the use, in part or in whole, of this Model and/or its variants. (See Section 5. References and additional references on the Website.) Disclaimer and Limitation of Liability

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This Model is provided to you “As Is,” without warranty of any kind, either expressed or implied. By using this Model, you agree that you and your representing institution or company will not hold Peking University, the Model inventors, the Model authors, as well as all other contributing members to the Model and its official distribution, liable for damage of any kind resulting from the download or use of the Model and its files and documents. Legal Notice This Model, including the files, documents, and inherent ideas, are protected by Chinese Copyright Law and Chinese Patent Law. Peking University and the authors reserve all rights. Unauthorized reproduction the files and/or the documents included in the Model package is unlawful.

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1. Model Files This documentation pertains to the model files in the PKU RRAM SPICE Model v2.1 package. A brief summary and description of the model files included in the package are shown in Table 1.

Table 1. Summary of Model Files File Name Description RRAM_v_2_1.va RRAM SPICE Model File

Additional Files

File Name Description User Guide RRAM_Model_v2.1_Quick_User_Guide.pdf This User Guide in PDF format. References/Publications [1]-[10] Sample Decks DC_RRAM_SET.sp Example HSPICE decks: DC SET operation DC_RRAM_RESET.sp Example HSPICE decks: DC RESET operation AC_RRAM_SET.sp Example HSPICE decks: AC SET pulse AC_RRAM_RESET.sp Example HSPICE decks: AC RESET pulse

The package should include all the sample decks, plus this User Guide document. A summary of the model scope is in 2. Scope of the Model; details regarding model usage and instantiation can be found in 3. Model Usage; and 4. Sample results describes the sample results using our model and discussion concerned.

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2. Scope of the Model

Table 2 below summarizes the scope of the model.

Table 2. Summary of the Scope of the RRAM Model Device Types Metal-Oxide Bipolar RRAM Device Dimensions: Switching Layer Thickness Unlimited (typical: ~3 nm - 10 nm) Formed filament width Unlimited (typical: ~1 nm - 5 nm) Initial filament width <formed CF width (typical: ~0.5 nm) Cell Size ~5 nm × 5 nm to 100 μm × 100 μm

Number of RRAMs / device 1 to Unlimited Physics Aspects & Practical Non-idealities:

Filament Growth Two-dimensional growth of one dominant filament Electronic Conduction Combined: ohmic & generalized tunneling mechanism Device parasitic effects RC components of MIM structure Temperature and Heat Conduction Joule heating

Variations: Resistance States Included Variations: Switching Voltages Included Dynamic Current Fluctuations Included for RESET process

This model is designed for fast and accurate simulation of metal-oxide based RRAM devices [1]. The model captures typical DC and AC electrical behaviors of metal-oxide based RRAM devices with physics-based compact model descriptions. The model assumes a conductive filament (CF) evolution process described by a change of the CF geometry during SET/RESET processes under various bias conditions [2]. The core of the model is a three-dimension description of CF, which includes both CF gap region and the CF width as the control variables, where the CF dimensions are not limited [3]. Parasitic effects are also modeled, including both parasitic resistance of switching layer and electrodes, and parasitic MIM capacitance. The mechanism and the structure are depicted in Fig. 1 and Fig. 2 below. Fig. 1 illustrates the physical process of the switching operation in an RRAM device [2]. Fig. 2 shows the model assumptions for the filament evolutions processes and corresponding models of electrical transport and parasitic effects [6]. Intrinsic variation effects such as statistical distributions of resistance states and switching voltages after SET/RESET processes as well as current fluctuations during RESET are supported, which has made this model the first one supporting the complete suite of RRAM variation effects to date. Since the model invoked in HSPICE or other SPICE software is a two-terminal component, it can thus be easily implemented in any circuit including memory array structures such as 1R, 1D1R, 1T1R and 1S1R [5]-[6].

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Fig. 1 Schematic physical process of resistive switching used in the model, including the generation of oxygen vacancies, oxygen ions hopping, oxygen ions absorbed and released by the electrode, recombination between oxygen vacancies and oxygen ions, local temperature increase due to local current and electron transport.

Fig. 2 Illustration of the RRAM SPICE model. (a) Equivalent circuit of RRAM cell composed of resistive switching element and parasitic elements. (b) Schematic of conductive filament evolution. (c) Equivalent circuit of resistive switching element modeling the metal-like and hopping current paths. (d) Adopted array configuration from Ref. [6].

(d) (a) (b) (c)

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3. Model Usage

The model is developed in Verilog-A, and it can be instantiated in HSPICE or other SPICE tools (with the appropriate Verilog-A support). Here we recommend that user adopt linux system as simulation environment. We use Hspice-2016_linux as our simulation tool. This section illustrates how to instantiate the model in HSPICE.

3.1 Model Variants – Standard Model vs. Dynamic Model Two model variants are available: 1) Standard RRAM Model (if parameter “sw” == 0)2) Dynamic RRAM Model (if parameter “sw” == 1)The Standard Model is recommended for describing the ensemble-average DC and ACswitching behavior. And the Standard Model is adopted as default. The Dynamic Model isrecommended for applications that involve dynamic current fluctuations and variations ofRRAM cell characteristics.

3.2 Convergence and Settings For improved accuracy and convergence, include the following commands at the beginning of the SPICE deck: *************************************************** .option converge = 0 .option RUNLVL = 6 .option METHOD=GEAR ***************************************************

3.3 Model Instantiation To instantiate the devices in the model, the library (model file) must be included at the beginning of the SPICE deck. If the model file and your test file are located in the same folder, you can use the syntax below. Otherwise, you should specify the absolute address where your model file is saved. .hdl RRAM_v_2_1.va

To instantiate an RRAM device, use the appropriate syntax below. The usage of this model is similar to that of the Si CMOS transistor model. * Standard RRAM ModelX_RRAM TE BE RRAM_v_2_1 < sw = 0 Parameter_Name = Parameter_Value>*Dynamic RRAM ModelX_RRAM TE BE RRAM_v_2_1 < sw = 1 Parameter_Name = Parameter_Value>The port definitions, TE and BE, for the RRAM are for the top electrode and the bottomelectrode, respectively. The ports TE and BE are not interchangeable in this model due tonature of the asymmetry of the RRAM programming mechanism and the details of the modelimplementation.

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The device parameters indicated in the < ... > are optional and can be set differently for each device instance. If the device parameters are omitted, default or global values set in the parameter definition file are used. The syntax for setting a parameter is: parameter_name = value or parameter Table 3 below lists the definitions and default values of the device parameters. 1 The range listed represents reasonable values based on experimental observations and physical insights. The units should be the same as the default values.

Table 3. Model Parameter Descriptions and Default Values

Parameters Descriptions Default Value Suggested Range1

I0

ρ

a

f Ea Eh Ei

αa & αh γ

Z & e

Rth

RH

RL

CP

L0

x0

WCF

Weff

w0

XT

VT

T0

sw

deltaGap

deltaCF

crit_x

hopping current density

resistivity of the CF

distance between VO

VO vibration frequency average active energy of VO

hopping barrier of O2- electrode/oxide interface

energy enhancement factor voltage enhancement factor

charge number & unit charge effective thermal resistance

oxide parasitic resistance

electrode contact resistance

electrode parasitic capacitance

initial switching layer length

initial gap length

switching layer width

effective width

initial CF width

characteristic gap length

characteristic voltage

ambient temperature

“model switch”

Gap varying rate

CF width varying rate

Gap variation fitting point

1013 A/m2

19.635 μΩ·m

0.25 nm

1013 Hz

0.7 eV

1.12 eV

0.82 eV

0.75 nm

1.5

2 & e

5×105 K/W

2e9 Ω

20 Ω

1 fF

5 nm

{L0, 0}

5 nm

0.5 nm

{0.5 nm, WCF}

0.4nm

0.4 V

300 K

0

4e-5 m/s

1e-4 m/s

0.5 nm

[1010,1015]

[0.1,1000]

[0.2,0.4]

[8×1012,1.2×1013]

[0.5,1.2]

[0.8,1.4]

[0.6,1.2]

0.75

1.5

2 & e

[2×105,106]

[106,3×109]

(0,100]

(0,25]

[1,10]

L0/0

[1,10]

0.5

(0,WCF]

[0.3,0.8]

[0.2,0.5]

(100,500)

{0,1}

[0,10-4]

[0,5×10-4]

[0, L0]

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4. Sample Results

Fig. 3 shows the typical DC electrical characteristics of RRAM. Fig. 3 (a) is a simplified structure diagram of a fabricated TiN/HfOx/Pt RRAM cell measured for the experimental data. The experimental data is plotted in blue scatters in Fig. 3 (c), which is fitted by our model in red line in the same figure. The key parameters used in the model are listed in Fig. 3 (b). Note that not all parameters are listed here for reason of limited space, but the given parameters are the key parameters that influence the resistive switching behaviors of RRAM.

BE: Pt

RS layer:

HfOx

TE: TiN

SET fitting Ea=0.83 VT=0.3 XT=0.45e-9 Vg=1.41RESET fitting Ea=0.84 Eh=0.95

Fig. 3 Typical DC I-V curves. (a) The structure of the simulated and measured RRAM. TE: top electrode, RS layer: resistance switching layer, BE: bottom electrode. (b) The key parameters used in the model. (c) I-V curves of the experimental data and the model calculated data. (d)&(e) I-V curves with parameter change.

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The DC I-V curves using different key parameters with varying values are plotted in Fig. 3(d)&(e).

Below is a short introduction of the key parameters that influence the resistive switching characteristics of RRAM. For further analysis purpose, users can print values of key variables in the model by calling system functions. As for the usage of system functions, please refer to the Verilog-A/AMS language documents.

Parameter VT is critical to the calculation of current, which determines the hopping current outside the conductive filament. For details, please refer to the model file and the Ref. [2].

Parameter Ea controls the rate of oxygen vacancy generation during SET process. In the model, decreasing Ea leads to the abrupt current increase at a lower voltage

Vg is the gate voltage of NMOS which is used as a selector and current-limiter. With smaller Vg, the maximum current will be limited to a lower level.

Parameter Ei controls the rate of the electrode releasing O2-, which is the first step of RESET process. The first stage will sustain a short time when voltage starts rising. But when it varies in a relatively large range, RESET voltage will be affected.

Parameter Eh is critical to the rate of the recombination between oxygen vacancies and O2-, which is the second stage during the RESET process. It will impact RESET voltage and then affects the current level during RESET.

For more parameter descriptions, users can look up to our model file.

BE: Pt

RS layer: TaOx

TE: Pt

Fig. 4 DC I-V curves of the Pt/TaOx/Pt RRAM cell. The experimental data is from Ref. [7]. (a) Material structure of the RRAM cell. (b) I-V curves of the experimental data and the model calculated data

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Fig. 4 and Fig. 5 are two sets of DC I-V curves with different materials. The experimental data in these two figures are extracted from Ref. [7] and [8]. To be specific, Fig. 4 shows a structure of Pt/TaOx/Pt, while the structure in Fig. 5 is Ti/NiO/Pt. From the figures above, we demonstrate that our model has a wide coverage of RRAM material system, so the users can utilize our model by adjusting the key material parameters based on the fabricated RRAM.

BE: Pt

RS layer: NiO

TE: Ti

Fig. 5 DC I-V curves of the Ti/NiO/Pt RRAM cell. The experimental data is from Ref. [8]. (a) Material structure of the RRAM cell. (b) I-V curves of the experimental data and the model calculated data

Fig. 6 Typical transient response during (a) SET and (b) RESET process.

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Fig. 6 is the transient response during SET process and RESET process simulated by our model. The experimental data is from Ref. [3]. An excellent agreement can be seen from the figures above. For the parameters, users can refer to the introduction above or look up to the model file.

Fig. 7 demonstrates another set of transient response during SET and RESET process. The experimental data are from Ref. [9]. By calibrating the key parameters in the model, a pretty good agreement can be reached between the simulation results and the experimental data.

Fig. 7 Another set of transient response under (a) SET and (b) RESET conditions.

Fig. 8 The transient fluctuation of resistance varies from cycle to cycle. (a) Simulated results. (b) Experimental data.

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Fig. 8 shows the transient fluctuation of resistance varies from cycle to cycle. The transient fluctuation of the resistance is due to the random generation and recombination of the oxygen vacancies during resistive switching. The experimental data is extracted from Ref. [10]. The HRS resistance in the experimental data shows a large scale of variation, while our simulation result shows a pretty good consistency. In the model, the dynamic current fluctuations and variations can be included by turning the parameter “sw” to “1”. This operation will add a random variation to the rate of change in filament evolution during SET and RESET process with Gaussian distribution. Users can adjust the parameters concerned to the Gaussian distribution to get different scale of random variation. For more details, please refer to the “sw” section in the model file.

Fig. 9 shows the transient response of the RRAM in the 1T1R array during SET and RESET process and the impacts of array size on the switching characteristics. The array configuration is exhibited in Fig. 2(d). For the transistor in the 1T-1R cell, we adopted the simplest MOSFET model (level 1 in spice library). The simulation is based on the worst scenario: the selected cell is located at the farthest corner and the other cells are in LRS.

For SET process, the simulation results reveal that with the array size enlarging, the maximum current of the selected cell presents a decreasing trend. It indicates that the current leakage in WL branch increase with the array size, causing the gate voltage of the NMOS decreasing with the array size. For RESET process, it can be seen that the slope of the initial rising current descends with the array size. The decreasing rising rate of the initial current manifests that the RC delay is more significant with the larger array size during RESET

Fig. 9 Transient response during (a) SET and (b) RESET process of RRAM in the 1T1R array with varying array size.

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5. References

[1] H.-S.P. Wong, H.-Y. Lee, S. Yu, Y.-S. Chen, Y. Wu, P.-S. Chen, B. Lee, F. Chen, and M.-J.Tsai, “Metal–Oxide RRAM,” Proceedings of IEEE, vol.100, no.6, pp.1951-1970, 2012.DOI: 10.1109/JPROC.2012.2190369

[2] P. Huang, X.Y. Liu, W.H. Li, Y.X. Deng, B. Chen, Y. Lu, B. Gao, L. Zeng, K.L. Wei, G. Du,X. Zhang, J.F. Kang, “A Physical Based Analytic Model of RRAM Operation for CircuitSimulation,” IEEE International Electron Devices Meeting (IEDM), pp.605-608, 2012.DOI:10.1109/iedm.2012.6479110

[3] P. Huang, X.Y. Liu, B. Chen, H. Li, Y.J. Wang, Y.X. Deng, K.L. Wei, L. Zeng, B. Gao, G. Du,X. Zhang, and J.F. Kang, “A Physics Based Compact Model of Metal Oxide Based RRAM DCand AC Operation,” IEEE Trans. Electron Devices, vol. 60, no.12, pp. 4090-4097, 2013.DOI: 10.1109/ted.2013.2287755

[4] P. Huang, B. Chen, H. Li, Z. Chen, B. Gao, X.Y. Liu and J.F. Kang, “Parameters Extraction onHfOX based RRAM,” European Solid-State Device Research Conference (ESSDERC), pp.250-253,2014. DOI:10.1109/essderc.2014.6948807

[5] H. Li, Z. Jiang, P. Huang, Y. Wu, H.-Y. Chen, B. Gao, X.Y. Liu, J.F. Kang, and H.-S.P. Wong,“Variation-aware, reliability-emphasized design and optimization of RRAM using SPICEmodel,” Design, Automation & Test in Europe (DATE), pp.1426-1430, 2015.DOI:10.7873/date.2015.0362

[6] H. Li, P. Huang, B. Gao, B. Chen, X. Liu, and J. Kang, “A SPICE Model of Resistive RandomAccess Memory for Large-Scale Memory Array Simulation,” IEEE Electron Device Lett., vol.35, no.2, pp.211-213, 2014. DOI:10.1109/LED.2013.2293354

[7] Ji Hyun Hur, Myoung-Jae Lee, Chang Bum Lee, Young-Bae Kim, and Chang-Jung Kim,“Modeling for bipolar resistive memory switching in transition-metal oxides,” Physical ReviewB, vol.82, no.15, pp.155321, 2010. DOI:10.1103/PhysRevB.82.155321

[8] G. Ma, X. Tang, H. Su, Y. Li, H. Zhang, and Z. Zhong, “Effects of Standard Free Energy on

NiO Bipolar Resistive Switching Devices,” IEEE Trans. Electron Devices, vol. 61, no.5, pp.

1237-1240, 2014. DOI: 10.1109/TED.2014.2309975

[9] S. Deora, G. Bersuker, K. Matthews, D. C. Gilmer, and P. D. Kirsch, “AC Variability and

Endurance Measurement Technique for Resistive Switching Memories”, IEEE Transactions on

Device and Materials Reliability, vol.14, no.1, pp.300-303, 2014.

DOI:10.1109/TDMR.2013.2291994

[10] X. Guan, S. Yu, and H. P. Wong, “A SPICE Compact Model of Metal Oxide Resistive Switching

Memory with Variations,” IEEE Electron Device Lett., vol. 33, no.10, pp.1405-1407, 2012.

DOI: 10.1109/LED.2012.2210856

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6. Contacts

Please direct all inquiries and comments to: Jinfeng Kang, Professor of Peking University Email: kangjf@pku.edu.cn Xiaoyan Liu, Professor of Peking University Email: xyliu@ime.pku.edu.cn OR (for technical support): Peng Huang, PhD with Peking University Email: phwang@pku.edu.cn Yudi Zhao, PhD with Peking University Email: zhaoyd@pku.edu.cn Weijie Xu, MS student with Peking University Email: xuweijie@pku.edu.cn Please report any bugs to us. Suggestions and comments are also welcome.