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Progress in 3DG. Adviser : PhD Jin-Hua Hong student : Jun-Yi Wu Date : 2008/12/18. outline. 3DG system Test architecture Testing core and wrapper Future work Low Power Test Architecture. . 3DG system Test architecture Testing core and wrapper Future work - PowerPoint PPT Presentation
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1
Progress in 3DG
Adviser : PhD Jin-Hua Hongstudent : Jun-Yi WuDate : 2008/12/18
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outline
3DG system Test architecture
Testing core and wrapper Future work
Low Power Test Architecture
3
3DG system Test architecture
Testing core and wrapper Future work
Low Power Test Architecture
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3DG system
IEEE-1500
DecoderDecoderArbiterArbiter
IPIP
Testing/Normal wrapper Testing/Normal wrapper
AHB
TICTIC
Default Slave
Default SlaveDecoderDecoderArbiterArbiter
IPIP
Testing/Normal wrapper Testing/Normal wrapper
AHB
TICTIC
Default Slave
Default Slave
TIC and IEEE-1500 in 3DG
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TIC architecture in 3DG
Utilize TESTACK to select Normal/Test function. In test mode TESTACK will be HIGH.
TIC
MUX
TESTREQA
TESTREQB
TESTACK
Normal/Test Function
Input
EBITicRead/STicRead
HADDR
HRDATAin
TESTBUS TESTOUT
Normal/Test Function Output
Normal Function
Internal External
32
32
32
32
32
32
AHB
Normal Function
32
HWDATA
Control signals
Control signals
32
32
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IEEE-1500 architecture in 3DG
RM
RM Boundary scan cell
RM Boundary scan cell
RM AHB Wrapper
RM AHB Wrapper
458 bit 458 bit 330 bit 330 bit
IEEE-1500MUX
Cell control Cell control
RM WSI RM WSO
By_pass
GM
GM Boundary scan cell
GM Boundary scan cell
GM AHB Wrapper
GM AHB Wrapper
172 bit 172 bit 382 bit 382 bit
IEEE-1500MUX
WSC
Cell control Cell control
TAP controller
WSI WSOTMSWRCK WRSTN
GM WSI GM WSO
By_pass
Internal
External
Between IP and AHB wrapper put boundary scan cell, and IEEE-1500 to control boundary scan cell.
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External pins in 3DG
TIC: TESTREQA TESTREQB TESTACK IEEE-1500: WSI WSO WRCK TMS WRSTN
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3DG system Test architecture
Testing core and wrapper Future work
Low Power Test Architecture
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Testing Architecture with IEEE-1500 and TIC
Include IEEE-1500 and TIC
AHB BUS
TIC
AMBA Core
IEEE-1500
IEEE-1500 Test data
TIC Test data
wrapper
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Testing Core by IEEE-1500
Utilize IEEE-1500 to testing AMBA core
AHB BUS
TIC
AMBA Core
IEEE-1500
IEEE-1500 Test data
TIC Test data
wrapper
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Testing Core by TIC
Utilize TIC to testing AMBA core
AHB BUS
TIC
AMBA Core
IEEE-1500
IEEE-1500 Test data
TIC Test data
wrapper
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Testing Wrapper by IEEE-1500 and TIC
Utilize TIC and IEEE-1500 to testing wrapper output.
AHB BUS
TIC
AMBA Core
IEEE-1500
IEEE-1500 Test data
TIC Test data
wrapper
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Testing Wrapper by IEEE-1500 and TIC
AHB BUS
TIC
AMBA Core
IEEE-1500
IEEE-1500 Test data
TIC Test data
wrapper
Utilize TIC and IEEE-1500 to testing wrapper input.
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3DG system Test architecture
Testing core and wrapper Future work
Low Power Test Architecture
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Low Power Test Architecture
Arbiter
TIC
ARM 7
Other Master
GM
RM
Other slave
Decoder
Other slave
HADDRHWDATA
HRDATA
HADDRHWDATA
HRDATA
HADDRHWDATA
HRDATA
HWDATA
HRDATA
HADDRHWDATA
HRDATA
HADDRHWDATA
HRDATA
HADDRHWDATA
HRDATA
Address and
Control MUX
Write data
MUX
Read data
MUX
HADDR
Power Management
CLK
POWER
TESTACK
In test mode, TIC will use address and TESTACK to control power management, then power management will cut don’t test IP’s power and clock.
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整合進度 之前 GM 的 SCAN CHAIN 有誤,導致整合時模擬跑到
一半當機,目前重新進行加入 SCAN CHAIN 中
ARM7 裡的 SCAN CHAIN 無法與現有 GM 與 RM 的 SCAN CHAIN 整合,因此將會將 ARM7 從新加入可以與GM 與 RM 整合的 SACN CHAIN