Radiation tolerance of 65 nm technology

Radiation tolerance of 65 nm technology

Sandro BonaciniCERN PH/ESE/[email protected]

mailto:[email protected]

Sandro Bonacini - PH/ESE - [email protected]

2

Outline

Test description Type of devices under test Measurement setup & conditions

Total Ionizing Dose effects results Threshold voltage shift Leakage current Transconductance reduction Aggregated effects on digital structures

Single-Event Upset measurement results SEU, MBU

Present work & future plans

Test structures, measurement setup One chip with digital logic

Assembled with foundry standard cells, pads and IP blocks

Packaged, functional tests & irradiation measurements run on a custom test board

Shift-register 64 kbit

Ring oscillator 1025 inverters

SRAM (from foundry compiler) 56 kbit

Irradiation up to 200 Mrad X-rays while operating

One chip with devices and analog structures Transistor devices

Irradiation & measurement at probe station, no bonding

Analog blocks Preamplifier Discriminator Binary weighted DAC Sub-binary radix DAC

Irradiation up to 200 Mrad X-rays under worst-case static bias

Test devices

Analog structures

SRAM

Shift-register

Ring oscillator

TID effects on CMOS technology

Sandro Bonacini - PH/ESE - [email protected] 4

Bird’s beak

Field oxide

Parasitic MOS

Parasitic channel

Source

Drain1. Effects in the thin gate oxide

2. Effects in the thick lateral isolation oxide (STI) between source and drain of a transistor

Threshold voltage shift

Leakage current

Core NMOS radiation performance


Up to ~20mV shift for 200 Mrad Some rebound effect visible for narrow devices in 130nm: was 150mV

At high doses Vth shift is positive for wide devices, negative for narrow devices STI edge oxide traps considerable charge (RINCE)

Subtreshold slope does not change significantly

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TID [rad]

V

th [V

]

ELT,148060 nm12060 nm24060 nm36060 nm48060 nm60060 nm100060 nm101 m1010 m

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TID [rad]

I leak

[A]

ELT12060nm24060nm36060nm48060nm60060nm100060nm101m1010m

Less than 10× increase in leakage for wide devices (W > 360nm)

Narrow devices have up to 2.5 orders of magnitude increase

Threshold voltage shift Leakage current

Core NMOS, leakage vs spread


I [A

] le

ak

10− 9

10− 10

10− 11

10− 12

device

ELT 120×60 nm 240×60 nm 360×60 nm 480×60 nm 600×60 nm 1000×60 nm 10×1 µm 10×10 µm

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TID [rad]

I leak

[A]


Radiation-induced leakage variation is comparable to transistor parameter spread

Parameter spread 1σ

Core NMOS, leakage current


65nm has better performance with respect to 130nm: (Plots are in the same scale) a rebound effect is visible in 130 nm: all 130nm devices are peaking at ~100nA Narrow devices increase Ileak by 3 orders of magnitude Ileak is ~1nA @136 Mrad

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TID [rad]

I leak

[A]


130 nm

65 nm

108107

TID [rad]106

F.Faccio et al., “Radiation-induced edge effects in deep submicron CMOS transistors”, IEEE Tr. Nucl. Sci. 2005

I/O NMOS radiation performance


Vth shift is positive at high doses Up to ~200mV for 200 Mrad

Vth,0 is ~500mV Interface states seem to dominate over trapped charge Some rebound effect visible for narrow devices

Bigger shift for narrow devices Similar to 130nm

max 170mV @136Mrad

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TID [rad]

V

th [V

]

400280 nm800280 nm2000280 nm101 m1010 mELT, 2400280 nm

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TID [rad]I le

ak [A

]

400280 nm800280 nm2000280 nm101 m1010 m

Increase in leakage by 2 orders of magnitude Most around 1 Mrad, then saturates No rebound within 200 Mrad

Enclosed Layout Transistor (ELT) structure is advised

Threshold voltage shift Leakage current

I/O NMOS, leakage current


Comparison with 130nm: (Plots are in the same scale) devices had Ileak peaking at 1uA @ 2Mrad

had ~5-6 orders of magnitude increase

Similar current 100pA@136Mrad 90 nm technology looks like 130nm (same foundry)

130 nm

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TID [rad]

I leak

[A]

400280 nm800280 nm2000280 nm101 m1010 m

65 nm

Core PMOS, threshold voltage shift


PMOS Vth shift limited to 60 mV trapped charge and

interface states sum up

More evident for narrow devices

Less than 10mV for transistors with W>1um

Compared to other technologies Better performance

than 130 nm had up to 90mV

@136Mrad 30mV for wide

devices In a 90 nm tech we

observed a similar effect: 70mV @ 200Mrad

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TID [rad]

V

th [V

]

12060 nm24060 nm36060 nm48060 nm60060 nm100060 nm101 m1010 mELT,148060 nm

Core PMOS, gm,max

reduction


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TID [rad]

g m,m

ax n

orm

aliz

ed [%

]

ELT12060 nm24060 nm36060 nm48060 nm60060 nm100060 nm101 m1010m

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TID [rad]

I on n

orm

aliz

ed (

%)

ELT, 148060 nm12060 nm24060 nm36060 nm48060 nm60060 nm100060 nm101 m1010 m

Radiation kills maximum gm,max (strong inversion) ...but not gm in weak inversion region

Could influence the speed of digital logic Affects only PMOS

gm,max Max. drive current

I/O PMOS, threshold voltage shift


Considerable shift of the threshold voltage Up to 800 mV

(+160%) for 200 Mrad Vth0 is ~550mV

More pronounced for narrow channel transistors

Devices turn off Design must be

oversized

Worse performance than in 130nm Had max 450mV

shift @136Mrad Similar to 90 nm

Seen 600mV @200 Mrad

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TID [rad]

V

th [V

]

400280 nm800280 nm2000280 nm101 m1010 mELT,1480280 nm

I/O PMOS, gm,max reduction


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TID [rad]

I on n

orm

aliz

ed (

%)

400280 nm800280 nm2000280 nm101 m1010 mELT, 1480280 nm

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TID [rad]

g m,m

ax n

orm

aliz

ed [%

]

400280 nm800280 nm2000280 nm101 m1010 mELT

Similar effect on gm,max in strong inversion as seen for core devices

Maximum drive current is greatly reduced due to V th and gm decrease

Necessary to oversize transistors

gm,max Max. drive current

Digital test structures: SRAM, S-R


Measured static and dynamic currents of SRAM and shift-register Dynamic test run @ 30MHz

SRAM static current increases by 300× Dynamic current reflects this change with a

small increase Ultra-narrow devices are used in the SRAM

from foundry (W=80nm) Peak current at ~2-3 Mrad

Dependent on dose rate (?)

0 0.5 1 1.5 2 2.5

x 108

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Dose [rad]

Cur

rent

[mA

]

SRAM static currentShift-register static currentSRAM dynamic currentShift-register dynamic current

Dose [×100 Mrad]

Shift-register static current changes very little Dynamic current practically constant (decrease!)

~12.5 nW/MHz per D-FF Visible partial annealing effect at room

temperature Time constant ~ 1.5 hours

annealing 25 °C

13.8 hoursannealing25 °C

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Dose [rad]

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rent

[mA

]

SRAM staticShift-register staticSRAM dynamicShift-register dynamic

annealing100 °C, 1 week

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0 50 100 150 200 250Frequency [M

Hz]Cu

rren

t [m

A]

Dose [Mrad]

CurrentFrequency

Digital test structures: ring-oscillator


Ring oscillator Logic slows down with radiation

-13.8% Must keep margin in digital design …or select cells with wider transistors Due to PMOS drive current reduction

Current and speed remain proportional ~ 3 nW/MHz for 1 inverter

Annealing 100 °C, 1 week

SEU test results, tech. comparison


65nm seems to saturate at a cross-section 3.4× smaller than 130nm About proportional to 4× area

reduction 90nm registers were custom-

made (not standard cells) Higher saturation cross-

section though area is ½ of cell in 130 nm

LET thresholds are less than 1.1 MeVcm2/mg for all technologies

Note: SEU-robust cells are well below 10-10 cm2/bit

1E-10

1E-9

1E-8

1E-7

1E-6

0.0 5.0 10.0 15.0 20.0 25.0 30.0 35.0

Cros

s Sec

tion

[cm

2/bi

t]

LET [MeVcm2/mg]

130 nm

90 nm

65 nm

Multiple Bit Upsets (MBUs) in SRAM


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1.1 3.0 6.0 10.2 14.4 20.4 28.9

Cros

s Sec

tion

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-9cm

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t]

LET [MeVcm2/mg]

6BU

5BU

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2BU

1BU

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s Sec

tion

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-9cm

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t]orientation

10BU

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3BU

2BU

1BU

Plots above are @1.2V supply Most MBUs occur in adjacent cells along n-wells (SRAM cell is ~1.0x0.5um)

(...along bit-lines and not along word lines, due to internal SRAM structure) Lower power supply worsens MBU contribution (up to 7-BU @0.9V, 0 deg) Shift-register MBUs are <1% (2-BU and 3-BU were seen)

LET = 20.4 MeVcm2/mg (Ar, 60 deg tilt)

MPW 26 November 2012

Test chip with several ring oscillators made of library inverters of different size … to test the impact of

TID on the speed of logic gates

DICE cell SEU test chip

Demonstrators: Low-power SEU-robust

serializer 4.8 Gb/s CLICpix, imager with

25um pixel sizeSandro Bonacini - PH/ESE - [email protected]


Thank you… 65 nm demonstrates a better radiation hardness than previous generation

technologies No ELT for digital logic

…but wide PMOSes help limiting drive/speed loss I/O devices still need ELT

PMOS might need to be oversized SEU performance is better as sensitive areas are smaller

But beware in using more logic in chips More evident MBUs

Additional information can be found in “Mechanisms of Noise Degradation in Low Power 65 nm CMOS Transistors Exposed to Ionizing Radiation”, V.Re, L.Gaioni, M.Manghisoni, L.Ratti, G.Traversi, IEEE Tr. Nucl. Sci., Vol.57, No.6, Dec. 2010

Future plans Design CMOS I/O standard pad library Select cells in standard cell library from foundry with devices WPMOS > 500nm (TBD) MPW in Nov. 2012

TID std. cell test structures, DICE SEU test, ClicPix, Low-power GBT

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20Sandro Bonacini - PH/ESE - [email protected]

Thank You

SEU test results – heavy ion beam


No substantial differences between static test and dynamic test run at 30 MHz

Evidence of 1 clock root SEU hit SRAM cell is 13× smaller than DFF

Max 1.7× increase in cross-section with reduced power supply voltage @ 0.9V

1.E-10

1.E-09

1.E-08

1.E-07

0 5 10 15 20 25 30 35

Cros

s Sec

tion

[cm

2/bi

t]

LET [MeVcm2/mg]

Shift-register @1.2V, dynamic

Shift-register @1.2V, static

SRAM @1.2V, static

1.E-10

1.E-09

1.E-08

1.E-07

0 5 10 15 20 25 30 35

Cros

s Sec

tion

[cm

2/bi

t]

LET [MeVcm2/mg]

Shift-register @0.9V, staticShift-register @1.2V, staticSRAM @0.9V, staticSRAM @1.2V, static

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PDK, metal stack and libraries

Integrate OA PDK and library to form a M/S kit

One metal stack and one library delivered at first 4 thin + 2 thick

no mimcaps included by default tcbn65lp

Available later (TBD): Second option of metal stack

3 thin + 2 thick Second option for library

tcbn65lpbwp7thvt

STIpoly

M2

M1

M3

M5

M6

M4

M1

W

M2

M3

M4

RDL

M5

M4

M5

poly

M2

M1

M3

M1

W

M2

M3

W

M6

RDLpassivation

M1

W

M1

W

Many tech. options but they all come at a cost Thin metals are expensive because of

their fine pitch

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Rad-hard CMOS I/O pad library Standard I/O pad library from foundry suffers from radiation

effects Use of 2.5V-rated transistors with >5-nm-thick gate oxide NMOS leakage PMOS tend to turn off + loss in transconductance

~50% loss in maximum drive current within 200 Mrad Speed reduction

Radiation hardened I/O pad library Rated for 1.2 V Only core devices, thin gate oxide Better radiation performance To be packaged together with the OA M/S design kit

Motivation

Future vertex detectors for high energy physics experiments can benefit from modern deep submicron technologies Scaling is necessary to improve the performances of pixel detectors

Smaller pixel sizes (pitch) More “intelligence” in each pixel

Faster serializers In general, the expected advantages in porting a front-end circuit to a more

advanced technology include A much more compact, faster digital part (reduction in area of ~60% compared to

130nm technology) Lower noise equivalent charge, due to the reduced capacitances associated with

smaller pixels Better matching than in 130nm

Studies on radiation hardness of the selected technology are needed A set of test chips was designed, fabricated and tested to assess radiation hardness

and functionality of both analog and digital test structuresSandro Bonacini - PH/ESE - [email protected]

Drawbacks of 65 nm Higher cost of tape-out compared to older technologies

Strong push for 1st working silicon Push for more IP re-usage? Must limit technology options usage

Higher gate leakage current

More stringent design rules: ELT transistors are not allowed, more difficult to achieve an optimal layout. OPC rules: avoid jogs, zigzag, shapes like “L”, “U” or ring, …

Deep submicron technologies are not optimized for analog designs Smaller dynamic range due to the lower power supply (1.2 V) reduces the possibilities to use some structures

(such as cascoded stages). Multiple stages, with possible stability issues, are needed to achieve a high gain. This problem is moreover aggravated by the lower output resistance of the MOSFETs which lowers the gain of the single stages.

65nm technology 130nm technology

Minimum gate length 60nm 120nm

Metal layers 10 8

Power supply 1.2 V - 1.0 V 1.5 V - 1.2 V

Gate leakage 350 pA/μm2 20 pA/μm2

Channel leakage (at minimum length) 211 pA/μm 400 pA/μm

Typical transistor leakage (minL,3minW) 84 pA 290 pA


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Radiation tolerance of 65 nm technology