RE-configure FPGA through JTAG◦ Heidelberg option, needs

reprogramming of Altera devices (not in this talk) Needed for re-programming after loss of

conf. due to radiation

◦ Nikhef option, re-programming would be a big advantage Re-configuration needed for debugging,

bug fixes, and upgrades. Only during technical stops. (no time limitations)

432 FE-Boxes with each 4 Actel proasic3e’s Flash based FPGA’s◦ Difficult to physically reach the

devices

Programming FPGA through the GBT-SCA

Antonio Pellegrino, Tom Sluijk, Wilco Vink 111 April 2013

◦ 432 Front end boxes with each

◦ One GBT master board◦ Connected with 5

SCA’s◦ One on Master GBT

board◦ Four, one on each TDC

board

◦ Four Actel TDC boards◦ Actel Proasic3E

A3PE100FG484 flash based FPGA

Programmable via JTAG 1 SCA

Actel re-programming via JTAG

Front end Box

Antonio Pellegrino, Tom Sluijk, Wilco Vink 211 April 2013

Software:◦ Flashpro(gui)

Programs several formats, pdb, stapl, ….

Hardware:◦ Actel FlashPro3

USB -> JTAG

Programming FPGA on testbench

Antonio Pellegrino, Tom Sluijk, Wilco Vink 311 April 2013

Program bitfile generated by Actel Designer Bitfile to JTAG “translation”

◦ By Control PC or CCPC CCPC -> PCIe -> memory

◦ JTAG algorithm over PCIe/memory mapped interface◦ C-code ??

E-link protocol driver to GBT <-> GBT <-> SCA◦ VHDL on Stratix AMC40, code available??◦ Writes to SCA buffer

JTAG connected to Actel Proasic3E (A3PE1500)◦ Single device chain

Programming FPGA on detector

Antonio Pellegrino, Tom Sluijk, Wilco Vink 4

SOL40 OT Front end box

11 April 2013

Available software by FPGA suppliers◦ Actel Stapl player, C-code available

http://www.actel.com/download/program_debug/stapl/stapl11.aspx#sup

CCPC compatible?

◦ Actel Bitfile -> JTAG register/pins (bitbangs JTAG pins/register) C-code written for for microprocessor(s), Uses Actel DAT format http://www.actel.com/download/program_debug/directc/dc27.aspx CCPC compatible? (Maybe in embedded Processor FPGA??)

◦ Altera JAM stapl player (currently used in CCPC’s LHCb for Xilinx and Altera) Actel generated stapl files aren’t compatible (both mention JESD71

standard)

Translation (visa versa) to◦ PCIe memory map◦ E-link to SCA JTAG buffer◦ Something available ???

CCPC software

Antonio Pellegrino, Tom Sluijk, Wilco Vink 511 April 2013

https://indico.cern.ch/getFile.py/access?contribId=7&sessionId=3&resId=1&materialId=slides&confId=242284

TCK programmable◦ 100kHz – 1MHz

TMS and TDO/TDI◦ Buffer size 4*32bits

Control loop (CCPC):

◦ Write TDO, TMS regs.◦ Write Go Command◦ SCA sends interrupt◦ Read TDI regs.

Slow Control Adapter -> JTAG

Antonio Pellegrino, Tom Sluijk, Wilco Vink 6

FPGA

TMS

TDO

TDI

TCK

SCA

11 April 2013

JTAG “player” software◦ No fixed timing relation between multiple bursts of SCA

buffer size in JTAG cycles◦ 128 bits + GBT latency, from TDO device to TDO(in)

software on CCPC Stapl files reads ID codes before programming, -> input needed Otherwise customize Stapl files

Actel timing requirements unknown◦ Does the device require constant bursts / TCK, min/max

frequency ???◦ Asked Actel, waiting for answers…◦ ProAsic3 Not capable of partial re-programming (Actel

information) SCA limitations

◦ JTAG Buffer size 128 bit◦ Latency in read back from TDO

Requirements and limitations

Antonio Pellegrino, Tom Sluijk, Wilco Vink 711 April 2013