Resistive switching concept - a new design paradigm

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Resistive switching concept - a new design paradigm

J.M. Portal, M. Bocquet, H. Aziza, D. Deleruyelle, M. Moreau and C. Muller

Im2np, CNRS & Aix-Marseille University, France

Workshop Memories 2012 MINATEC, Grenoble - France

1.  Memory Taxonomy

2.  Challenges and Opportunities

3.  Embedded Memory Arrays

4.  Distributed Memory in Logic

5.  Concluding Remarks

Outline

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Outline

3

Memory Taxonomy

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E2PROM Flash

Nano-Si, SONOS

PCM, CBRAM MRAM ReRAM

Charge storage Resistance switching

Memories

SRAM DRAM

Non volatile Volatile

DRAM (Micron)

Flash (Intel) (MRAM) Freescale

RHRS : High resistance

state

RLRS : Low resistance

state

Very High pristine R FORMING (once)

SET

RESET

Bipolar switching Opposite polarity for RESET/

SET,FORMING

Unipolar switching Same polarity for all

operations 5

ReRAM Behavior

•  Resistive Switching devices can be classified according to: ü  Type of RS material (i.e. inorganic, organic, molecular…) ü  Nature of the RS phenomenon (i.e. thermochemical, redox or electronic) ü  Voltage polarity (i.e. unipolar/bipolar)

Source: ITRS – ERD/ERM Technology Work Groups Report on Emerging Research Memory Technologies (2010)

MetalIL

active materials: TiOx, Ta2O5, HfO2

Metal

TE

BE

Memory cell

BEOL compatible Low voltage

For design purpose, ReRAM compact model

(Eldo, Virtuoso)

ReRAM Classification






Outline

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Mobile Application Challenges

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0.010.110.001

0.01

0.1

1

10

100

1000

Gate Length (microns)

Active Power

Passive Power

1994 2005

1 0.1 0,01 Gate length (!m)

1000

100

10

1

0.1

0.01

0.001 P

ow

er

De

nsi

ty (

W/c

m2

) Source: K. Nowka, IBM

Time

Periodic Wakeup

Idle/Stand-by

Wakeup & Operation

•  Mobile applications activity regarding time = 10% ON / 90% OFF

•  Passive power (OFF) is increasing with technology nodes

•  Low-Power techniques §  Technological solutions: high k, FDSOI,

MTVT MOS etc… but variability is increasing, limiting improvement

§  Design solutions: Power island, Power gating with retention flop, stand-by/sleep/freeze mode

Sleep/Freeze mode

Logic NV

M

Logic

NVM

Logic NVM cells /circuits

•  Interconnected chips §  Separate optimized technologies §  Tradeoffs: cost, communication speed, power

•  Embedded implementation §  Logic and NVM on a monolithic substrate §  Tradeoffs: process compatibility, array

efficiency, communication speed, power

•  Distributed implementation §  Single chip with distributed NVM cells &

circuits

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CPU state Cache NVM

Key Requirements for Distributed NVM

•  Readiness for leading edge technology node • Cost and scalability

§  BEOL compatible §  3D stackable §  Good Scalability in x and y with lithography

•  Performances §  Low voltage (CMOS compatible)/ Low current §  Fast writing/reading times §  Reduced variability

•  Reliability §  Non-volatility with long retention (> 10 years) §  High endurance

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SRAM cache

LV Logic

CPU

Analog FE

NOR NVM

NAND NVM

HV Logic

Evolution driven by low power mobile applications

Today Tomorrow? New Paradigms

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LV Logic

CPU

Analog FE

NVSRAM cache

eFPGA

Embedded Resistive Switching Memory


LV Logic

CPU

Analog FE

NVSRAM cache

eFPGA


Embedded Resistive Switching Memory 1.  Memory Taxonomy





Outline

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•  Data discrimination requires distinct resistance states with RLow & RHIGH as large as possible (↓ power consumption) 1 §  Limited process variations 2 (→ narrow resistance distributions)

§  Sensing solutions improvement …

Memory Window Requirements

Bit resistance

Bit n

umb

er

ΔR = RHigh – RLow

RHigh

"0"

proper discrimination

σσ RRef

"1"

RLow

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1 Muller et al., "Design Technology for Heterogeneous Embedded Systems", Springer, 2011 2 Lee et al., IEEE Proc. of International Electron Devices Meeting, pp. 1-4, 2008 2 Aziza et al., IEEE Proc. of Non-Volatile Memory Technology Symposium, 2011

Memory Architecture

1T-1R : Core-cell relies on the association of a select/access device with a ReRAM.

US Patent no. 6,791,859 B2, 2004 US Patents no. 6,849,891 – 2009/0184305 – 2009/0026434

Generic resistive switching memory circuit

Cross-point: Core-cell relies on single ReRAM between WL/BL.

Trade-off between array density and sneak path issue

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Cross-Point Array

WL0

WL1

WL2

WL3

BL0 BL1 BL2 BL3 BL0 BL1 BL2 BL3

Selected word VDD/2 (V) Sub-circuit

0 (V) Sub-circuit

VDD/2 (V) Sub-circuit

Cell (2R) level: •  2R with complementary

states •  Set both ReRAM (RLRS

state) •  Reset selectively one

ReRAM (RHRS state)

Array level: •  VDD, gnd are applied on

selected word •  VDD/2 is applied on

unselected word to prevent unselected cell changes

W.S. Zhao et al., IEEE Proc. Nanoarch, 2012, to appear 15

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WL

BL BL

2 steps read operation: •  Pre-charge - (PCH=‘0’), BL

and WL are biased to VDD through the S.A

•  Read – (PCH=‘1’ & WL=‘0’) BL are grounded through ReRAM to obtain logic value on output Q

PCSA: •  No static consumption •  Differential read of the 2R

devices in the cell •  All the cells in a word are

read in parallel

Cross-Point Array

BL

BL

WL

En_Read

PCH PCH

RHRS

RLRS

Q Q

MPC0 MPC1 MPA0

MPA1

MNA0 MNA1

MNE0 MNE1

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LV Logic

CPU

Analog FE

NVSRAM cache

eFPGA


Embedded Resistive Switching Memory 1.  Memory Taxonomy





Outline

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Non Volatile SRAM CMOS SRAM with BEOL resistive switching memory

•  Need extra transistor to access Resistive element for write & read operation.

•  Complementary state in both ReRAM to store data before power down.

Pi-Feng Chiu et al., IEEE Symposium on VLSI Circuits, 2010, p. 229-230

Hraziia et al., EUROSOI Conference 2012

Simulated with 22 nm FDSOI & ReRAM

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Non Volatile Flip-Flop

Y. Matsuya, et al., IEEE JSSC, vol. 32, 1997 S. Onkaraiah , et al., IEEE NEWCAS 2012, to appear

CMOS Flip-Flop with BEOL resistive switching memory •  Today solution based on retention Flip-Flop (passive power,

volatile, area cost 8T)

•  Flip-Flop with ReRAM (No passive power when power down, non-volatile, reduced area cost 6T-2R)

•  Challenges: reduction of set/reset current, endurance

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Simulated with 22 nm FDSOI & ReRAM

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Outline

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Concluding Remarks

•  ReRAM evolution opens the way to new design approach because: §  Programming voltages are compatible with CMOS biasing §  Memory point are inserted in BEOL on top of CMOS

•  “Distributed memory” or “memory in logic” concept is really appealing §  Distributed embedded cross-point arrays §  Non-Volatile SRAM and Non-Volatile Flip-Flop

•  Mobile applications could benefit from this architectural evolution §  Static power reduction §  freeze mode: Save & restore power budget reduction

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Thank You for Your Attention

Institut Matériaux Microélectronique Nanosciences de Provence

UMR 7334 CNRS, Universités Aix-Marseille et Sud Toulon-Var

[email protected]

"Vieux port" of Marseille

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Acknowledgements

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Resistive switching concept - a new design paradigm