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IS2008/10/13/15 SoC
Bluetooth® 4.1 Mono Audio SOC
Features
System Specification Compliant with Bluetooth Specification v.4.1
(EDR) in 2.4 GHz ISM band It supports following profiles :
- HFP 1.6 - HSP 1.1 - A2DP 1.2 - AVRCP 1.5 - SPP 1.0 - PBAP 1.0
Baseband Hardware
16MHz main clock input
Built-in internal ROM for program memory
Support to connect to two hosts ( phones, tablets…) with HFP or A2DP profiles simultaneously
Adaptive Frequency Hopping (AFH) avoids occupied RF channels
Fast Connection supported
RF Hardware
Fully Bluetooth 4.1 (EDR) system in 2.4 GHz ISM band.
Combined TX/RX RF terminal simplifies external matching and reduces external antenna switches.
Max. +4dBm output power with 20 dB level control from register control.
Built-in T/R switch for Class 2/3 application
To avoid temperature variation, temperature sensor with temperature calibration is utilized into bias current and gain control.
Fully integrated synthesizer has been created. There requires no external VCO, varactor diode, resonator and loop filter.
Crystal oscillation with built-in digital trimming for temperature/process variations.
Audio processor
Support 64 kb/s A-Law or -Law PCM format, or CVSD (Continuous Variable Slope Delta Modulation) for SCO channel
operation.
Noise suppression
Echo suppression
SBC and optional AAC decoding
Packet loss concealment
Build-in four languages (Chinese/ English/ Spanish/ French) voice prompts and 20 events for each one.
(This function can be set up in “IS20XXS_UI” tool.)
Support SCMS-T
Audio Codec
20 bit DAC and 16 bit ADC codec
98dB SNR DAC playback
Built-in 1 channel 2.3W class-D amplifier for a 4Ω speaker (for IS2013/15S only)
Peripherals
Built-in Lithium-ion battery charger (up to 350mA)
Integrate 3V, 1.8V configurable switching regulator and LDO
Built-in ADC for battery monitor and voltage sense.
A line-in port for external audio input
Two LED drivers
Flexible HCI interface High speed HCI-UART (Universal
Asynchronous Receiver Transmitter) interface (up to 921600bps)
Package
6x6mm2 48QFN package
(IS2008S, IS2010S)
7x7mm2 56QFN package (IS2013S, IS2015S)
Description
Mono Audio Chip is a compact, highly integrated,
CMOS single-chip RF and baseband IC for
Bluetooth v4.1 with Enhanced Data Rate 2.4GHz
applications. This chip is fully compliant with
Bluetooth specification and completely
Mono Audio SoC
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backward-compatible with Bluetooth 3.0, 2.0 or
1.2 systems.
It incorporates Bluetooth 1M/2M/3Mbps RF,
single-cycle 8bit MCU, TX/RX modem, 5-port
memory controller, task/hopping controller,
UART interface, and MICROCHIP’s own
Bluetooth software stack to achieve the
required BT v4.1 with EDR functions.
To provide the superior audio and voice
quality, it also integrates a DSP co-processor, a
PLL, and a CODEC dedicated for voice and
audio applications.
For voice, not only basic CVSD encoding and
decoding but also enhanced noise reduction
and echo cancellation are implemented by the
built-in DSP to achieve better quality in both
sending and receiving sides. For the enhanced
audio applications, SBC/AAC_LC decoding
functions can be also carried out by DSP to
satisfy Bluetooth A2DP requirements.
In addition, to minimize the external
components required for portable devices, a
battery voltage sensor, battery charger, a
switching regulator and LDO are integrated to
reduce system BOM cost for various Bluetooth
applications.
As the market of portable/wireless speakers
demand is increasing, a 1 channels 2.3W
class-D amplifier which provides up to 100dB
SNR is also built-in to reduce BOM cost and
PCB area.
Applications
Mono headsets with A2DP
Mono speakerphones
Mono Audio SoC
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Table of Contents
1.0 DEVICE OVERVIEW ....................................................................................................................................4 2.0 KEY FEATURES TABLE ..............................................................................................................................5 3.0 PIN DESCRIPTION AND POWER SUPPLY ................................................................................................6 4.0 TRANSCEIVER ...........................................................................................................................................13 5.0 MICROPROCESSOR .................................................................................................................................14 6.0 AUDIO .........................................................................................................................................................15 7.0 POWER MANAGEMENT UNIT ..................................................................................................................17 8.0 GENERAL PURPOSE IOs ..........................................................................................................................19 9.0 OPERATION WITH EXTERNAL MCU .......................................................................................................20 10.0 ANTENNA PLACEMENT RULE ...............................................................................................................25 11.0 SPECIFICATIONS ....................................................................................................................................26 12.0 REFERENCE CIRCUIT ............................................................................................................................33 13.0 PACKAGE INFORMATION.......................................................................................................................34 14.0 REFLOW PROFILE AND STORAGE CINDITION ...................................................................................39
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Abbreviations List: HFP: Hands-free Profile AVRCP: Audio Video Remote Control Profile A2DP: Advanced Audio Distribution Profile PBAP: Phone Book Access Profile HSP: Headset Profile SPP: Serial Port Profile NFC: Near Field Communication CDA: Class D Amplifier SCMS-T: Serial Copy Management System
Mono Audio SoC
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1.0 DEVICE OVERVIEW
The mono audio chip series include IS2008S, IS2010S, IS2013S and IS2015S chip. The chip integrates
Bluetooth 4.1 radio transceiver, PMU, DSP and 1-channel CDA (Class D Amplifier). Figure 1-1 shows the
application block diagram.
FIGURE 1-1: APPLICATION BLOCK DIAGRAM
FIGURE 1-2: INTERFACE BETWEEN MCU AND IS20XX CHIP
IS20XXS
HCI_TXD
HCI_RXD
PWR
P0_0
MCUUART_TX
UART_RX
MCU_WAKEUP
BT_WAKEUP
8051
16KB patch RAM
448KB ROM
44KB RAM
24-bit DSP Core
MCU
158KB ROM
88KB RAM
DSP
IS20XX
Classic RF
MACMODEM
BTv4.1+EDRTransceiver
RF Controller
Antenna
16 M Hz Crystal
EEPROM
Power Switch
LED
BAT Charger
1.8V BUCK
3.0V LDO*2
LED Driver *2
PMULi-Ion BAT
2-Channel DAC
Digital Core
2-Channel ADC
Audio Codec
(For IS2008/2010 only)
Speaker2W
Stereo Class-D AMP
MIC1
MIC2
Speaker
AUX_IN(analog signal) I2C
(GPIOs or H/W)IO Port 0~3
Mono Audio SoC
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2.0 KEY FEATURES TABLE
Feature Chip IS2008S IS2010S IS2013S IS2015S
Application Headset Headset Speaker Speaker
Stereo/Mono Mono Mono Mono Mono
Pin count 48 48 56 56
Dimension (mm2) 6x6 6x6 7x7 7x7
Audio DAC output 1-ch 1-ch 1-ch 1-ch
DAC (single-end) [email protected] (dB) -98 -98 -98 -98
DAC (cap-less) [email protected] (dB) -96 -96 -96 -96
ADC SNR @2.8V (dB) -90 -90 -90 -90
I2S digital interface X X X X
Analog Aux- in X X
Mono MIC 2 2 1 1
Support external audio AMP X X
Build-in Class-D amplifier X X
1-ch
1-ch
UART
LED Driver 2 2 2 2
Internal DC-DC step-down regulator
DC 5V Adaptor Input
Battery Charger (350mA max)
GPIO for Application 6 6 9 9
Button support 6 6 6 6
Support NFC application
Voice prompt
Multi-tone
DSP sound effect X X
Profile
HFP 1.6 1.6 1.6 1.6
AVRCP 1.5 1.5 1.5 1.5
A2DP 1.2 1.2 1.2 1.2
PBAP 1.0 1.0 1.0 1.0
HSP 1.1 1.1 1.1 1.1
SPP X 1.0 X 1.0
Note: “” means support the feature “X” means no support the feature.
Mono Audio SoC
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3.0 PIN DESCRIPTION AND POWER SUPPLY
3.1 PIN ASSIGNMENT
TABLE 3-1: IS2008S/IS2010S PIN DESCRIPTION
Pin No. Pin type Name Description
1 P VCOM Internal biasing voltage for CODEC
2 I MICN2 Mic 2 mono differential analog negative input
3 I MICP2 Mic 2 mono differential analog positive input
4 I MICN1 Mic 1 mono differential analog negative input
5 I MICP1 Mic 1 mono differential analog positive input
6 P MICBIAS Electric microphone biasing voltage
7 P VDD_CORE Core 1.2V power input; Connect to CLDO_O pin
8 O P1_2 IO pin, default pull-high input EEPROM clock SCL
9 I/O P1_3 IO pin, default pull-high input EEPROM data SDA
10 I RST_N System Reset Pin, active when rising edge.
11 P VDD_IO I/O power supply input (2.7~3.3V); Connect to LDO31_VO pin
12 I/O P0_1 IO pin, default pull-high input (Note 1) 1. FWD key when class 2 RF (default), active low. 2. Class1 TX Control signal of external RF T/R switch, active high.
13 I/O P1_5
IO pin, default pull-high input (Note 1) 1. NFC detection pin, active low. 2. Out_Ind_0 3. Slide Switch Detector, active low. 4. Buzzer Signal Output
Mono Audio SoC
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Pin No. Pin type Name Description
14 I HCI_RXD HCI-UART RX data
15 O HCI_TXD HCI-UART TX data
16 P CODEC_VO 3.1V LDO output for CODEC power
17 P LDO31_VIN 3.1V LDO input; Connect to SYS_PWR pin
18 P LDO31_VO 3.1V LDO output
19 P ADAP_IN 5V power adaptor input
20 P BAT_IN 3.3~4.2V Li-ion battery input
21 - NC No Connection
22 P SAR_VDD SAR 1.8V input; Connect to BK_O pin
23 P SYS_PWR Power Output which come from BAT_IN or ADAP_IN
24 P BK_VDD 1.8V buck VDD Power Input; Connect to SYS_PWR pin
25 P BK_LX 1.8V buck pin for switch
26 P BK_O 1.8V buck feedback input
27 I PWR Multi-Function Push Button and power on key
28 I LED2 LED Driver 2
29 I LED1 LED Driver 1
30 I/O P0_3
IO pin, default pull-high input (Note 1) 1. REV key (default), active low. 2. Buzzer Signal Output 3. Out_Ind_1 4. Class1 RX Control signal of external RF T/R switch, active high.
31 P CLDO_O 1.2V core LDO output
32 P PMIC_IN PMU blocks power input; Connect to BK_O pin
33 P RFLDO_O 1.28V RF LDO output
34 P VBG Bandgap output reference for decoupling interference
35 P ULPC_VSUS ULPC 1.2V output power
36 I XO_N 16MHz Crystal input negative
37 I XO_P 16MHz Crystal input positive
38 P VCC_RF RF power input (1.28V) for both synthesizer and TX/RX block; Connect to RFLDO_O pin
39 I/O RTX RF RTX path
40 I P0_2 IO pin, default pull-high input (Note 1) Play/Pause key (default), active low.
41 I P2_0 IO pin, default pull-high input System Configuration, H: Application L: Baseband(IBDK Mode)
42 I P2_7 IO pin, default pull-high input (Note 1) Volume up key (default), active low.
43 I P0_5 IO pin, default pull-high input (Note 1) Volume down (default), active low.
44 P VDD_IO I/O power supply input (2.7~3.3V); Connect to LDO31_VO pin
Mono Audio SoC
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Pin No. Pin type Name Description
45 P VDDAO Positive power supply dedicated to CODEC output amplifiers; Connect to CODEC_VO pin
46 O AOHPM Headphone common mode output/sense input.
47 O AOHPL L-channel analog headphone output
48 P VDDA Positive power supply/reference voltage for CODEC; Connect to CODEC_VO pin
49 P EP Exposed pad as ground
* I: signal input pin * O: signal output pin * I/O: signal input/output pin * P: power pin
Note 1: These button or functions can be setup by “IS20XXS_UI” tool.
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TABLE 3-2: IS2013S/IS2015S PIN DESCRIPTION
Pin No. Pin type Name Description
1 P VDDAO Positive power supply dedicated to CODEC output amplifiers; Connect to CODEC_VO pin
2 O AOHPM Headphone common mode output/sense input.
3 O AOHPL L-channel analog headphone output
4 P VDDA Positive power supply/reference voltage for CODEC; Connect to CODEC_VO pin
5 P VCOM Internal biasing voltage for CODEC
6 I MICN1 Mic 1 mono differential analog negative input
7 I MICP1 Mic 1 mono differential analog positive input
8 P MIC_BIAS Electric microphone biasing voltage
9 I AIL L-channel single-ended analog inputs
10 P VDD_CORE Core 1.2V power input; Connect to CLDO_O pin
11 O P1_2 IO pin, default pull-high input EEPROM clock SCL
12 I/O P1_3 IO pin, default pull-high input EEPROM data SDA
13 I RST_N System Reset Pin, active when rising edge.
14 P VDD_IO I/O power supply input (2.7~3.3V); Connect to LDO31_VO pin
15 I/O P0_1 IO pin, default pull-high input (Note 1) 1. FWD key when class 2 RF (default), active low. 2. Class1 TX Control signal of external RF T/R switch, active high.
Mono Audio SoC
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Pin No. Pin type Name Description
16 I P2_4 IO pin, default pull-high input System Configuration, L: Boot Mode with P2_0 low combination
17 I/O P0_4 IO pin, default pull-high input. (Note 1) 1. NFC detection pin, active low. 2. Out_Ind_0
18 I/O P1_5
IO pin, default pull-high input (Note 1) 1. NFC detection pin, active low. 2. Out_Ind_0 3. Slide Switch Detector, active low. 4. Buzzer Signal Output
19 I HCI_RXD HCI-UART RX data
20 O HCI_TXD HCI-UART TX data
21 P CODEC_VO 3.1V LDO output for CODEC power
22 P LDO31_VIN 3.1V LDO input; Connect to SYS_PWR pin
23 P LDO31_VO 3.1V LDO output
24 P ADAP_IN 5V power adaptor input
25 P BAT_IN 3.3~4.2V Li-Ion battery input
26 P SAR_VDD SAR 1.8V input; Connect to BK_O pin
27 P SYS_PWR Power Output which come from BAT_IN or ADAP_IN
28 P LDO18_VDD 1.8V LDO VDD Power Input; Connect to SYS_PWR pin
29 P LDO18_O 1.8V LDO output
30 I PWR Multi-Function Push Button and power on key
31 - NC No Connection
32 I LED2 LED Driver 2
33 I LED1 LED Driver 1
34 I/O P0_0 IO pin, default pull-high input (Note 1) 1. Slide Switch Detector, active low. 2. UART TX_IND, active low.
35 I/O P0_3
IO pin, default pull-high input (Note 1) 1. REV key (default), active low. 2. Buzzer Signal Output 3. Out_Ind_1 4. Class1 RX Control signal of external RF T/R switch, active high.
36 I EAN Embedded ROM/External Flash enable H: Embedded; L: External Flash
37 P CLDO_O 1.2V core LDO output
38 P PMIC_IN PMU blocks power input; Connect to BK_O pin
39 P RFLDO_O 1.28V RF LDO output
40 P VBG Bandgap output reference for decoupling interference
41 P ULPC_VSUS ULPC 1.2V output power
42 I XO_N 16MHz Crystal input negative
43 I XO_P 16MHz Crystal input positive
Mono Audio SoC
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Pin No. Pin type Name Description
44 P VCC_RF RF power input (1.28V) for both synthesizer and TX/RX block; Connect to RFLDO_O pin
45 I/O RTX RF RTX path
46 I P0_2 IO pin, default pull-high input (Note 1) Play/Pause key (default), active low.
47 I P2_0 IO pin, default pull-high input System Configuration, H: Application L: Baseband(IBDK Mode)
48 I P2_7 IO pin, default pull-high input (Note 1) Volume up key (default), active low.
49 I P3_0 IO pin, default pull-high input (Note 1) Line-in Detector (default), active low.
50 I P0_5 IO pin, default pull-high input (Note 1) Volume down (default), active low.
51 P VDD_IO I/O power supply input (2.7~3.3V); Connect to LDO31_VO pin
52 P AVDD_CDA Supply voltage of audio amplifier.
53 P VBP_CDA Reference voltage output.
54 O HPON_CDA Negative BTL output of channel-1
55 O HPOP_CDA Positive BTL output of channel-1
56 P PVDD_CDA Supply voltage of power stage ch-1
57 P EP Exposed pad as ground
* I: signal input pin * O: signal output pin * I/O: signal input/output pin * P: power pin
Note 1: These button or functions can be setup by “IS20XXS_UI” tool.
Mono Audio SoC
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3.2 POWER SUPPLY
The device is powered via BAT pin input. If a battery is not connected, an external power supply needs to
provide to this input. Figure 3-1 shows the PCB connections from BAT pin to other voltage supply pins of the chip.
FIGURE 3-1: POWER TREE DIAGRAM
(Use PCB trace link these pins)
VDDA /VDDAO
VDD_IO
3V LDO
1.8V Buck
SAR_VDD
LDO31_VIN
CODEC_VO
LDO31_VO
BK_VDD
BK_LX
BK_O
VDD_CORE
VCC_RF
1.2V LDOPMIC_IN
CLDO_O
RFLDO_O
PVDD_CDA
Li-
Ion
BA
T
BAT_IN
ADAP_IN
SYS_PWRPower Switch
5V Adapter
(4.2~3.0V)
(4.5~5.5V)
(4.2~3.0V)
(3.0~2.7V)
(3.3~2.7V)
(1.8V)
(1.2V)
(1.28V)
Mono Audio SoC
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4.0 TRANSCEIVER
The mono audio chip is designed and optimized for Bluetooth 2.4 GHz system. It contains a complete radio frequency transmitter/receiver section. An internal synthesizer generates a stable clock for synchronize with another device.
4.1 TRANSMITTER
The internal PA has a maximum output power of +4dBm with 20dB power level control. This is applied into Class2/3 radios without external RF PA.
The transmitter directly performs IQ conversion to minimize the frequency drift, and it can excess 20dB power range with temperature compensation mechanism.
4.2 RECEVIER
The LNA operates with TR-combined mode for single port application. It can save a pin on package and without an external TX/RX switch.
The ADC is utilized to sample the input analog wave and convert into digital signal for de-modulator analysis. A channel filter has been integrated into receiver channel before the ADC, which to reduce the external component count and increase the anti-interference capability.
The image rejection filter is used to reject image frequency for low-IF architecture. This filter for low-IF architecture is intent to reduce external BPF component for super heterodyne architecture.
RSSI signal is feedback to the processor to control the RF output power to make a good tradeoff for effective distance and current consumption.
4.3 SYNTHESIZER
A synthesizer generates a clock for radio transceiver operation. There is a VCO inside with tunable internal LC tank. It can reduce variation for components. A crystal oscillation with internal digital trimming circuit provides a stable clock for synthesizer.
4.4 MODEM
For Bluetooth v1.2 specification and below, 1 Mbps was the standard data rate based on Gaussian Frequency Shift Keying (GFSK) modulation scheme. This basic rate modem meets BDR requirements of Bluetooth v2.0 with EDR specification.
For Bluetooth v2.0 with EDR specification, Enhanced Data Rate (EDR) has been introduced to provide 2 and 3 Mbps data rates as well as 1 Mbps. This enhanced data rate modem meets EDR requirements of Bluetooth v2.0 with EDR specification. For the viewpoint of baseband, both BDR and EDR utilize the same 1MHz symbol rate and 1.6 KHz slot rate. For BDR, 1 symbol represents 1 bit. However each symbol in the payload part of EDR packets represents 2 or 3 bits. This is achieved by using two different modulations, π/4 DQPSK and 8DPSK.
4.5 AFH (Adaptive Frequency Hopping)
Stereo audio chip have AFH function to avoid RF interference. It has an algorithm to check the interference nearby and choice clear channel to transceiver Bluetooth signal.
Mono Audio SoC
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5.0 MICROPROCESSOR
A single-cycle 8-bit MCU is built into the mono audio chip to execute the Bluetooth protocols. It operates from 16MHz to higher frequency where the firmware can dynamically adjust the tradeoff between the computing power and the power consumption. The MCU firmware is hard-wired in ROM to minimize the firmware execution power consumption and to save the external flash cost.
5.1 MEMORY
A synchronous single port RAM interface is used. There are sufficient ROM and RAM to fulfill the requirement of processor. A register bank, a dedicated single port memory and a flash memory are connected to the processor bus. The processor coordinates all the link control procedures and data movement using a set of pointers registers.
5.2 EXTERNAL RESET
The chip provides a watchdog timer to reset the chip. It has an integrated Power-On Reset (POR) circuit that resets all circuits to a known power-on state. This action can also be driven by an external reset signal that can be used to externally control the device, forcing it into a power-on reset state. The RST signal input is active low and no connection is required in most applications.
5.3 REFERENCE CLOCK
Mono audio chip is composed of an integrated crystal oscillation function. It uses a 16 MHz external crystal and two specified loading capacitors to provide a high quality system reference timer source. This feature is typically used to remove the initial tolerance frequency errors associated with the crystal and its equivalent loading capacitance in mass production. Frequency trim is achieved by adjusting the crystal loading capacitance through the on-chip trim capacitors Ctrim..
The value of trimming capacitance is around 200fF (200x10-15 F) per LSB at 5 bits word, therefore the overall adjustable clock frequency is around 40 KHz.
FIGURE 5-1: CRYSTAL CONNECTION
IS20XXS
XO_N XO_P
CL1 CL2
trimC =200fF * (1~31) ; Cint 3pF
CL=[(CL1*CL2)/(CL1+CL2)]+(Ctrim/2)+Cint
(e.g. Set trim value as 16, then C trim= 3.2pF.
For a 16M Hz crystal which CL=9pF, we can get CL1 = CL2 =9.1pF in this case.)
For CL selection, please refer to the datasheet of crystal vendor
Mono Audio SoC
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6.0 AUDIO
There are a few stages for input audio and output audio. Each stage can be programmed to vary the gain response characteristics. For microphone input, both single-end input and differential input are supported. One of the important points in maintaining a high quality signal is to provide a stable bias voltage source to the condenser microphone’s FET. DC blocking capacitors may be used at both positive and negative sides of input. Internally, this analog signal is converted to 16-bit 8 kHz linear PCM data.
6.1 DIGITAL SIGNAL PROCESSOR
A digital signal processor (DSP) cooperates with MCU to perform digital audio processing with some advanced features such as noise cancellation, audio output level suppression and etc. It provides audio processing with some advanced features. The DSP cancels the acoustic echo that may present in headset or speaker. All the audio processing is performed by the DSP with low power consumption. This technique effectively cancels the incoming echo signal without impact to the desired voice signal. An outgoing signal to the speaker which level exceeds the threshold (and therefore deemed likely to create echo) will be result in suppression of the signal along the input path from the microphone. Filtering is also applied to provide a smoother transition for more natural user experience.
FIGURE 6-1: BLOCK DIAGRAM OF DSP
Far- End
NRIIR/EQ DAC
Audio
Amp
ADCHPFAECNear-End NR/AES
HPF
Digital Mic Gain
Additive Background Noise
IIR/EQ
CVSD/A-Law/u-Law Decoders
CVSD/A-Law/u-Law Encoders
DSP
BT Chip
BT RF/Base-
band Processor
Speaker
MIC
Antenna
(a)
IIR/EQ DACAudio
AmpSBC/AAC Decoders
DSP
BT Chip
8051 Processor/
BT RF/Base-
band Processor
Audio
Effect
Speaker
Antenna
(b)
Processing flow of speakerphone applications for (a) speech and (b) audio signal processing.
There is a “DSPTool_IS20XX” can support user to set up these DSP parameter. For more detail information, please reference “BT5502_DSP_APP” document.
Mono Audio SoC
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6.2 CLASS-D AUDIO AMPLIFIER
The class D amplifier has significant advantage in many applications because of its lower power dissipation which produces less heat. IS2013S and IS2015S chip has built-in a class D amplifier that reduces circuit board space and system cost. The efficiency of the amplifier extends the battery life in portable systems.
The class D amplifier is implemented by using a full-bridge output stage. A full bridge uses two half-bridge stages to drive the load differentially. It provides a good signal to noise ratio (SNR) and enough drive capability for a 4 Ohm speaker driver.
6.3 CODEC
The built-in codec has a high Signal to Noise ratio performance. This built-in codec consist of an analog to digital converter (ADC), a digital to analog converter (DAC) and additional analog circuitry.
6.4 LINE IN (Aux In)
The chip supports one analog line in from external audio source. The analog line in signal can be processed by the DSP to generate different sound effect (Multi-band Dynamic Range Compression, Audio Widening). The sound effect can be set up by DSP tool.
Mono Audio SoC
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7.0 POWER MANAGEMENT UNIT
The on-chip Power management Unit (PMU) has two main feature; Lithium Ion battery charging and voltage regulation. A power switch is used to switch over the power source between battery and adaptor automatically. The PMU also provides driving current for 2 LEDs.
7.1 CHARGING A BATTERY
Mono audio chip has a built-in battery charger which is optimized for lithium polymer batteries. The charger includes a current sensor for charging control, user programmable current regulation and high accuracy voltage regulation.
The charging current parameters are configured by “IS20XXS_UI” tool. Whenever the adaptor is plug-in, the charging circuit will be activated. Reviving, Pre-charging, Constant Current and Constant Voltage modes are implemented and re-charging function is also included. The maximum charging current is 350mA.
FIGURE 7-1: CHARGING CURVE
7.2 VOLTAGE MONITORING
A 10-bit Successive-Approximation-Register analog to digital converter (SAR ADC) provides one dedicated channel for battery voltage level detection. The warning level is programmable by “IS20XXS_UI”
tool. This ADC provides a good resolution that MCU can control the charging process.
7.3 LDO
The built-in LDO is used to convert the battery or adaptor power for power supply. It also integrates hardware architecture to control power on/off procedure. The built-in programmable LDOs provide power for codec and digital IO pads. It is used to buffer the high input voltage from battery or adapter. This LDO needs 1uF bypass capacitor.
7.4 SWITCHING REGULATOR
The built-in programmable output voltage regulator can convert battery voltage for RF and baseband core power supply. This converter has high conversion efficiency and fast transient response.
Precharge Voltage
2.5v
CC Voltage 3.0v
CC current 0.5c
Recharge Voltage
4.1v
CV Voltage 4.2v Constant Current Mode Constant Voltage Mode
Recharge
ModePre charge
Mode
Reviving
Mode
Reviving Current
2mA
Precharge Current
0.1c
Recharge current
0.25c
Mono Audio SoC
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7.5 LED DRIVER
There are two dedicate LED drivers to control the LEDs. They provide enough sink current (16 step control and 0.35mA for each step) that LED can be connected directly with IS20XXS. LED setting can be set up by “IS20XXS_UI” tool.
IS20XXSLED1
LED2
SYS_PWR
Mono Audio SoC
Page 19
8.0 GENERAL PURPOSE IOs
Stereo audio chip provides six IOs for key functions. The corresponding key functions can be set up by “IS20XXS_UI” tool. The first button (Button 0) must be power key. The power on/off functions only can be set on PWR pin. There are four different operations (short click, long click, double click and combinations) for every button can be defined as different functions. All these function can be set up by “IS20XXS_UI” tool.
IO Pin for Buttons
Button Name Default Functions IO pin name
Button 0 Power / MFB PWR
Button 1 PLAY/PAUSE P0_2
Button 2 Volume UP P2_7
Button 3 Volume DOWN P0_5
Button 4 FWD P0_1
Button 5 REV P0_3 Note: All these function can be set up by “IS20XXS_UI” tool.
Some signals were generated to indicate or control outside devices. The most popular applications are
NFC for easy pairing, external audio amplifier for louder speaker and buzzer for indication.
IOs pin for added functions
Functions IO configurable features
Slide switch P0_0 / P1_5
Buzzer P0_3
NFC detect P0_4 / P1_5
External AMP enable P1_5 Note: All these function can be set up by “IS20XXS_UI” tool.
Mono Audio SoC
Page 20
9.0 OPERATION WITH EXTERNAL MCU IS20XXS support UART command set to make an external MCU to control IS20XXS chip. Here is the connection interface between IS20XXS and MCU. FIGURE 9-1: INTERFACE BETWEEN MCU AND IS20XX CHIP
MCU can control IS20XXS chip by UART interface and wakeup IS20XXS by PWR pin. IS20XXS provide wakeup MCU function by connect to P0_0 pin of IS20XX.
“UART_CommandSet_v154” document provide all UART command which IS20XX support and “IS20XXS_UI” tool will help you to set up your system support UART command.
For more detail description, please reference “UART_CommandSet_v154” document and “IS20XXS_UI”
tool.
IS20XXS
HCI_TXD
HCI_RXD
PWR
P0_0
MCUUART_TX
UART_RX
MCU_WAKEUP
BT_WAKEUP
UART interface
UART interface
Mono Audio SoC
Page 21
9.1 TIMING SEQUENCE OF UART APPLICATION FIGURE 9-2: POWER ON/OFF SEQUENCE
Mono Audio SoC
Page 22
FIGURE 9-3: TIMING SEQUENCE OF RX INDICATION AFTER POWER ON
FIGURE 9-4: TIMING SEQUENCE OF POWER OFF
Mono Audio SoC
Page 23
FIGURE 9-5: TIMING SEQUENCE OF POWER ON (NACK)
FIGURE 9-6: RESET TIMING SEQUENCE IF MODULE HANGS UP
Mono Audio SoC
Page 24
FIGURE 9-7: TIMING SEQUENCE OF POWER DROP PROTECTION
BAT_IN +4V
RST_N from Reset IC
If BT’s BAT use adaptor translates voltage by LDO, we recommend use “Reset IC” to avoid power
off suddenly. Rest IC spec output pin must be “Open Drain”、delay time ≦ 10ms
Recommend part: TCM809SVNB713 or G691L263T73
Power
Off
2.9V ~
3V
Mono Audio SoC
Page 25
10.0 ANTENNA PLACEMENT RULE
For Bluetooth product, antenna placement will affect whole system performance. Antenna need free space to transmit RF signal, it can’t be surround by GND plane. Here are some examples of good and poor placement on a Main application board with GND plane.
FIGURE 10-1: ANTENNA PLACEMENT EXAMPLES
FIGURE 10-2: KEEP OUT AREA SUGGESTION FOR ANTENNA
For more detail free space of antenna placement design, you can reference the design rule of antenna produce vendor.
System GND Plane Worse Case
Poor Case
Good Case
Acceptable Case
Antenna
Antenna
Antenna
Antenna
Mono Audio SoC
Page 26
11.0 SPECIFICATIONS Table 11-1: ABSOLUTE MAXIMUM SPECIFICATION
Symbol Parameter Min Max Unit
VDD_CORE Digital core supply voltage 0 1.35 V
VCC_RF RF supply voltage 0 1.35 V
SAR_VDD SAR ADC supply voltage 0 2.1 V
VDDA/VDDAO CODEC supply voltage 0 3.3 V
VDD_IO I/O supply voltage 0 3.6 V
BK_VDD BUCK supply voltage 0 4.3 V
LDO31_VIN Supply voltage 0 4.3 V
BAT_IN Input voltage for battery 0 4.3 V
ADAP_IN Input voltage for adaptor 0 7.0 V
TSTORE Storage temperature -65 +150 ºC
TOPERATION Operation temperature -20 +70 ºC
Table 11-2: RECOMMENDED OPERATING CONDITION
Symbol Parameter Min Typical Max Unit
VDD_CORE Digital core supply voltage 1.14 1.2 1.26 V
VCC_RF RF supply voltage 1.22 1.28 1.34 V
SAR_VDD SAR ADC supply voltage 1.62 1.8 1.98 V
VDDA/VDDAO CODEC supply voltage 2.7 2.8 3.0 V
VDD_IO I/O supply voltage 2.7 3.0 3.3 V
BK_VDD 1.8V BUCK supply voltage 3 3.7 4.25 V
LDO31_VIN 3V LDO supply voltage 3 3.7 4.25 V
BAT_IN Input voltage for battery 3 3.7 4.25 V
ADAP_IN Input voltage for adaptor 4.5 5 5.5 V
TOPERATION Operation temperature -20 +25 +70 ºC Note: All these supply voltage are programmable by EEPROM parameters.
Mono Audio SoC
Page 27
Table 11-3: BUCK SWITCHING REGULATOR
Parameter Min Typical Max Unit
Input Voltage 3.0 3.7 4.25 V
Output Voltage (Iload=70mA, Vin=4V) 1.7 1.8 2.05 V
Output Voltage Accuracy ±5 %
Output Voltage Adjustable Step 50 mV
/Step
Output Adjustment Range -0.1 +0.25 V
Average Load Current (ILOAD) 120 mA
Conversion efficiency (BAT=3.8V, Iload = 50mA) 88 %
Quiescent Current (PFM) 40 μA
Output Current (peak) 200 mA
Shutdown Current <1 μA
Note: (1) Test condition: SAR_VDD=1.8V, temperature=25 ºC. (2) These parameters are characterized but not tested in manufacturing.
Table 11-4: LOW DROP REGULATOR
Parameter Min Typical Max Unit
Input Voltage 3.0 3.7 4.25 V
Output Voltage
VOUT CODEC 2.8
V
VOUT IO 2.8
Output Accuracy (VIN=3.7V, ILOAD=100mA, 27’C) ±5 %
Output current (average) 100 mA
Drop-out voltage (Iload = maximum output current)
300 mV
Quiescent Current (excluding load, Iload < 1mA)
45 μA
Shutdown Current <1 μA Note: (1) Test condition: SAR_VDD=1.8V, temperature=25 ºC. (2) These parameters are characterized but not tested in manufacturing.
Mono Audio SoC
Page 28
Table 11-5: BATTERY CHARGER
Parameter Min Typical Max Unit
Input Voltage 4.5 5.0 5.5 V
Supply current to charger only 3 4.5 mA
Maximum Battery Fast Charge Current Note: ENX2=0
Headroom > 0.7V (ADAP_IN=5V)
170 200 240 mA
Headroom = 0.3V (ADAP_IN=4.5V)
160 180 240 mA
Maximum Battery Fast Charge Current Note: ENX2=1
Headroom > 0.7V (ADAP_IN=5V)
330 350 420 mA
Headroom = 0.3V (ADAP_IN=4.5V)
180 220 270 mA
Trickle Charge Voltage Threshold 3 V
Battery Charge Termination Current, (% of Fast Charge Current)
10 %
Note: (1) Headroom = VADAP_IN – VBAT (2) ENX2 is not allowed to be enabled when VADAP_IN – VBAT > 2V (3) These parameters are characterized but not tested in manufacturing.
Table 11-6: LED DRIVER
Parameter Min Typical Max Unit
Open-drain Voltage 3.6 V
Programmable Current Range 0 5.25 mA
Intensity Control 16 step
Current Step 0.35 mA
Power Down Open-drain Current 1 μA
Shutdown Current 1 μA Note: (1) Test condition: SAR_VDD=1.8V, temperature=25 ºC. (2) These parameters are characterized but not tested in manufacturing.
Mono Audio SoC
Page 29
Table 11-7: AUDIO CODEC DIGITAL TO ANALOGUE CONVERTER
T= 25oC, Vdd=3.0V, 1KHz sine wave input, Bandwidth = 20Hz~20KHz
Parameter (Condition) Min. Typ. Max. Unit
Over-sampling rate 128 fs
Resolution 16 20 Bits
Output Sample Rate 8 48 KHz
Signal to Noise Ratio Note: 1 (SNR @cap-less mode) for 48kHz
96 dB
Signal to Noise Ratio Note: 1 (SNR @single-end mode) for 48kHz
98 dB
Digital Gain -54 4.85 dB
Digital Gain Resolution 2~6 dB
Analog Gain -28 3 dB
Analog Gain Resolution 1 dB
Output Voltage Full-scale Swing (AVDD=2.8V) 495 742.5
mV rms
Maximum Output Power (16Ω load) 34.5 mW
Maximum Output Power (32Ω load) 17.2 mW
Allowed Load Resistive 8 16 O.C. Ω
Capacitive 500 pF
THD+N (16Ω load) 0.05 %
Signal to Noise Ratio (SNR @ 16Ωload) 96 dB Note: (1) fin=1KHz, B/W=20~20KHz, A-weighted, THD+N < 0.01%, 0dBFS signal, Load=100KΩ (2) These parameters are characterized but not tested in manufacturing.
Mono Audio SoC
Page 30
Table 11-8: Audio codec Analogue to Digital Converter
T= 25oC, Vdd=3.0V, 1KHz sine wave input, Bandwidth = 20Hz~20KHz
Parameter (Condition) Min. Typ. Max. Unit
Resolution 16 Bits
Output Sample Rate 8 48 KHz
Signal to Noise Ratio Note: 1
(SNR @MIC or Line-in mode) 90 dB
Digital Gain -54 4.85 dB
Digital Gain Resolution 2~6 dB
MIC Boost Gain 20 dB
Analog Gain 60 dB
Analog Gain Resolution 2.0 dB
Input full-scale at maximum gain (differential) 4 mV rms
Input full-scale at minimum gain (differential) 800 mV rms
3dB bandwidth 20 KHz
Microphone mode (input impedance) 24 KΩ
THD+N (microphone input) @30mVrms input 0.02 % Note: (1) fin=1KHz, B/W=20~20KHz, A-weighted, THD+N < 1%, 150mVpp input (2) These parameters are characterized but not tested in manufacturing.
Mono Audio SoC
Page 31
Table 11-9: SINGLE-CHANNEL CLASS-D AMPLIFIER
Parameter (Condition) Min. Typ. Max. Unit
Standalone SNR (A-weighting) 100 dB
Gain 12 dB
PSRR (217Hz, 200mV on PVDD) 70 dB
Efficiency 4ohm 80 85 %
8ohm 85 90 %
Supply Voltage 3.0 3.7 4.5 V
Load 4 ohm
Quiescent current (1 channel) 2 mA
Sample frequency 250 KHz
Over current limits 2.3 A
Shutdown current 1.0 uA Note: (1) Test condition: PVDD_CDA=4.2V, temperature=25 ºC. (2) These parameters are characterized but not tested in manufacturing.
Table 11-10: SYSTEM CURRENT CONSUMPTION
System Status Typ. Max. Unit
System Off Mode 2 5 uA
Standby Mode 0.8 mA
Linked Mode 0.4 mA
SCO Link 7.8 mA
A2DP Link (V p-p=200mV; 1k tone signal) 10.7 mA
Note: Use IS2010 EVB as test platform. Test condition: BAT_IN= 3.8V, link with HTC EYE cell phone.
Mono Audio SoC
Page 32
Table 11-11: TRANSMITTER SECTION FOR BDR and EDR
Parameter Min Typ Max Bluetooth
specification Unit
Maximum RF transmit power 3.0 4.0 -6 to 4 dBm
Relative transmit power -4 -1.2 1 -4 to 1 dB Note: The RF Transmit power is calibrated during production using MP Tool software and MT8852 Bluetooth Test equipment. Test condition: VCC_RF= 1.28V, temperature=25 ºC.
Table 11-12: RECEIVER SECTION FOR BDR and EDR
Modulati
on Min Typ Max
Bluetooth specification
Unit
Sensitivity at 0.1% BER
GFSK -90 ≤-70 dBm
Sensitivity at 0.01% BER
π/4 DQPSK
-91 ≤-70 dBm
8DPSK -82 ≤-70 dBm
Note: (1) Test condition: VCC_RF= 1.28V, temperature=25 ºC. (2) These parameters are characterized but not tested in manufacturing.
Mono Audio SoC
Page 33
12.0 REFERENCE CIRCUIT FIGURE 12-1: IS2008/10S reference circuit
FIGURE 12-2: IS2013/15S reference circuit
P1_5
R129
100K
12
R52
100K
1 2
ON
SW
10
SW
-1B
IT
12
GD
S
Q14
STS
2301
13
2
Q8
STS
2306
31
2
SY
S_P
WR
R50
10K
1 2
SW
3P
T-5
501G
12
34
VD
DIO
SLIDE SWITCH
MF
B
R14
1K
1 2
C136
10u/1
6V
L10
L10uH
-2
MIC
2+
D12
SP
E0572
2 1
MIC
1+
D13
SP
E0572
2 1
D10
SP
E0572
2 1
D11
SP
E0572
2 1
MIC
2-
MIC
1-
FWD
C66
15p/5
0V
VOL_UP
SW
6
SW
-TA
CT
12
34
P2_7
C68
15p/5
0V
SW
8
SW
-TA
CT
12
34
P0_2
C64
15p/5
0V
VOL_DN
REV
PLAY/PAUSE
SW
4
SW
-TA
CT
12
34
AD
AP
_IN
P0_3
C65
15p/5
0V
SW
5
SW
-TA
CT
12
34
P0_5
C67
15p/5
0V
SW
7
SW
-TA
CT
12
34
P0_1
AOHPL
AOHPMS
TP
13
1
AO
HP
LTP
11
1
C11
10p/5
0V
AO
HP
M
C15
10p/5
0V
C12
39p/5
0V
C17
39p/5
0V
AO
HP
M
D16
SP
E0572
2 1
D14
SP
E0572
2 1
AO
HP
L
Board
Nam
e
Siz
eTitle
Rev
Date
:S
heet
of
P/N
MA
IN C
IRC
UIT
1.4
IS2008/1
0S
Re
fere
nce
Cir
cu
it
C
22
Wednesday
, M
ay
20,
2015
XXXX
5F
, N
o.5
, In
dustr
y E
. R
d. V
II, H
sin
chu S
cie
nce P
ark
,
Hsin
chu C
ity
30078,
Taiw
an
TE
L.
886-3
-5778385
C28
1u/1
6V
RF
LD
O_O
C29
1u/1
6V
C32
1u/1
6V
1V
21V
8
AN
T1
AN
T-M
P8
1
TP
9
RF
-TP
1
C4
NP
-0402
L2
1nH
C3
NP
-0402
P0_3
ULP
C_V
SU
SV
BG
IS2008S
IS2010S
U6
IS2010S
_M
H+2M
IC
MIC
N2
2
AOHPL47 VDDA48
VC
OM
1
MIC
N1
4
MIC
P1
5
MIC
BIA
S6
VD
D_C
OR
E7
VD
D_IO
11
RS
T_N
10
P12
8
P13
9
P0543
HCI_TXD15HCI_RXD14
XO_P37
XO
_N
36
ULP
C_V
SU
S35
P2742
VB
G34
RF
LD
O_O
33
PM
IC_IN
32
CLD
O_O
31
NC21
SYS_PWR23
P2041
P1513
P0240
P01
12
VDD_IO44
RTX39
VCC_RF38
EP49
VDDAO45 AOHPM46
MIC
P2
3
P03
30
CODEC_VO16
LDO31_VIN17
LDO31_VO18
ADAP_IN19
BAT_IN20
SAR_VDD22
BK_VDD24
BK
_LX
25
BK
_O
26
PW
R27
LE
D1
29
LE
D2
28
R68
1K
/1%
1 2
1V
8
VB
G
MF
B
C26
1u/1
6V
LE
D1
ULP
C_V
SU
S
C25
1u/1
6V
LE
D2
C77
10u/1
6V
P0_1
CO
DE
C_V
O
C23
1u/1
6V
C27
1u/1
6V
2V
8
C81
10u/1
6V
C19
1u/1
6V
C82
10u/1
6V
C87
1u/1
6V
1V
8
ADAP_IN
SY
S_P
WR
BA
T_IN
C80
1u/1
6V
(Peak current: 400mA !!)
CO
DE
C_V
O
C84
1u/1
6V
C79
1u/1
6V
C83
1u/1
6V
C78
1u/1
6V
SY
S_P
WR
SY
S_P
WR
2V
8
P1_5
P2_0P2_7P0_5
P0_2
C31
1u/1
6V
MIC
_N
2M
IC_P
2M
IC_N
1M
IC_P
1
RF
LD
O_O
L3
6.8
p/5
0V
C86
1u/1
6V
MIC
_B
IAS
1V
2
2V
8
P1_2
C34
1u/1
6V
P1_3
RS
T_N
C41
1u/1
6V
C36
1u/1
6V
AOHPMAOHPL
(1uF X5R or 4.7uF Y5V)
R69
1K
1 2
SY
S_P
WR
P1_5
Q7
STS
2306
31
2
R23
1M
1 2
GD
SQ9
STS
2301
13
2
D20
21
D21
CD
SU
400B
12
D22
CD
SU
400B
12
R25
270/1
%
12
R29
120/1
%1
2
MF
B
R30
1K
/1%
1 2
R13
NP
-0805
TP
29
1
NFC
TP
30
1
U7
AC
E24C
64
A0
1
A1
2
A2
3
GN
D4
SD
A5
SC
L6
WP
7V
CC
8
HCI_RXDHCI_TXD
AD
AP
_IN
SY
S_P
WR
MF
B
SW
9S
W-T
AC
T
12
34
ADAPTOR PLUG IN RESET
R28
2K
1 2
C70
1u/1
6V
Q3
MM
BT3904
32
1
RS
T_N
C21
10p/5
0V
C24
10p/5
0V
X1
X4P
-16M
HZ
41
32
EEPROM
MIC
_P
1
C35
0.0
47u/2
5V M
IC_N
1
C43
0.0
47u/2
5V
C37
220p/5
0V
R10
2K
12
TP
5 1
MIC
_B
IAS
MIC
1+
TP
6 1
MIC
1-
MIC1
R6
1K
12
C20
4.7
u/1
0V
C22
4.7
u/1
0V R
71K
12
MIC
_P
2
C40
0.0
47u/2
5V M
IC_N
2
C42
220p/5
0V C44
0.0
47u/2
5V
R11
2K
12
TP
7 1
MIC
2-
MIC
2+
TP
8 1 MIC2
MIC
_B
IAS
R8
1K
12
C46
4.7
u/1
0V
C45
4.7
u/1
0V
R9
1K
12
2V
8
P1_2
R18
NP
-0603
AD
AP
_IN
P1_3
C39
1u/1
6V
R17
4K
7
1 2
EEPROM
C38
0.1
u/1
6V
POWER
P2
DC
-JA
CK
1 2 3
LED
1V
2
TP
35 1
CORE_LDO
RF_LDO
RF
LD
O_O
RS
T_N
TP
28 1
ADAP
BAT-
BK_OUT
HCI_TXD
TEST POINT
GND
HCI_RXD
RESET
HC
I_TXD
HC
I_R
XD
CODEC_VDD
AD
AP
_IN
P2_0
TP
17
1
TP
15
1
TP
19
1
TP
16
1
TP
20 1
TP
21
1
TP
24
1
TP
22
1
1V
8
TP
25
1
BA
T_IN
TP
26
1
CO
DE
C_V
O
P2_0
BAT+
VD
DIO
TP
27
1
VDD_IO
LE
D2
LE
D1
LE
D1
LE
D-B
12
LE
D2
LE
D-H
R1
2S
YS
_P
WR
Mono Audio SoC
Page 34
13.0 PACKAGE INFORMATION 13.1 CHIP IDENTIFICATION SYSTEM
PART NO. X -Y (Chip Name) (Package Type) (Version) Chip name: IS2008 IS2010 IS2013 IS2015 Package Type: S = QFN (Saw Type) Package Version: e.g. “-203” is means the chip version is 203.
Examples: a) IS2015S-002: 002 version ROM code IS2015 chip in QFN type package.
CO
DE
C_
VO
C3
11
u/1
6V
AO
HP
LA
OH
PM
C7
71
0u
/16
V
(Vo=(1+ R24/R16)*1.25)
R6
81
K/1
%
1 2
1V
8
C2
31
u/1
6V
MIC
_N
1
MIC
_P
1
C3
72
20
p/5
0VC3
50
.04
7u
/25
V
C4
20
.04
7u
/25
V
AIL
MF
B
MIC
_P
1M
IC_
N1
C2
71
u/1
6V
MIC
_B
IAS
C2
61
u/1
6V
VB
G
C2
51
u/1
6V
UL
PC
_V
SU
S
2V
8
P1_3
P1_2
C4
11
u/1
6V
RS
T_
N
C3
61
u/1
6V
AD
AP
_IN
CDA
(Close to IC)
HP
ON
_O
D2
3S
PE
0572
2 1
HP
OP
_O
D2
4S
PE
0572
2 1
FB
6G
SM
A2
01
20
91
2
FB
5G
SM
A2
01
20
9
12
HP
OP
HP
OP
_O
C5
02
20
p/5
0V
HP
ON
C4
32
20
p/5
0V
HP
ON
_O
TP
311
TP
321
C2
11
0p
/50
V
C2
41
0p
/50
V
X1
X4
P-1
6M
HZ
41
32
IS2013S
IS2015S
U6
AO
HP
L3
VD
DA
4
VC
OM
5
MIC
N1
6
MIC
P1
7
MIC
BIA
S8
VD
D_
IO14
RS
T_
N13
P12
11
P13
12
VD
D_
CO
RE
10
P2416
EP57
VD
DA
O1
AO
HP
M2
PVDD_CDA56
HPOP_CDA55
HPON_CDA54
VBP_CDA53
AVDD_CDA52
XO
_N
42
UL
PC
_V
SU
S41
AIL
9
VB
G40
RF
LD
O_
O39
PM
IC_
IN38
CL
DO
_O
37
EA
N36
P2748
P0417
LE
D1
33
LE
D2
32
PW
R30
LD
O1
8_
O29
P00
34
P2047
P3049
P0246
P0115
VDD_IO51
RTX45
VCC_RF44
XO_P43
P0550
HCI_RXD19
HCI_TXD20
P03
35
P1518
CODEC_VO21
LDO31_VIN22
LDO31_VO23
ADAP_IN24
BAT_IN25
SAR_VDD26
SYS_PWR27
LDO18_VDD28
NC
31
R2
6N
P-0
80
5
FB
9G
SM
A2
01
20
9
12
C1
81
u/1
6V
HPONHPOP
R1
02K
12
C8
81
0u
/16
V
CD
A_
PW
R
C1
61
u/1
6V
+
C6
01
00
u/1
6V1 2
+
C1
17
10
0u
/16
V
1 2
(Peak current: 1A !!)
+
C6
11
00
u/1
6V
1 2
C8
10
u/1
6V
C3
31
u/1
6V
(C88 should close
to IC!!)
PV
DD
_C
DA
_IN
R2
1K
8/1
%
1 2
C7
10
u/1
6V
AD
AP
_IN
R2
0N
P-0
60
3
C5
0.1
u/1
6V
C6
10
u/1
6V
U1
AP
L1117-V
C
ADJ/GND1
OUT2
IN3
R1
620
1 2
R9
1K
/1%
1 2
BA
T_
IN
D2
1N
40
02
21
GD
S Q4
STS
23
01
13
2
R1
120K
1 2
5V
CD
A_
PW
R
Warning! 4.5V max
R6
0300
12
R6
1300
12
C3
00
.1u
/16
VP
3T
SH
-38
65
D
4 32 10
1
P3_0
R6
2N
P-0
60
3
LINE
INPUT
AIR
R
R6
3N
P-0
60
3
AIL
AIL
L
C4
01
u/1
6V
AOHPL
AOHPMS
TP
13
1 TP
11
1A
OH
PL
C1
11
0p
/50
V
AO
HP
M
C1
51
0p
/50
V
C1
23
9p
/50
V
P0_2
C1
73
9p
/50
V
P2_7
P0_5
AO
HP
M
P0_1
AO
HP
L
D1
4S
PE
0572
2 1
D1
6S
PE
0572
2 1
VOL_UP
FWD
C6
61
5p
/50
V
D1
3S
PE
0572
2 1
MIC
1+ C6
81
5p
/50
V
TP
61T
P5
1
SW
6
SW
-TA
CT
12
34
OPTIONAL: 4.5V Booster Circuit
If no boost, add R26 0-ohm
SW
8
SW
-TA
CT
12
34
PLAY/PAUSE
MIC1
P0_3
VOL_DN
REV
MIC
_B
IAS
C6
41
5p
/50
V
SW
4
SW
-TA
CT
12
34
MIC
1-
MIC
1+
C6
51
5p
/50
V
SW
5
SW
-TA
CT
12
34
C6
71
5p
/50
V
MF
BMIC
1-
D1
0S
PE
0572
2 1
SW
7
SW
-TA
CT
12
34
D1
8S
PE
0572
2 1
SY
S_
PW
R
SW
9S
W-T
AC
T
12
34
D1
9S
PE
0572
2 1
AIL
L
AIR
R
Audio
EEPROM
C2
81
u/1
6V
C2
91
u/1
6VR
FL
DO
_O
P0_0
C3
21
u/1
6V
VB
G
R1
29
100K
12
1V
21V
8
UL
PC
_V
SU
S
SW
10
SW
-1B
IT
12
R5
2
100K
1 2
Q8
STS
23
06
31
2
SY
S_
PW
R
R5
010K
1 2
GD
S
Q14
STS
23
01
13
2
VD
DIO
SW
3P
T-5
50
1G
12
34
MF
B
SLIDE SWITCH
R1
4
1K
1 2
C1
36
10
u/1
6V
2V
8
P1_2
R1
8N
P-0
60
3
P1_3
C3
91
u/1
6V
R1
74K
7
1 2
EEPROM
C3
80
.1u
/16
V
U3
SM
48
39
N
S1
S2
S3
G4
D8
D7
D6
D5
R1
6390K
12
L1
L1
0u
H-3
TP
9
RF
-TP
1
L2
1nH
12 R
24
1M
12
CO
DE
C_
VO
R2
10
12A
NT
1
AN
T-M
P8
1
C3
NP
-04
02
R2
2N
P-0
60
3
C4
NP
-04
02
U2
RT
92
66
E
CE
1
EXT
2
GN
D3
LX
4
VD
D5
FB
6
D1
1N
58
22
21
HCI_RXDHCI_TXD
P0_3
P0_0
R6
91
K/1
%
1 2
P0_1P2_4
C8
21
0u
/16
VC
81
10
u/1
6V
P0_4
C8
71
u/1
6V
1V
8S
YS
_P
WR
BA
T_
IN
(Peak current: 400mA !!)
CO
DE
C_
VO
C8
41
u/1
6V
C8
01
u/1
6V
C8
31
u/1
6V
C7
91
u/1
6V
C7
81
u/1
6VSY
S_
PW
R
SY
S_
PW
R2V
8
Optional if ADAP_IN>5V
2V
8
POWER
AD
AP
_IN
P2
DC
-JA
CK
1 2 3
LE
D2
LE
D1
AD
AP
_IN
P0_4
SY
S_
PW
R
Q7
STS
23
06
31
2
R2
31M
1 2
GD
SQ9
STS
23
01
13
2
D2
1C
DS
U4
00
B1
2
D2
0
21
D2
2C
DS
U4
00
B1
2
R2
91
20
/1%
12
R2
52
70
/1%
12
MF
B
R1
3N
P-0
80
5
R3
01
K/1
%
1 2
TP
29
1
NFC TP
30
1
2V
8
C1
91
u/1
6V
LE
D2
LE
D1
SY
S_
PW
R
LE
D1
LE
D-B
12
LED
LE
D2
LE
D-H
R1
2A
DA
P_
IN
ADAPTOR PLUG IN
RESET
RS
T_
N
R2
82K
1 2
C7
01
u/1
6V
Q3
MM
BT3
90
4
32
1
P0_5
P0_2
P3_0 P3_0
P2_0P2_7
1V
2
TP
35
1CORE_LDO
RF
LD
O_
O
TP
28
1RF_LDO
RS
T_
N
LDO18_OUT
BAT-
ADAP
GND
TEST POINT
HCI_TXD
RESET
HCI_RXD
HC
I_R
XD
HC
I_TX
D
EA
N
P2_4
P2_0
TP
15
1
CODEC_VDD
TP
16
1
TP
18
1
TP
20
1TP
17
1TP
19
1
TP
21
1TP
22
1 TP
23
1
TP
24
1 TP
25
1
1V
8T
P2
61
BA
T_
IN
BAT+
P2_0
CO
DE
C_
VO
TP
27
1
P2_4
VDD_IO
VD
DIO
EAN
(1uF X5R or 4.7uF Y5V)
Bo
ard
Na
me
Siz
eT
itle
Re
v
Da
te:
Sheet
of
P/N
MA
IN C
IRC
UIT
2.3
IS2013/1
5 R
efe
ren
ce
Cir
cu
it
Cu
sto
m
22
Th
urs
da
y,
Ap
ril 0
2,
20
15
XX
XX
5F
, N
o.5
, In
dustr
y E
. R
d. V
II, H
sin
chu S
cie
nce P
ark
,
Hsin
ch
u C
ity
30
07
8,
Ta
iwa
nT
EL
.
88
6-3
-57
78
38
5
RF
LD
O_
O
C8
61
u/1
6V
L3
6.8
p/5
0V
R6
1K
12
C2
24
.7u
/10
VC
20
4.7
u/1
0V
R7
1K
12
C3
41
u/1
6V
1V
2
U7
AC
E2
4C
64
A0
1
A1
2
A2
3
GN
D4
SD
A5
SC
L6
WP
7V
CC
8
Mono Audio SoC
Page 35
b) IS2010S-203: 203 version ROM code IS2010 chip in QFN type package.
13.2 PACKAGE MARKING INFORMATION
48 Lead QFN (6x6x0.9 mm) Example
56 Lead QFN (7x7x0.9 mm) Example
Mono Audio SoC
Page 36
Legend:
XXX: Chip serial number version and ○e3 Pb-free JEDEC designator for Matte Tin (Sn)
YY: Year code (last 2 digits of calendar year) WW: Week code (week of January 1 is week “1”) NNN: Alphanumeric traceability code
13.3 PACKAGE DETAIL
QFN48 6x6 Chip Outline (IS2008S /IS2010S)
Mono Audio SoC
Page 37
QFN48 6x6 PCB Footprint (IS2008S /IS2010S)
Mono Audio SoC
Page 38
QFN56 7x7 Chip Outline (IS2013S / IS2015S)
Mono Audio SoC
Page 39
QFN56 7x7 PCB Footprint (IS2013S / IS2015S)
Mono Audio SoC
Page 40
14.0 REFLOW PROFILE AND STORAGE CINDITION
Mono Audio SoC
Page 41
14.1 STENCIL OF SMT ASSEMBLY SUGGESTION
14.1.1 STENCIL TYPE & THICKNESS Laser cutting Stainless steel Thickened 0.5 mm Pitch: thickness < 0.15 mm
14.1.2 APERTURE SIZE AND SHAPE FOR TERMINAL PAD
Aspect ratio (width/thickness) > 1.5 Aperture shape The stencil aperture is typically designed to match the pad size on the PCB. Oval-shaped opening should be used to get the optimum paste release. Rounded corners to minimize clogging. Positive taper walls (5o tapering) with bottom opening larger than the top.
14.1.3 APERTURE DESIGN FOR THERMAL PAD
The small multiple openings should be used in steady of one big opening. 60~80% solder paste coverage Rounded corners to minimize clogging Positive taper walls (5° tapering) with bottom opening larger than the top
Don’t recommend Recommend Recommend Coverage 91% Coverage 77% Coverage 65%
14.2 REFLOW CONDITION
PCB
Stencil
Mono Audio SoC
Page 42
1.) Follow : IPC/JEDEC J-STD-020 2.) Condition :
Average ramp-up rate (217℃ to peak): 1~2℃/sec max.
Preheat：150~200C、60~180 seconds
Temperature maintained above 217℃ : 60~150 seconds
Time within 5℃ of actual peak temperature: 20 ~ 40 sec.
Peak temperature：260 +5/-0 ℃
Ramp-down rate : 3℃/sec. max.
Time 25℃ to peak temperature : 8 minutes max.
Cycle interval：5 minus
FIGURE 14-1: REFLOW PROFILE
14.3 STORAGE CONDITION
Slope: 1~2℃/sec max.
(217℃ to peak)
Ramp down rate :
Max. 3℃/sec.
Preheat: 150~200℃
25℃
217℃
peak: 260 +5/-0℃
60 ~ 180 sec. 60 ~150sec
20~40 sec.
Time (sec)
1. Calculated shelf life in sealed bag: 24 months at < 40 ℃ and <90% relative humidity (RH)
2. After bag is opened, devices that will be subjected to reflow solder or other high temperature process
must be Mounted within 168 hours of factory conditions <30℃/60% RH
FIGURE 14-2: LABEL OF CHIP BAG (Please notice the baking requirement)
