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1 N I SL BSOE/UCSC
RRAM Architectures and Circuits at Nanoscale
Sangho Shin, and Sung Mo “Steve” Kang
Dept. of EE, UCSC
April 6, 2012
2 N I SL BSOE/UCSC
Outline of This Talk
RRAM Architectures and Models II
Complementary RRAMs III
Summary IV
Introduction I
3 N I SL BSOE/UCSC
Memristors and Memristive Electronics
• Circuit Theoretic and Design Research
– Memristive nonlinear dynamics
– Compact device modeling
– Low Power Systems Design
• Nanoelectronics- Memristive Systems
– Ultra-dense nonvolatile memories
– Stateful Boolean logic and resistive nanocomputing
– Self-reconfigurable circuits and systems
– Neuromorphic synaptic circuits and systems, memory-intensive systems for bioinformatics and other applications
Memristor dynamics and crossbar integration
Memristor as 4th fundamental device
4 N I SL BSOE/UCSC
Nonvolatile Resistive Memory
• Nanotechnology Enables Ultra-Dense Memory
Memristive devices array in a nano-crossbar structure
Early memory based on p-Si/a-Si/Ag by Univ. of Michigan
Ref. S.H. Cho, et. al., Nano Letters, 2009
5 N I SL BSOE/UCSC
Resistive Random Access Memory (RRAM)
• Key factors of importance
– Physical Geometry
– Process/Thermal Reliability
– Embedding Compatibility into CMOS
– Forming or formingless
– 3D Stackability
• Challenges for Memory Devices
– Number of Storage Bits/Device
– Retention >10 years
– Endurance > 1017
– Read/Write Energy < 1fJ/bit
– Read/Write Speed < 1ns
6 N I SL BSOE/UCSC
RRAM Architectures and Models II
Complementary RRAMs III
Summary IV
Introduction I
7 N I SL BSOE/UCSC
Issues on RRAMs
• Technology issues
– Reliable device process (Variability)
– Multi-layer memory integration
• Circuit issues
– Power consumption for Write/Read operations
– Performance degradation by “Sneak currents”
– “Data-pattern” sensitive power & read performance
vS
vR
RS
R11 R12
R21 R22
RS
iS
8 N I SL BSOE/UCSC
How to deal with “Sneak Currents”?
vS.2
vR
RS
R12
R21 R22
RS
(a)
RS
R11 R12
R21 R22
RS
(b)
R11
vS.1
vR
vS.2vS.1
vX
R11 R12
R21 R22
RS
(c)
vR
vS.2vS.1
RS
VBIT
With selection devices (e.g., 1T1R or 1D1R)
Trading-off with power ( 0 ≤ vX < vR )
Forced bit-line voltages (e.g., TIA type)
Performance (a) (b) (c)
Sensing margin Large Narrow Large
Speed Fast Fast Slow
Power Low Moderate ~ High Low
2D capacity Low High High
3D stackability Challenging Good Good
9 N I SL BSOE/UCSC
Sensing Behaviors of RRAMs
• Passive RRAM with Resistor Terminations
– Sensing performance is highly dependent on the stored “Data-pattern”, due to “Sneak Currents”
– The more low-resistance cells lead to the lower sensing margin
gS
vS(k).l
i=k
vR
vS(k).j
gS gS
gkl
gilgij
gkj
0 20 40 60 80 100 120 1400.14
0.16
0.18
0.2
Reading column index (j)
v S(k
).l /
vR
P1=0.2
P1=0.5
P1=0.8
Data-pattern sensitive Read performance (128x128 array)
10 N I SL BSOE/UCSC
RRAM Modeling
• Analysis and Estimation of RRAM Performance (m×n array)
– Full node analysis needs to solve for
gS
vS(k).l
j=l
i=k
GIGII
GIIIGIV
vR
vS(k).j
gS gS
gkl
gilgij
gkj
j≠l
i≠k
To be analyzed
Cellto be read
m-columns
n-r
ow
s
k U
U
U Ii Iu
ukSui
Jy
yi
ji
RjkjkS
Ii
jiS vgg
gvgvgg ..
– A worst case equivalent model has been reported in 1969.
– Computation efficient statistical model for analysis of data- and variability-dependency
– Sub-grouping for modeling
• GI : cell to be read (k, l)
• GII : cells in reading row
• GIII : cells in reading column
• GIV : all the others
for j=1, 2, …, m
11 N I SL BSOE/UCSC
kS
kXkakSP(k)
VCGVG
lkS
kS
IIIeIIIeIVeIIIe
IIIeIVeIVeIVe
IIIeIVe
R
lk
IIe
lkS
kS
lkIIIeS
IIeIVeSeSe
v
v
gggg
gggg
ggv
g
g
v
v
ggg
ggg
.....
....
..
.
..
.... 1
0
0
Rv
kakXPkS GCGV1
2x2 Equivalent Memory Model
• 2×2 equivalent model for n×m RRAM array
– Each group is represented in a single equivalent admittance
– Capable of flexible analysis and ease of simulation
vS(k).l
j=l
i=kvR
vS(k)
gS
j≠l
i≠k
ge.S
ge.II
ge.IV ge.III
gkl
To be analyzed
e.S
IVIVe
XIIIe
IIIIe
SSe
IISe
gnmg
gng
gmg
gmg
m
11
1
1
1
1
.
.
.
.
.
12 N I SL BSOE/UCSC
2x2 Model Results
• Example for 128×128 array
– Conditions : a=ROFF/RON=103, (ROFF=10 M, RON=10 k)
– Data-pattern dependent b (=ROFF/RS) is desirable
100
101
102
103
104
105
10-5
10-4
10-3
10-2
10-1
b (gS/g
OFF)
v S
(k).
l
pII,III,IV
=0.1
pII,III,IV
=0.3
pII,III,IV
=0.5
pII,III,IV
=0.7
pII,III,IV
=0.9
100
101
102
103
104
105
10-9
10-8
10-7
10-6
b (gS/g
OFF)
I cell.
av
pII,III,IV
=0.1
pII,III,IV
=0.3
pII,III,IV
=0.5
pII,III,IV
=0.7
pII,III,IV
=0.9
(a) Detection margin (b) Average cell current
Symbols : n×m simulation
Lines : 2×2 model
13 N I SL BSOE/UCSC
Array Size Dependency
• Optimal RS (RS.opt)
– Generally required to be small for large array sizes
– Sensitive to data-pattern
2 8 32 128 512 2,04810
2
103
104
Array size (n, m)
pII.III.IV
=0.1
pII.III.IV
=0.3
pII.III.IV
=0.5
pII.III.IV
=0.7
pII.III.IV
=0.9
2 8 32 128 512 204810
-3
10-2
10-1
100
Array size (n, m)
pII.III.IV
=0.1
pII.III.IV
=0.3
pII.III.IV
=0.5
pII.III.IV
=0.7
pII.III.IV
=0.9
Detection margin
vS)
Optimum b-ratio
bopt)
• Detection margin (vS)
– Decreases with array size
– Sensitive to data-pattern
– For 1% margin, n & m <128
14 N I SL BSOE/UCSC
Data-Pattern Dependency
• Highly sensitive performance to data-pattern
– bopt/a is approximately linear to data probability
– Data dependent optimum b-ratio (bopt=ROFF/RS.opt) is desirable
• a-ratio (=ROFF/RON) dependency
– Generally good for larger a-ratios (rapidly desensitized as a >102)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10
1
2
3
4
5
6
pII,III,IV
bopt /
a
a=102
a=103
a=104
0 p1
bopt
bopt.max
bopt.min
boptbopt
0 0.2 0.4 0.6 0.8 1
10-2
10-1
100
pII,III,IV
a=101
a=102
a=103
a=104
Detection margin
vS.opt)
15 N I SL BSOE/UCSC
Data-Dependent Adaptable RS.opt
• Adaptable gS configuration
– Composed of grounded replica rows and fixed resistance rows.
• x # of replica rows
• y # of gOFF rows
– Expected value of gS
– Adaptable RS.opt leads to both low-
power and large detection margin.
i=k
vR gkl
vS(k).l
j=l
Replica
rows
(x)
gOFF
rows
(y)
R-RAM
array
optyxpx bab 11
xyx opt
optopt
min.and,
1b
a
b
a
b
16 N I SL BSOE/UCSC
Adaptable RS.opt Example
• 128×128 RRAM array
– RON=10k, ROFF=10M (a=103)
– RS constructions by
• Reconnecting a part of unread RRAM (x=5)
• Dedicated ROFF rows (y=35)
i=k
vR gkl
vS(k).l
j=l
Dedicated
ROFF rows
(y)
RRAM
array
(n)
RS
(x+y)
A part of
RRAM
array
(x)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10
1
2
3
4
5
6
Probabilities of "1"
b /
a r
atio
Worst-case design
Self-adaptable design
17 N I SL BSOE/UCSC
Worst Case vs. Self-adaptable
• Worst case design
– Constant bopt/a that made for the worst case data pattern
– The worst case appears with all stored data of “1”s
– Excess current consumption and reduced detection margin for non-worst cases
• Self-adaptable design
– Adaptable bopt/a that made for every data pattern
– For every data pattern, it provides maximally available detection margin
– Current consumption can be saved for general non-worst cases.
18 N I SL BSOE/UCSC
Performance Comparison
• Worst case vs. self-adaptable design
– Self-adaptable design shows the larger vS and low Icell.av ,
simultaneously, compared to the worst-case design
– Especially for low probability cases
0 0.2 0.4 0.6 0.8 10
1
2
3
4
5
6
7x 10
-7
Probabilities of "1"
Worst-case model
Self-adaptable model
Worst-case design
Self-adapable design
0 0.2 0.4 0.6 0.8 1
10-2
10-1
100
Probabilities of "1"
Worst-case model
Self-adaptable model
Worst-case design
Self-adapable design
Detection margin
vS)
Average cell current
Icell.av)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 110
0
101
102
103
Probabilities of "1"
Sample design: sS improvement [%]
Sample design: Icell.av
reduction [%]
v
Average improvement: + 46% for vS increment + 14% current reduction
19 N I SL BSOE/UCSC
RRAM Architectures and Models II
Complementary RRAMs III
Summary IV
Introduction I
20 N I SL BSOE/UCSC
Complementary Memory Cell
• Complementarily written two devices cell (CR-cell)
– Provides data-dependent equivalent sense resistance (RS.eq )
RM
vS
~
vR
RM
1
11.
a
aRSV
1
1.
a
aCRSV
a/. OFFoptS RR
RM
vS
vR
RS
MeqS RR~
.
1R-cell CR-cell
21.
a OFFRS gI
a
a
1
. OFFCRS gI
Readout circuit configuration
Sense resistance
Normalized detection margin
Normalized average current
> <
<
>
ONOFF RR /a
21 N I SL BSOE/UCSC
Array Properties of CR-cell Array
• Features
– Lower design complexity
• With no optimization process on RS
– Data-dependent equivalent RS
– Reduced effective density
– Doubled number of sneak paths by complementary devices
• Data-pattern dependency
– Constant detection margin
• With larger window
– Regulated readout currents
• With smaller values
vS.2
vR
R11 R12
R21 R22
R11 R12
R21 R22
~ ~
~~
vS.1
2x2 array of CR-cell memories
22 N I SL BSOE/UCSC
n xm Dimensional CR-cell Array
Rij
~
Rkj
vS
Rkl~
m-columns
Ril
Rkl
Ril~
Reading row
(Group-A)
Non-reading
memory rows
(Group-B)
Complementary
of Group-B
(Group-C)
Complementary
of Group-A
(Group-D)Rkj
vR
R11 R12
R21 R22
R11 R12
R21 R22
~ ~
~~
R1m
R2m
R1m
R2m
~
~
Rn1 Rn2
Rn1 Rn2~~
Rnm
Rnm~W
ord
-lin
e d
eco
de
r, M
od
e s
witch
es
Bit-line data buffers,
Mode switches
Mode switches,
Sense Amplifiers
Re
fere
nce
ge
ne
rato
rs
VREF
23 N I SL BSOE/UCSC
Write-Mode Configuration
• 2-Step ‘WORD-wise’ Writing
– Step-1: RESET for all devices of a selected word line
– Step-2: SET for selected bit devices (other devices are halfway selected)
R11 R12
R21 R22
R11 R12
R21 R22
~ ~
~~
R1m
R2m
R1m
R2m
~
~
Rn1 Rn2
Rn1 Rn2~~
Rnm
Rnm~
VW32
VW32
VW
VW
VW31
VW31
VW31
R11 R12
R21 R22
R11 R12
R21 R22
~ ~
~~
R1m
R2m
R1m
R2m
~
~
Rn1 Rn2
Rn1 Rn2~~
Rnm
Rnm~
Step-1: RESET Step-2: Selective SET
Bit controlled
24 N I SL BSOE/UCSC
Read-Mode Configuration
• ‘WORD-wise’ READ
– Comparison VS with VREF
• Reference generation
– Desirable to be data-dependent
– Finding median VS by
dedicated ROFF & RON columns
– Each REF cell has complementary devices (pIII=0.5)
– Reference buffer isolates capacitances of SAs
2/.. LREFHREFREF VVV
VR
R11 R12
R21 R22
R11 R12
R21 R22
~ ~
~~
R1m
R2m
R1m
R2m
~
~
Rn1 Rn2
Rn1 Rn2~~
Rnm
Rnm~
RON
ROFF
ROFF
RON
RON
ROFF
ROFF
RON
RON
ROFF
ROFF
RON
RO RO
VREF
VS.1 VS.2 VS.m VREF.H VREF.L
D1 D2 Dm
VREF generationMemory array
Reading
row
Unread
rows
CMOS
circuitrySAs
Ref. Buff
25 N I SL BSOE/UCSC
Performance Comparison (I)
• Array size dependency
– Optimally designed 1R-cell array vs. CR-cell array
– CR-cell memory is capable of ~4x larger size
Symbols : CR-cells array
Thin lines: 1R-cells array
1R-cell RRAM CR-cell RRAM
101
102
103
10-3
10-2
10-1
100
Array size (n, m)
V
S
p1=0.1
p1=0.3
p1=0.5
p1=0.7
p1=0.9
VS.1R=10-2
101
102
103
10-3
10-2
10-1
100
Array size (n, m)
v S
p1=0.1
p1=0.3
p1=0.5
p1=0.7
p1=0.9
VS.CR=10-2
Data-pattern independent detection performance
26 N I SL BSOE/UCSC
Performance Comparison (II)
• Data-pattern Dependency
– Optimally designed 1R-cell array vs. CR-cell array
– Lower current consumption for all cases
– Data-independent detection performance
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 110
-3
10-2
10-1
100
Probability of data "1"
V
S
n=m=22
n=m=24
n=m=26
n=m=28
n=m=210
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 110
-7
10-6
10-5
10-4
Probability of data "1"
I col.a
vn=m=22
n=m=24
n=m=26
n=m=28
n=m=210
Symbols : CR-cells array
Thin lines: 1R-cells array
Voltage Detection Window Sensing Current
27 N I SL BSOE/UCSC
Variability Effect on Read Performance
• For a 128x128 array:
– Resistances: log-N dist. w/i =20%
– RON.0=10k, ROFF.0=10M
– Array size=128x128
– REF sections for every 8-bits
Section-1 Section-2 ...
0 0.2 0.4 0.6 0.8 10
0.2
0.4
0.6
0.8
1
p1
VR
EF [
V]
0 0.2 0.4 0.6 0.8 1-0.015
-0.01
-0.005
0
0.005
0.01
0.015
p1
VS-V
RE
F [V
] 3VS.LRS
Data-dependent VREF
VS.LRS
VS.HRS
3VS.HRS
28 N I SL BSOE/UCSC
RRAM Architectures and Models II
Complementary RRAMs III
Summary IV
Introduction I
29 N I SL BSOE/UCSC
Summary
• Computation efficient RRAM model
– Data-dependent 2x2 equivalent circuit model
– Provides optimal design parameters for any random data
• Complementarily written RRAM cell (CR-cell) has been presented
– Data-pattern independent sensing performance
– Larger voltage sensing window, Regulated lower sensing current
30 N I SL BSOE/UCSC
References
• D. B. Strukov, G. S. Snider, D. R. Stewart, and R. S. Williams, “The Missing Memristor Found,” Nature, vol. 453, pp.80-83, May 2008.
• L. O. Chua, and S. M. Kang, “Memristive Devices and Systems,” Proc. IEEE, vol. 64, pp.209-223, Feb. 1976.
• G. S. Snider, “Self-organized computation with unreliable, memristive nanodevices,” Nanotechnology 36, Aug. 2007.
• D. B. Strukov and K. K. Likharev, “CMOL FPGA: a reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices,” Nanotechnology, vol. 16, pp. 888-900, 2005.
• S. Shin, K. Kim, and S. M. Kang, “Memristor Application to Programmable Analog ICs,” IEEE Trans. on Nanotechnology, vol.10, no.2, pp.266-274, Mar. 2011.
• B. Mouttet, “Proposal for Memristors in Signal Processing,” Nano-Net 2008, pp. 11-13, 2009.
• M. Liu, and W. Wang, “Application of nanojunction-based RRAM to reconfigurable IC,” Micro & Nano Letters, vol.3, no.3, pp.101-105, Sept. 2008.
• J. Borghetti, G. S. Snider, P. J. Kuekes, J. J. Yang, D. R. Stewart, and R. S. Williams, “‘Memristive’ switch enable ‘stateful’ logic operations via material implication,” Nature, vol. 464, pp. 873-876, Apr. 2010.
• G. S. Rose, Y. Yao, J. M. Tour, A. C. Cabe, N. Gergel-Hackett, N. Majumdar, J. C. Bean, L. R. Harriott, and M. R. Stan, “Designing CMOS/Molecular Memories While Considering Device Parameter Variations,” ACM J. on Emerging Technologies in Computing Systems, vol.3, no.1, Apr. 2007.
• S. H. Jo, K. H. Kim, and W. Lu, “High-Density Crossbar Arrays Based on a Si Memristive System,” Nano Letters, vol. 9, pp. 870-874, 2009.
• Y. Ho, G. M. Huang, and P. Li, “Nonvolatile Memristor Memory: Device Characteristics and Design Implications,” IEEE/ACM Int. Conf. on Computer-Aid Design, pp. 485-490, Nov. 2009.
• S. Shin, K. Kim, and S. M. Kang, “Data-Dependent Statistical Memory Model for Passive Memristive Devices Array,” IEEE Trans. on Circuits and Systems II, vol.57, no.12, pp.986-990, Dec. 2010.
• E. Linn, R. Rosezin, C. Kugeler, and R. Waser, “Complementary resistive switches for passive nanocrossbar memories,” Nature Materials 9, pp. 403-406, 2010.
• W. T. Lynch, “Worst-Case Analysis of a Resistor Memory Matrix,” IEEE Trans. on Computers, vol. c-18, issue 10, pp. 940-942, Oct. 1969.
• M. S. Qureshi, M. Pickett, F. Miao, and J. P. Strachan, “CMOS Interface Circuits for Reading and Writing Memristor Crossbar Array,” ISCAS 2011, pp. 2594-2597, May 2011.
