SAM3S-EK Development Board · The SAM3S Evaluation Kit (SAM3S-EK) enables evaluation capabilities and code development of appli-cations running on a SAM3S4C device. 1.2 User Guide

SAM3S-EK Development Board....................................................................................................................

User Guide

11031C–ATARM–30-Mar-11

Section 1Introduction.................................................................................................................1-1

1.1 SAM3S Evaluation Kit ........................................................................................................ 1-1

1.2 User Guide......................................................................................................................... 1-1

1.3 References and Applicable Documents ............................................................................. 1-1

Section 2Kit Contents ................................................................................................................2-1

2.1 Deliverables ....................................................................................................................... 2-1

2.2 Electrostatic Warning ......................................................................................................... 2-2

Section 3Power Up....................................................................................................................3-1

3.1 Power up the Board ........................................................................................................... 3-1

3.2 DevStart ............................................................................................................................. 3-1

3.3 Recovery Procedure .......................................................................................................... 3-1

3.4 Sample Code and Technical Support ................................................................................ 3-1

Section 4Evaluation Kit Hardware .............................................................................................4-1

4.1 Board Overview.................................................................................................................. 4-1

4.2 Features List ...................................................................................................................... 4-2

4.3 Function Blocks.................................................................................................................. 4-2

4.3.1 Processor............................................................................................................. 4-2

4.3.2 Memory................................................................................................................ 4-2

4.3.3 Clock Circuitry...................................................................................................... 4-3

4.3.4 Reset Circuitry ..................................................................................................... 4-4

4.3.5 Power Supply and Management.......................................................................... 4-4

4.3.6 UART ................................................................................................................... 4-5

4.3.7 USART................................................................................................................. 4-5

4.3.8 Display Interface .................................................................................................. 4-6

4.3.9 JTAG/ICE............................................................................................................. 4-8

4.3.10 Audio Interface..................................................................................................... 4-9

4.3.11 USB Device ....................................................................................................... 4-10

4.3.12 Analog Interface ................................................................................................ 4-11

4.3.13 QTouch Elements .............................................................................................. 4-12

4.3.14 User Buttons ...................................................................................................... 4-13

4.3.15 LEDs .................................................................................................................. 4-13

4.3.16 SD/MMC Card ................................................................................................... 4-14

4.3.17 ZigBEE............................................................................................................... 4-14

4.3.18 PIO Expansion................................................................................................... 4-14

SAM3S-EK Development Board User Guide 1-1


4.4 Configuration.................................................................................................................... 4-15

4.4.1 PIO Usage ......................................................................................................... 4-15

4.4.2 Jumpers ............................................................................................................. 4-19

4.4.3 Test Points......................................................................................................... 4-20

4.4.4 Solder Drops...................................................................................................... 4-20

4.4.5 Assigned PIO Lines, Disconnection Possibility.................................................. 4-20

4.5 Connectors....................................................................................................................... 4-22

4.5.1 Power Supply Connector J9 .............................................................................. 4-22

4.5.2 USART Connector J5 With RTS/CTS Handshake Support ............................... 4-22

4.5.3 UART Connector J7 .......................................................................................... 4-23

4.5.4 USB Device Connector J15 ............................................................................... 4-23

4.5.5 TFT LCD Connector J8...................................................................................... 4-24

4.5.6 JTAG Debugging Connector J6......................................................................... 4-24

4.5.7 SD/MMC - MCI Connector J3 ............................................................................ 4-27

4.5.8 Analog Connector CN1 & CN2 .......................................................................... 4-27

4.5.9 RS485 Connector J14 ....................................................................................... 4-28

4.5.10 Headphone Connector J11................................................................................ 4-28

4.5.11 ZigBEE Connector J16 ...................................................................................... 4-28

4.5.12 PIO Expansion Port C Connector J12 ............................................................... 4-29

4.5.13 PIO Expansion Port A Connector J13 .............................................................. 4-30

4.5.14 PIO Expansion Port B Connector J14 ............................................................... 4-31

Section 5Schematics .................................................................................................................5-1

5.1 Schematics......................................................................................................................... 5-1

Section 6Troubleshooting..........................................................................................................6-1

6.1 Self-Test............................................................................................................................. 6-1

6.2 Board Recovery ................................................................................................................. 6-1

Section 7Revision History..........................................................................................................7-1

7.1 Revision History ................................................................................................................. 7-1

1-2 SAM3S-EK Development Board User Guide


Section 1

Introduction

1.1 SAM3S Evaluation Kit

The SAM3S Evaluation Kit (SAM3S-EK) enables evaluation capabilities and code development of appli-cations running on a SAM3S4C device.

1.2 User Guide

This guide focuses on the SAM3S-EK board as an evaluation platform. It is made up of 6 sections:

Section 1 includes references, applicable documents, acronyms and abbreviations.

Section 2 describes the kit contents, its main features and specifications.

Section 3 provides board specifications.

Section 4 describes the development environment.

Section 5 provides instructions to power up the SAM3S-EK and describes how to use it.

Section 6 describes the hardware resources, default jumper and switch settings, and connectors.

Section 7 provides schematics.

Section 8 describes the troubleshooting.

1.3 References and Applicable Documents

Table 1-1. References and Applicable Documents

Title Comment

SAM3S Datasheet http://www.atmel.com/dyn/products/datasheets.asp?family_id=605#2127



Section 2

Kit Contents

2.1 Deliverables

The Atmel® SAM3S-EK toolkit contains the following items:

Board:

– a SAM3S-EK board

– a universal input AC/DC power supply with US, Europe and UK plug adapters

Cables:

– one USB cable

– one serial RS232 cable

A Welcome Letter

Figure 2-1. Unpacked SAM3S-EK

Unpack and inspect the kit carefully. Contact your local Atmel distributor, should you have issues con-cerning the contents of the kit.



Kit Contents

2.2 Electrostatic Warning

The SAM3S-EK board is shipped in a protective anti-static package. The board must not be subjected to high electrostatic potentials. A grounding strap or similar protective device should be worn when han-dling the board. Avoid touching the components or any other metallic element of the board.



Section 3

Power Up

3.1 Power up the Board

Unpack the board taking care to avoid electrostatic discharge. Unpack the power supply, select the right power plug adapter corresponding to that of your country, and insert it in the power supply.

Connect the power supply DC connector to the board and plug the power supply to an AC power plug.

The board LCD should light up and display a welcome page. Then, click or touch icons displayed on the screen and enjoy the demo.

3.2 DevStart

The on-board NAND Flash contains “SAM3S-EK DevStart”.

It is stored in the “SAM3S-EK DevStart” folder on the USB Flash disk available when the SAM3S-EK is connected to a host computer and you click on the Flash Disk icon of the on-board demo.

Click the file “welcome.html” in this folder to launch SAM3S-EK DevStart.

SAM3S-EK DevStart guides you through installation processes of IAR™ EWARM, Keil MDK and GNU toolkits. Then, it gives you step-by-step instructions on how to rebuild a single example project and how to program it into the SAM3S-EK. Optionally, if you have a SAM-ICE™, instructions are also given about how to debug the code.

We recommend that you backup the “SAM3S-EK DevStart” folder on your computer before launching it.

3.3 Recovery Procedure

The DevStart ends by giving step-by-step instructions on how to recover the SAM3S-EK to the state as it was when shipped by Atmel.

Follow the instructions if you deleted the contents of the embedded Flash or the NAND Flash and want to recover from this situation.



Power Up

3.4 Sample Code and Technical Support

After boot up, you can run some sample code or your own application on the development kit. You can down load sample code and ge t techn ica l suppor t f rom Atme l webs i te http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4678

Figure 3-1. Atmel Website for AT91SAM Products



Section 4

Evaluation Kit Hardware

4.1 Board Overview

This section introduces the Atmel SAM3S Evaluation Kit design. It introduces system-level concepts, such as power distribution, memory, and interface assignments.

The SAM3S-EK board is based on the integration of an ARM® Cortex®-M3 processor with on-board NAND Flash and a set of popular peripherals. It is designed to provide a high performance processor evaluation solution with high flexibility for various kinds of applications.

Figure 4-1. SAM3S-EK Block Diagram




4.2 Features List

Here is the list of the main board components and interfaces:

SAM3S4C chip LQFP100 package with optional socket footprint

12 MHz crystal

32.768 KHz crystal

Optional SMB connector for external system clock input

NAND Flash

2.8 inch TFT color LCD display with touch panel and backlight

UART port with level shifter circuit

USART port with level shifter circuit multiplexed with RS485 port with level shifter circuit

Microphone input and mono/stereo headphone jack output

SD/MMC interface

Reset button: NRST

User buttons: Left and Right

QTouch® buttons: Up, Down, Left, Right, Valid and Slider

Full Speed USB device port

JTAG/ICE port

On-board power regulation

Two user LEDs

Power LED

BNC connector for ADC input

BNC connector for DAC output

User potentiometer connected to the ADC input

ZigBEE connector

2x32 bit PIO connection interfaces (PIOA, PIOC) and 1x16 bit PIO connection interface (PIOB)

4.3 Function Blocks

4.3.1 Processor

The SAM3S-EK is equipped with a SAM3S4C device in LQFP100 package.

4.3.2 Memory

The SAM3S4 chip embeds:

256 Kbytes of embedded Flash

48 Kbytes of embedded SRAM

16 Kbytes of ROM with embedded BootLoader routines (UART, USB) and In-Application Programming functions (IAP) routines.




The SAM3S features an External Bus Interface (EBI) that permits interfacing to a broad range of external memories and virtually to any parallel peripheral. The SAM3S-EK board is equipped with a memory device connected to the SAM3 EBI:

One NAND Flash MT29F2G08AADWP.

Figure 4-2. NAND Flash

NCS0 chip select signal is used for NAND Flash chip selection. Furthermore, a dedicated jumper can disconnect it from the on-board memories, thereby letting NCS0 free for other custom purpose.

4.3.3 Clock Circuitry

The clock generator of a SAM3S microcontroller is made up of:

A Low Power 32.768 Hz Slow Clock Oscillator with bypass mode.

A 3 to 20 MHz Crystal Oscillator, which can be bypassed (12 MHz needed in case of USB).

A factory programmed fast internal RC Oscillator. 3 output frequencies can be selected: 4 (default value), 8 or 12 MHz.

A 60 to 130 MHz PLL (PLLB) providing a clock for the USB Full Speed Controller.

A 60 to 130 MHz programmable PLL (PLLA), capable to provide the clock MCK to the processor and to the peripherals. The input frequency of PLLA is from 7.5 and 20 MHz.

The SAM3S-EK board is equipped with one 12 MHz crystal, optional Piezoelectric Ceramic Resonator 12 Mhz (Murata ref. CSTCE12M0G15L99-R0), one 32.768 Hz crystal and an external clock input con-nector (optional, not populated by default).

Figure 4-3. External Clock Source

MT29F2G08AADWP

PC7PC6PC5PC4PC3PC2PC1PC0

PC10PC9PC16PC17

PC18

PC14

+3V3

DGND

+3V3

DGND

+3V3

+3V3

PC[0..31]{3,5,7}

MN3MN3

WE18

N.C66

VCC37

CE9

RE8

N.C1120

WP19

N.C55

N.C11

N.C22

N.C33

N.C44

N.C1221

N.C1322

N.C1423

N.C1524

R/B7

N.C1726

N.C1827N.C1928

I/O029

N.C2134N.C2235

VSS36

PRE38N.C2339

VCC12

VSS13

ALE17

N.C811 N.C710

N.C914

N.C1015

CLE16

N.C1625

N.C2033

I/O130

I/O332I/O231

N.C2747

N.C2646

N.C2545

I/O744I/O643I/O542I/O441

N.C2440

N.C2848

C27100nFC27100nF

R1547KR1547K

R21 47KR21 47K

R1647KR1647K

C291uFC291uF

R19 0RR19 0R

R22DNPR22DNP

JP9JP9

C28100nFC28100nF

NOT POPULATED

DNP

XOUT32

XIN32

XIN32XOUT32

PA7PA8

XIN

XOUT

PB8

PB9

DGND

DGND

DGND

DGNDDGND

R3 DNPR3 DNP

R6 DNPR6 DNP

R9 DNPR9 DNP

R1 DNPR1 DNPC320pFC320pF

R4 0RR4 0R

C420pFC420pF

R249.9R 1%R249.9R 1%

Y1Y1

12

3

R8 DNPR8 DNPR7 DNPR7 DNP

AT91SAM3S

MN1

AT91SAM3S

MN1

PA7_RTS0_PWMH349

PA8_CTS0_AD12BTRG48PB8_XOUT

96

PB9_XIN97

R110RR110R

Y2 12MHzY2 12MHz

C1 20pFC1 20pF

R10 DNPR10 DNP

Y332.768KHzY332.768KHz

12

3

R5 0RR5 0R

R120RR120R

J1J1

12 3

54

C2 20pFC2 20pF




The SAM3S chip internally generates the following clocks:

SLCK, the Slow Clock, which is the only permanent clock of the system

MAINCK, the output of the Main Clock Oscillator selection: either a Crystal Oscillator or a 4/8/12 MHz Fast RC Oscillator

PLLACK, the output of the Divider and 60 to 130 MHz programmable PLL (PLLA)

PLLBCK, the output of the Divider and 60 to 130 MHz programmable PLL (PLLB)

4.3.4 Reset Circuitry

On-board NRST button BP1 provides an external reset control of the SAM3S.

The NRST pin is bidirectional. It is handled by the on-chip reset controller. It can be driven low to provide a reset signal out to the external components. Conversely, it can be asserted low from the outside to reset the microcontroller Core and the peripherals. The NRST pin integrates a permanent pull-up resistor of about 100 kOhm to VDDIO.

On the SAM3S-EK board, the NRST signal is connected to the LCD module and JTAG port.

Note: At power-on, the NRST signal is asserted with a default duration of 2 clock cycles. That duration may not be sufficient to correctly reset any other system or board devices connected to that signal. First, in your custom application, you need to check for these devices' datasheets about reset duration requirements. Then, you need to set an appropriate configuration in the NRST Manager. This is done through the ERSTL field in the RSTC_MR register. The NRST duration is thereby configurable between 60 µs and 2 s, whether it is subse-quently activated by a software reset or a user reset. Refer to the SAM3S datasheet for in depth information.

4.3.5 Power Supply and Management

The SAM3S-EK board is supplied with an external 5V DC block through input J9. It is protected by a PolyZen diode MN9 and an LC combinatory filter MN10. The PolyZen is used in the event of an incorrect power supply connection.

The adjustable LDO regulator MN12 is used for the 3.3V rail main supply. It powers all the 3.3V compo-nents on the board.

Figure 4-4. Power Block

The SAM3S4/2/1 product series has different types of power supply pins:

VDDIN pin: Power for the internal voltage regulator, ADC, DAC, and analog comparator power supplies. The voltage ranges from 1.8V to 3.6V.

DGND

+5V

+5V +3V3

C75100uF

+ C75100uF

C6522uF

+ C6522uF

C64100nFC64100nF

MN10BNX002-01MN10BNX002-01

SV1

SG2

CV3

CG14

CG25

CG36

C76100nFC76100nF

C6622uF

+ C6622uF

MN9ZEN056V130A24LSMN9ZEN056V130A24LS

1

2

3

R92102K 1%R92102K 1%

MN12MIC29152WUMicrel's 1.5A LDO, TO263-5


VIN2

VOUT4

SD1

GN

D1

3

ADJ5

GN

D2

6

R89169K 1%R89169K 1%

J9MP179P 2.1mmJ9MP179P 2.1mm

12

3




VDDIO pins: Power for the Peripherals I/O lines. The voltage ranges from 1.62V to 3.6V.

VDDOUT pin: Output of the internal voltage regulator.

VDDCORE pins: Power for the core, including the processor, embedded memories and peripherals. The voltage ranges from 1.62V to 1.95V.

VDDPLL pin: Power for the PLL A, PLL B and 12 MHz oscillator. The voltage ranges from 1.62V to 1.95V.

Note: VDDPLL should be decoupled and filtered from VDDCORE.

4.3.6 UART

The Universal Asynchronous Receiver Transmitter features a two-pin UART that can be used for com-munication and trace purposes. It offers an ideal channel for in-situ programming solutions. This UART is associated with two PDC channels to reduce the processor time on packet handling.

This two-pin UART (TXD and RXD only) is buffered through an RS232 Transceiver MN6 and brought to the DB9 male connector J7.

Figure 4-5. UART

4.3.7 USART

The Universal Synchronous/Asynchronous Receiver Transmitter (USART) provides one full duplex uni-versal synchronous/asynchronous serial link. The data frame format is extensively configurable (data length, parity, number of stop bits) to support a broad range of serial communication standards. The USART is also associated with PDC channels for TX/RX data access.

Note: For design optimization purposes, both transmitters have been implemented on the same PIO lines, that is PA21, 22, 23, 24 25.

To avoid any electrical conflict, the RS485 transceiver is isolated from the receiving line PA21.

Should you need to implement an RS485 channel in place of the RS232, follow the procedure below:

1. make sure your software will permanently set PA23 to a high level - this will permanently disable the RS232 receiver.

2. solder a shunt resistor in place of R25 (a solder drop will do).

+3V3

DGNDDGND

+3V3 +3V3

FGND

PA10PA9

C39100nFC39100nF

C40100nFC40100nF

TP5SMDTP5SMD

J7J7

5

4

3

2

1

9

8

7

6

10 11

R46100KR46100K

C38100nFC38100nF

TP6SMDTP6SMD

C41100nFC41100nF

R47 0RR47 0R

R48 0RR48 0R

C42100nFC42100nF

MN6MAX3232CSEMN6MAX3232CSE

T1IN11

T2IN10 R1OUT12

R2OUT9

T1OUT14

T2OUT7R1IN13

R2IN8

V+2

C1+1

C1-3

C2+4

C2-5

V-6

VCC16

GND15

R45100KR45100K




4.3.7.1 RS232

SAM3S-EK connects the USART1 bus (including TXD, RXD, RTS, CTS handshake signal controls and EN command) to the DB9 male connector J5 through the RS232 Transceiver MN5.

Figure 4-6. USART

4.3.7.2 RS485

As noticed above, the USART1 is shared with the RS485 port, connected to the transceiver MN4, con-nected to the 3-point connector J4. The design includes selectable jumpers for RS485 bus termination resistors selection (JP10, JP11, JP12).

Figure 4-7. RS485

4.3.8 Display Interface

The SAM3S-EK carries a TFT Transmissive LCD module with touch panel, FTM280C34D. Its integrated driver IC is ILI9325. The LCD display area is 2.8 inches diagonally measured, with a native resolution of 240 x 320 dots.

4.3.8.1 LCD Module

The LCD module gets reset from the NRST signal. As explained, this NRST is shared with the JTAG port and the push-button BP1. The LCD chip select signal is connected to NCS1; the jumper JP13 can dis-connect it so that this PIO line is available for other custom usage.

The SAM3S communicates with the LCD through PIOC where an 8-bit parallel “8080-like” protocol data bus has to be implemented by software.

PA25PA24PA21PA22

PA23

FGND

DGND

+3V3

DGND

+3V3

+3V3

DGND

R36 0RR36 0R

C34100nFC34100nF

C35100nFC35100nFC36

100nFC36100nF

R3247KR3247K

MN5ADM3312EARUMN5ADM3312EARU

C1+6

C1-20

C2+2

C2-4

C3+24

C3-22

VCC3

V+1

V-21

GND23

SD19

EN5

T1IN7

T1OUT18

R1IN15

R1OUT10

T2IN8

T2OUT17

R2IN14

R2OUT11

T3IN9

T3OUT16

R3IN13

R3OUT12

R38 0RR38 0R

C314.7uFC314.7uF

C32100nFC32100nF

R35 0RR35 0R

C37100nFC37100nF

C33100nFC33100nF

J5J5

5

4

3

2

1

9

8

7

6

10 11

R34 0RR34 0RR33 0RR33 0R

R31 0RR31 0R

R37 47KR37 47K

PA22

PA24

PA25

PA21

PA23

DGND

+3V3

+3V3 +3V3

DGND

FGND

MN4ADM3485ARZMN4ADM3485ARZ

RO1

RE2

DE3

DI4

VCC8

GND5

A6

B7

R28 0RR28 0R

R30DNPR30DNP

J4J41

2

3

R29120RR29120R

C30100nFC30100nFR26 0RR26 0R

JP11JP11 JP12JP12

JP10JP10

R27 0RR27 0R

R23DNPR23DNP

R25 DNPR25 DNP

R24DNPR24DNP




Figure 4-8. LCD Block

4.3.8.2 Backlight Control

The LCD backlight is made of four integrated white chip-LEDs arranged in parallel. These are driven by an AAT3155 charge pump, MN8.The AAT3155 is controlled by the SAM3S through a single PIO line PC13 interface; the 0 Ohm resistor R68 is mounted in series on this line, which permits to use it for other custom purposes. In that case, the pull-up resistor R64 maintains the charge pump permanently enabled by default.

On the anode drive line, a 0 Ohm resistor R59 is implemented in series for an optional current limitation.

Figure 4-9. Backlight Control

NOT POPULATED

LCD_DB10LCD_DB11LCD_DB12LCD_DB13LCD_DB14LCD_DB15LCD_DB16LCD_DB17

2.8" 320x240 TFT LCD DISPLAY

X_RIGHT

X_LEFTY_UP

Y_DOWN

X_LEFTX_RIGHTY_DOWNY_UPLED_K4LED_K3LED_K2LED_K1

LED_A


NRSTPC15

PC19

PC11PC8

PC13


LCD_DB9LCD_DB8LCD_DB7LCD_DB6LCD_DB5LCD_DB4LCD_DB3LCD_DB2LCD_DB1LCD_DB0

LCD_DB0

LCD_DB4

LCD_DB9

LCD_DB5LCD_DB7LCD_DB6LCD_DB8LCD_DB1LCD_DB3LCD_DB2

PC23PC22

DGND

DGND

+3V3

DGND

+3V3

DGND

DGND

NRST

PC[0..31]

D1PACDN044Y5RTVS, SOT23-5


1

2

345

R5610KR5610K

JP13JP13

RA3DNPRA3DNP

1234 5

678

R61 DNPR61 DNP

+ C4310uF

+ C4310uF

PINsonBOT

PIN 39

PIN 1

FTM280C34D-8bit

PINsonBOT

PIN 39

PIN 1

FTM280C34D-8bit

C44100nFC44100nF

J8FH26-39S-0.3SHWJ8FH26-39S-0.3SHW

VDD1

DB172

DB163

DB154

DB145

DB136

DB127

DB118

DB109

DB910

DB811

DB712

DB613

DB514

DB415

DB316

DB217

DB118

DB019

VDD20

RD21

WR22

RS23

CS24

RESET25

IM026

IM127

GND28

LED-A29

LEDK130

LEDK231

LEDK332

LEDK433

Y+34

Y-35

X+36

X-37

NC38

GND39

R584.7KR584.7K

C45100nFC45100nF

R63 DNPR63 DNP

RA2DNPRA2DNP

1234 5

678

R59 0RR59 0R

R4947KR4947K

LED_A

LED_K1LED_K2LED_K3LED_K4

PC13

+3V3

+3V3

DGND

DGND

R680RR680R

C574.7uFC574.7uF

C551uFC551uF

MN8AAT3155ITP-T1MN8AAT3155ITP-T1

C1+10

C1-9

EN/SET11

C2+7

C2-6

OUTCP8

IN5

GND4

D13

D22

D31

D412

R6447KR6447K

B1BN03K314S300RB1BN03K314S300R C56

1uFC561uF

C541uFC541uF TP7

SMDTP7SMD




4.3.8.3 Touch Screen Interface

The LCD module integrates a 4-wire touch panel controlled by MN7 (ADS7843) which is a slave device on the SAM3S SPI bus. The controller sends back the information about the X and Y positions, as well as a measurement for the pressure applied to the touch panel. The touch panel can be used with either a stylus or a finger.

The ADS7843 touch panel controller connects to the SPI0 interface via the NPCS0 control signal. Two interrupt signals are connected and provide events information back to the microcontroller: PenIrq and Busy.

Note: PenIrq (PA16) is shared with ZigBEE signal IRQ0. Busy (PA17) is shared with ZigBEE signal IRQ1. Therefore, if using a ZigBEE interface in concurrence with the TouchScreen controller, take care not to have both drivers enabled at the same time on either PA16 or PA17.

For that purpose, 0 Ohm resistors have been implemented on these PIO lines in order to disconnect either end driver from the other:

On the touch panel controller side, R67 and R69.

On ZigBEE side, R117 and R120.

for further information, refer to the “Schematics” section.

Touch ADC auxiliary inputs IN3/IN4 of the ADS7843 are connected to test point (TP8, TP9) for optional function extension.

Figure 4-10. Touch Panel Control

4.3.9 JTAG/ICE

A standard 20-pin JTAG/ICE connector is implemented on the SAM3S-EK for the connection of a com-patible ARM JTAG emulator interface, such as the SAM-ICE from Segger.

Notes: 1. The NRST signal is connected to BP1 system button and is also used to reset the LCD module. The 0 ohm resistor R44 may be removed in order to isolate the JTAG port from this system reset signal.

2. The TDO pin is in input mode with the pull-up resistor disabled when the Cortex M3 is not in debug mode. To avoid current consumption on VDDIO and/or VDDCORE due to floating input, the internal pull-up resistor corresponding to this PIO line must be enabled.

PA12PA13PA14

PA17

PA11

X_RIGHTY_UPX_LEFTY_DOWN

PA16

DGND

+3V3

+3V3

+3V3

AGND_TP AGND_TP

R62100KR62100K

R70 0RR70 0R

R67 0RR67 0R

R66 0RR66 0R R65100KR65100K

C60100nFC60100nF

C58100nFC58100nF

L210uH/100mAL210uH/100mA

R72100KR72100K

R69 0RR69 0R

C614.7uFC614.7uF

TP9SMDTP9SMD

R711RR711R

C59100nFC59100nF

TP8SMDTP8SMD

R740RR740R

R73100KR73100K

MN7ADS7843EMN7ADS7843E

XP2

YP3

XM4

YM5

DCLK16

DIN14

DOUT12

CS15

BUSY13

PENIRQ11

VREF9

VCC11

VCC210

GND6

IN37

IN48




Figure 4-11. JTAG Interface

4.3.10 Audio Interface

The SAM3S–EK board supports both audio recording and playback.

The audio volume can be adjusted using the potentiometer RV1, and the microphone amplifier gain can be adjusted via jumpers (fixed gain of 24 or 26 dB).

4.3.10.1 Microphone Input

The embedded microphone is connected to an audio pre-amplifier using the TS922 operational amplifier (MN11). The gain is set by using JP14 and JP15 jumpers; both must be set or removed at the same time.

By modifying the jumper positions, you can select each of the following gain values:

20 dB (default setting, both JP14 and JP15 are off)

26 dB (both JP14 and JP15 are on).

Note:

3. The TB1 series 0 Ohm resistor is a reservation for future impedance adaptation facility. Under specific amplifier settings conditions, this enables the easy insertion of a capaci-tor or any other bipolar device on the audio path. On the other hand, R83 is a default 0 Ohm resistor that enables the disconnection of PB0 from the audio input path for cus-tom usage.

4. The audio pre-amplifier MN11 is powered by a dedicated low dropout regulator MIC5219-3.3 (MN14).

+3V3

DGND

NRSTPB5

PB7PB6PB4

R43100KR43100K

R41100KR41100K

R39100KR39100K

J6J6

VTref1

Vsupply2

nTRST3

GND14

TDI5

GND26

TMS7

GND38

TCK9

GND410

RTCK11

GND512

TDO13

GND614

nSRST15

GND716

DBGRQ17

GND818

DBGACK19

GND920

R42100KR42100K

R40100KR40100K

R44 0RR44 0R




Figure 4-12. Microphone Input

4.3.10.2 Headphone Output

The SAM3S-EK evaluation kit supports mono/stereo audio playback driven by a TPA0223 audio ampli-fier connected to two DAC channels of the microcontroller.

The TPA0223 is a 2W mono Bridge-Tied-Load (BTL) amplifier designed to drive speakers with as low as 4 Ohm impedance. The amplifier can be reconfigured on the fly to drive two stereo Single-Ended (SE) signals into head phones.

Figure 4-13. Headphone Output

JP14 and JP15 should be setor removed together

AGND

AGND AGND

AVDD

AGND AGND

AGND

AVDD

AGND

AGND

DGND

AVDD

AGND

VCC33

PB0

C721nFC721nF

R801KR801K

R90100KR90100K

C671uFC671uF

C74100nFC74100nF

R841KR841K

R8747KR8747K

R791KR791K

R781KR781K

R77470RR77470R

B2 BN03K314S300RB2 BN03K314S300R

C7122nFC7122nF

R830RR830R

R88470RR88470R

TB10RTB10R

C6322uFC6322uF

C62100pFC62100pF

C774.7uFC774.7uF

R851KR851K

C7322uFC7322uF

R75 47KR75 47K

MN11TS922MN11TS922

IN1-2

IN1+3

OUT27

IN2-6

IN2+5

GND4

VCC8

OUT11

JP14JP14

R76 47KR76 47K

R93100KR93100K

R910RR910R

JP15JP15

C691nFC691nF

R8647KR8647K

R821KR821K

C681uFC681uF

MIC1SVB6050MIC1SVB6050

12

R81100RR81100R

AUDIO_OUTL

AUDIO_OUTL

AGND

VDD_AMP

AGND

AGND

AGND

AGND

+5V

AGNDDGND

VDD_AMP

AGND

PB14 {3,7}

PB13

JP19JP19

C82100nFC82100nF

C88 0.47uFC88 0.47uF

+C81 220uF+C81 220uF

R103 100KR103 100K

R95 1KR95 1K

C871uFC871uF

R99 47KR99 47K

JP20JP20

R98 33KR98 33K

C86 0.47uFC86 0.47uF

MN13TPA0223DGQMN13TPA0223DGQ

VDD3

RIN5

MONO-IN1

LIN9

LO/MO-10

RO/MO+6

ST/MN7

SHUTD0WN2

BYPASS4

GND8

PA

D11

+ C8010uF

+ C8010uF

C85 0.47uFC85 0.47uF R100 33KR100 33K

R105 33KR105 33K

SD1SD1

1 2

+C83 220uF+C83 220uF

J11EARJACKJ11EARJACK5

4321R97 1KR97 1K

R102 100KR102 100KTP12SMDTP12SMD

C84 0.47uFC84 0.47uF

SD2SD2

1 2

B3BN03K314S300R

B3BN03K314S300R

JP17JP17

J10J1012

R104 47KR104 47K

R101 100KR101 100K

C791uFC791uF

( to DAC outputconnector )




Using a readily available 1/8-in. (3,5 mm) stereo headphone jack, the control switch is closed when no plug is inserted. When closed, a 100-kOhm/1-kOhm divider pulls the ST/MN input low. When a jack plug is inserted, the 1-kOhm resistor is disconnected and the ST/MN input is pulled high. The mono speaker (J10 connector) is also physically disconnected from the RO/MO+ output so that no sound is heard from the speaker while the headphones are inserted.

4.3.11 USB Device

The SAM3S UDP port is compliant with the Universal Serial Bus (USB) rev 2.0 Full Speed device speci-fication. J15 is a micro B-type receptacle for USB device.

Both 27-Ohm resistors R114 and R116 build up a 90-Ohm differential impedance together with the (embedded) 6-Ohm output impedance of the SAM3S full speed channel drivers.

R110 and R112 build up a divider bridge from VBUS +5V to implement plug-in detection (5V level gets lowered to a PIO compatible 3.3V level) through PC21.

Figure 4-14. USB

4.3.12 Analog Interface

4.3.12.1 Analog Reference

The 2V5 voltage reference is based on an LM4040 (Precision Micropower Shunt Voltage Reference).

This ADVREF level can be set as 2.5V or 3.3V via the jumper JP2.

Figure 4-15. Analog Vref

PC21

PB10

PB11

DGND

DGND FGND

FGND

C9410pFC9410pF

R110 47KR110 47K

R116 27RR116 27R

5V D- D+ ID G

J15USB Micro B

5V D- D+ ID G

J15USB Micro B

1 2 3 4

7

5

689

RV1V5.5MLA0603RV1V5.5MLA0603


R112 68KR112 68K

R114 27RR114 27R

ADVREF

DGND

DGND

VCC33

+5V

JP2JP2

1

2

3C5100nFC5100nF

AT91SAM3SAT91SAM3SADVREF

1 R132.2KR132.2K

MN2LM4040-2.5

MN2LM4040-2.5




4.3.12.2 Analog Input

The BNC connector CN1 is connected to the ADC port PB1 as an external analog input. An on-board 50-Ohm resistor termination can be applied by closing jumper JP16. A low pass filter can be implemented for the BNC connector CN1 by replacing R94 and C78 with custom resistor and capacitor values, depending on your application requirements.

A 10-KOhm potentiometer (VR1) is also connected to this channel to implement an easy access to ADC programming and debugging (or implement an analog user control like display brightness, volume, etc.).

Either of these two functions can be selected by jumper JP18.

Figure 4-16. ADC Input

4.3.12.3 Analog Output

The BNC connector CN2 is connected to the DAC port PB13 and provides an external analog output. An on-board 50-Ohm resistor termination can be enabled by closing jumper JP21. A filter can be imple-mented on this output channel by replacing R106 and C90 with appropriate resistor and capacitor values, depending on the application requirements.

Figure 4-17. DAC Output

4.3.13 QTouch Elements

QTouch keys consist in a series of sensors formed by the association of a copper area and the capaci-tive effect of human fingers approaching it.

4.3.13.1 Keys

The SAM3S-EK implements five individual capacitive touch keys (UP, DOWN, RIGHT, LEFT and VALID) using five pairs of PIO.

Potentiometer

AD12B5

ADC

DGND

DGND

VCC33

PB1JP18JP18

1

2

3

CN1BNCCN1BNC

1234

5

JP16JP16

VR110KVR110K

13

2

R9649.9R 1%R9649.9R 1%

C8910nFC8910nF

R940RR940R

C7810nFC7810nF

SOLDER DROP 2 pins open.Normal

DAC01

DAC

AUDIO_OUTL

DGND

PB14

C90 2.2uFC90 2.2uFJP21JP21

R10949.9R 1%R10949.9R 1%

SD1SD1

1 2R1060RR1060R

CN2BNCCN2BNC

1234

5

SD2SD2

1 2




Figure 4-18. QST Keys

4.3.13.2 Slider

A group of channels forms a Slider. A Slider is composed of three channels for a QTouch acquisition method using three pairs of PIO. Such a sensor is used to detect a linear finger displacement on a sen-sitive area. A typical implementation is volume control.

Figure 4-19. QT_Slider

4.3.14 User Buttons

There are two mechanical user buttons on the SAM3S-EK, which are connected to PIO lines and defined to be "left" and "right" buttons by default.

In addition, a mechanical button controls the system reset, signal NRST.

Figure 4-20. System Buttons

PC25

PC24

PC31

PC30

PC29

PC28

PC23

PC22

PC27

PC26

R53 1KR53 1K

C4922nFC4922nF

R60 1KR60 1K

R51 1KR51 1K

R57 1KR57 1K

C5122nFC5122nF

R55 1KR55 1K

C4722nFC4722nF

K1DNPK1DNP

C5322nFC5322nF

C5222nFC5222nF

PA1

PA0

PA3

PA2

PA5

PA4

R54 1KR54 1K

R50 1KR50 1K

C5022nFC5022nF

C4622nFC4622nF

S1DNPS1DNP

SL

SM

SR

SR

R52 1KR52 1K

C4822nFC4822nF

PB3

PC12

DGND

NRST

JP26JP26

BP1BP11

423

BP3BP31

423

JP25JP25BP2BP21

423




4.3.15 LEDs

There are three LEDs on the SAM3S-EK board:

A blue LED (D2) and a green LED (D3), which are user defined and controlled by the GPIO.

A red LED (D4), which is a power LED indicating that the 3.3V power rail is active. It is also controlled by the GPIO and can be treated as a user LED as well. The only difference with the two others is that it is controlled through a MOS transistor. By default, the PIO line is disabled; a pull-up resistor controls the MOS to light the LED when the power is ON).

Figure 4-21. LEDs

4.3.16 SD/MMC Card

The SAM3S EK has a high-speed 4-bit multimedia MMC interface, which is connected to a 4-bit SD/MMC micro card slot featuring a card detection switch.

Figure 4-22. SD Card

4.3.17 ZigBEE

SAM3S has a 10-pin male connector for the RZ600 ZigBEE module.

Note: 0 Ohm resistors have been implemented in series with the PIO lines that are used else-where in the design, thereby enabling their individual disconnection, should a conflict occur in your application.

PA19

PA20

PC20

+3V3

DGND

D4 Red-ledD4 Red-led

R113220RR113220R

Q1IRLML2502

Q1IRLML2502

1

32

R115 100KR115 100K

D3 Green-ledD3 Green-led

R117220RR117220R

R111220RR111220R D2 Blue-ledD2 Blue-led

PA28

PA29

PA6

PA26PA27

PA30PA31

DGND

+3V3

DGND

+ C2510uF

+ C2510uF

RA168KX4RA168KX4

12345 6 7 8

R1810KR1810K

R1710KR1710K

C26100nFC26100nF

J3TF01AJ3TF01A

DAT21

DAT32

CMD3

VCC4

CLK5

VSS6

DAT07

DAT18

GND10

CD9

Sh111

Sh212

Sh313

R20 0RR20 0R




Figure 4-23. ZigBEE Interface

4.3.18 PIO Expansion

The SAM3S product features three PIO controllers, PIOA, PIOB and PIOC, which are multiplexed with the I/O lines of the embedded peripherals. Each PIO Controller controls up to 32 lines (16 for PIOB). Expansion ports J12, J13 and J14 provide PIO lines access for customer defined usage.

Figure 4-24. PIO Expansion

Note: All PIO lines are available on these expansion connectors, except those that are used for the QTouch elements.

IRQ0_ZBEEIRQ1_ZBEESPIO_NPCS2#MISO

MOSISPCK

SLP_TRZB_RSTN

PA13

PA16

PB2PA12 PA14

PA15PA17PA18

DGND

+3V3

C9518pFC9518pF

R120 0RR120 0RJ16J16

1 23 45 67 89 10

R119 0RR119 0RR118 0RR118 0R

JP27JP27R121 0RR121 0R

C962.2nFC962.2nF

C972.2uFC972.2uF

PC0PC1PC2PC3PC4PC5PC6PC7PC8PC9PC10PC11PC12PC13PC14PC15

PC19

PC17

PC21

PC16

PC20

PC18

PB6

PB1

PB3

PB7

PB4

PB0

PB5

PB2

PB14

PB9

PB11PB12

PB8

PB13

PB10

PA6

PA9

PA11

PA14PA13

PA7PA8

PA12

PA10

PA15

PA22

PA27

PA23

PA29PA30

PA25

PA21

PA28

PA24

PA26

PA31

PA16PA17PA18PA19PA20

+3V3 +3V3 +3V3+3V3

DGND DGND

DGND

DGND DGND

+3V3 +3V3

DGND

+5V +3V3 +5V +5V+3V3 +3V3

PC[0..31]

PB[0..14]

PA[0..31]

JP23JP23

1

2

3

JP22JP22

1

2

3

J14J141 23 45 67 89 10

11 1213 1415 1617 1819 2021 2223 24

J13J131 23 45 67 89 10

11 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 40

J12J121 23 45 67 89 10

11 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 40

JP24JP24

1

2

3




4.4 Configuration

This section describes the PIO usage, the jumpers, the test points and the solder drops of a SAM3S-EK board.

4.4.1 PIO Usage

Table 4-1. PIO Port A Pin Assignments and Signal Descriptions

NoI/O

LinePeripheral

APeripheral

BPeripheral

C Extra Function System

Function Comment

1 PA0 PWMH0 TIOA0 A17 WKUP0 QTouch slider (left) SNS

2 PA1 PWMH1 TIOB0 A18 WKUP1 QTouch slider (left) SNSK

3 PA2 PWMH2 SCK0 DATRG WKUP2 QTouch slider (middle) SNS

4 PA3 TWD0 NPCS3 QTouch slider (middle) SNSK

5 PA4 TWCK0 TCLK0 WKUP3 QTouch slider (right) SNS

6 PA5 RXD0 NPCS3 WKUP4 QTouch slider (right) SNSK

7 PA6 TXD0 PCK0 MCI card detection

8 PA7 RTS0 PWMH3 XIN32 CLK32KHz

9 PA8 CTS0AD12BTR

GWKUP5 XOUT32 CLK32KHz

10 PA9 URXD0 NPCS1 PWMFI0 WKUP6 UART receive data

11 PA10 UTXD0 NPCS2 UART transmit data

12 PA11 NPCS0 PWMH0 WKUP7 NPCS0# (TSC)

13 PA12 MISO PWMH1 MISO_TSC ZigBEE MISO

14 PA13 MOSI PWMH2 MOSI_TSC ZigBEE MOSI

15 PA14 SPCK PWMH3 WKUP8 SPCK_TSC ZigBEE CLK

16 PA15 TF TIOA1 PWML3 WKUP14 / PIO_DCEN1 ZigBEE SLPTR

17 PA16 TK TIOB1 PWML2 WKUP15 / PIO_DCEN2 IRQ_TSC ZigBEE IRQ0

18 PA17 TD PCK1 PWMH3 AD0 BUSY_TSC ZigBEE IRQ1

19 PA18 RD PCK2 A14 AD1 ZigBEE RSTN

20 PA19 RK PWML0 A15 AD2/ WKUP9 Blue LED (UserLED1)

21 PA20 RF PWML1 A16 AD3/ WKUP10 Green LED (UserLED2)

22 PA21 RXD1 PCK1 AD8 USART RXD

23 PA22 TXD1 NPCS3 NCS2 AD9 USART TXD

24 PA23 SCK1 PWMH0 A19 POI_DCCLK USART transceiver enable

25 PA24 RTS1 PWMH1 A20 POI_DC0 USART RTS

26 PA25 CTS1 PWMH2 A23 POI_DC1 USART CTS

27 PA26 DCD1 TIOA2 MCDA2 POI_DC2 MCI data bit 2

28 PA27 DTR1 TIOB2 MCDA3 POI_DC3 MCI data bit 3

29 PA28 DSR1 TCLK1 MCCDA POI_DC4 MCI command




30 PA29 RI1 TCLK2 MCCK POI_DC5 MCI clock

31 PA30 PWML2 NPCS2 MCDA0 WKUP11 / POI_DC6 MCI data bit 0

32 PA31 NPCS1 PCK2 MCDA1 POI_DC7 MCI data bit 1

Table 4-1. PIO Port A Pin Assignments and Signal Descriptions (Continued)

NoI/O

LinePeripheral

APeripheral

BPeripheral


Function Comment

Table 4-2. PIO Port B Pin Assignments and Signal Descriptions

NoI/O

LinePeripheral

APeripheral

BPeripheral


Function Comment

1 PB0 PWMH0 AD4 Microphone input

2 PB1 PWMH1 AD5 Analog input

3 PB2 URXD1 NPCS2 AD6 / WKUP12 ZigBee chip select

4 PB3 UTXD1 PCK2 AD7 User push-button 1

5 PB4 TWD1 PWMH2 TDI JTAG data in

6 PB5 TWCK1 PWML0 WKUP13TDO/

TRACESWOJTAG data out

7 PB6 TMS/SWDIO JTAG test mode select

8 PB7 TCK/SWCLK JTAG clock

9 PB8 XOUT CLK12MHz

10 PB9 XIN CLK12MHz

11 PB10 DDM USB DM

12 PB11 DDP USB DP

13 PB12 PWML1 ERASE Flash erase selector

14 PB13 PWML2 PCK0 DAC0 Audio Output R

15 PB14 NPCS1 PWMH3 DAC1 Audio Output L




Table 4-3. PIO Port C Pin Assignments and Signal Descriptions

No I/O Line Peripheral APeripheral

BPeripheral

CExtra

Function System

Function Comments

1 PC0 D0 PWML0 EBI D0




5 PC4 D4 NPCS1 EBI D4

6 PC5 D5 EBI D5

7 PC6 D6 EBI D6

8 PC7 D7 EBI D7

9 PC8 NWR0/NWE TFT LCD write enable

10 PC9 NANDOE NAND Flash output enable

11 PC10 NANDWE NAND Flash write enable

12 PC11 NRD TFT LCD read enable

13 PC12 NCS3 AD12 User push-button 2

14 PC13 NWAIT PWML0 AD10 LCD backlight control

15 PC14 NCS0 NAND Flash chip select

16 PC15 NCS1 PWML1 AD11 TFT LCD chip select

17 PC16 A21/NANDALE NAND Flash ALE

18 PC17 A22/NANDCLE NAND Flash CLE

19 PC18 A0/NBS0 PWMH0 RDYBSY NAND Flash RDY/BSY

20 PC19 A1 PWMH1 TFT LCD RegSel

21 PC20 A2 PWMH2 Red LED (Power)

22 PC21 A3 PWMH3 USB Vbus detection

23 PC22 A4 PWML3 QTouch valid button SNS

24 PC23 A5 TIOA3 QTouch valid button SNSK

25 PC24 A6 TIOB3 QTouch up button SNS

26 PC25 A7 TCLK3 QTouch up button SNSK

27 PC26 A8 TIOA4 QTouch down button SNS

28 PC27 A9 TIOB4 QTouch down button SNSK

29 PC28 A10 TCLK4 AD13 QTouch left button SNS

30 PC29 A11 TIOA5 AD14 QTouch left button SNSK

31 PC30 A12 TIOB5 QTouch right button SNS

32 PC31 A13 TCLK5 QTouch right button SNSK




4.4.2 Jumpers

The SAM3S-EK board jumpers are essentially used for two main purposes: functional selection or cur-rent measurement. Details are given below.

Table 4-4. Jumpers Setting

Designation Label Default Setting Feature

JP1 JTAG OPEN Close to select the JTAG boundary scan of the SAM3S

JP2 ADVREF 1-2Analog reference voltage selection between 3.3V (close 1-2) and 2.5V (close 2-3)

JP3 ERASE OPEN Close to reinitialize the Flash contents and some of its NVM bits.

JP4 TESTNot populated

(OPEN)Close for manufacturing test or fast programming mode

JP5 VDDPLL CLOSE Access for current measurement on VDDPLL

JP6 VDDIO CLOSE Access for current measurement on VDDIO

JP7 VDDIN CLOSE Access for current measurement on VDDIN

JP8 VDDCORE CLOSE Access for current measurement on VDDCORE

JP9 CE FLASH CLOSE NCS0 enable NAND Flash chip select

JP10 RS485 OPEN Maintain differential impedance for RS485 interface

JP11 RS485 CLOSE Maintain impedance matching for RS485 interface

JP12 RS485 OPEN Maintain differential impedance for RS485 interface

JP13 CS CLOSE NCS1 chip select LCD

JP14 - JP15 MIC GAIN0CLOSE (both) 20db

OPEN (both) 26dbClose both to lower gain stage on microphone input.

JP16 ADC input OPEN Close for impedance matching on ADC BNC port

JP17 – JP19 MIC Gain stage Close to mux RIN/LIN into MONO-IN path within audio PA

JP18 SELECT ADC INP1-2

2-3

ADC input potentiometer

ADC input BNC

JP20 MONO/STEREO CLOSE Close to fix in mono speaker, no matter the stereo plug state

JP21 DAC output OPEN Close for impedance matching on DAC BNC port

JP22PIO expansion J12

voltage supply2-3 Set to 3.3V (position 1-2 sets to 5V)





JP25 BP2 CLOSE Open to disconnect and free PB3 for custom usage

JP26 BP3 CLOSE Open to disconnect and free PC12 for custom usage

JP27 ZIGBEE CLOSEPower supply connection/disconnection for the ZigBEE module

May also be used as a current measurement point




4.4.3 Test Points

Some test points have been placed on the SAM3S-EK board for the verification of important signals.

4.4.4 Solder Drops

There are two solder drops designed on the SAM3S-EK for isolation.

4.4.5 Assigned PIO Lines, Disconnection Possibility

As pointed out in some previous interface description, 0 Ohm resistors have been inserted on the path of the receiver PIO lines of the SAM3S-EK. These are the PIO lines connected to an external driver on the board. The 0 Ohm resistors allow disconnecting each of these for custom usage (through PIO expansion connectors for example). This feature gives the user an added level of versatility for prototyping a system of his own. See the table below.

Table 4-5. Audio Input Configuration

JP17 JP19 MONO-STEREO INPUT

OFF OFF PIN test point (TP12)

OFF ON Left-in only

ON OFF Right-in only

ON ON Sum of Left-in and Right-in

Table 4-6. Test Points

Designation Part Description

TP1 Ring Hook GND

TP2 Ring Hook GND

TP3 Ring Hook GND

TP4 Ring Hook GND

TP5 Pad UART TXD

TP6 Pad UART RXD

TP7 Pad LCD Backlight driver anode

TP8 Pad Aux ADC input for Touch Screen controller

TP9 Pad Aux ADC input for Touch Screen controller

TP10 Ring Hook +5V

TP11 Ring Hook +3V3

TP12 Pad Optional Audio PA input

Table 4-7. Solder Drops

Designation Default Setting Feature

SD1 OPEN Isolation of DAC output from shared channel (PB14)

SD2 CLOSE Connects PB14 to the AUDIO_OUTL channel




Table 4-8. Disconnecting Possibility

Designation Default Assignment PIO

R19 0R PC18, RDY/BSY on NAND Flash

R20 0R PA29

R22 DNP Optional write protection on NAND Flash

R25 0R PA21

R26 0R PA25

R27 0R PA24

R28 0R PA22

R31 0R PA23

R33 0R PA22

R34 0R PA21

R35 0R PA24

R36 0R PA25

R44 0R NRST

R47 0R PA9

R48 0R R2OUT/MN5

R59 0R LCD backlight LED anode

R66 0R PA11

R67 0R PA5

R68 0R PC13

R69 0R PA4

R70 0R Vref TSC

R118 0R PA3 ZB_RSTN

R119 0R PA5 IRQ1_ZBEE

R120 0R PA4 IRQ0_ZBEE

R121 0R PA6 SLP_TR

Table 4-9. Default Not Populated Parts

Reference Function

J1, R1 External clock resource input

Y1, R3, R7 Backup 12 MHz crystal

R6, R8 Isolation on 12 MHZ clock source and GPIO expansion

R9, R10 Isolation on 32 KHz clock source and GPIO expansion

R22 Optional write protection NAND Flash

R23 Optional pull-up for open drain output or equivalent device

R24, R30 Differential impedance matching for RS485 cable




4.5 Connectors

4.5.1 Power Supply Connector J9

The SAM3S-EK evaluation board can be powered from a 5VDC power supply connected to the external power supply jack J9. The positive pole is the center pin.

Figure 4-25. Power Supply Connector J9

4.5.2 USART Connector J5 With RTS/CTS Handshake Support

Figure 4-26. Male RS232/USART Connector J5

D1 Optional ESD protection for LCD touch panel

R61, R63, RA2, RA3 Optional data bus termination for LCD controller

JP4 Test mode selection for the SAM chip

J2 Optional QFP socket for the SAM3 chip

K1 Virtual component for QTouch keys set - implemented as copper areas

S1 Virtual component for QTouch slider set - implemented as copper areas

TPxx Surface-mounted test points (copper area)

Table 4-9. Default Not Populated Parts

Reference Function

Table 4-10. Power Supply Connector J9 Signal Descriptions

Pin Mnemonic Signal Description

1 Center +5vcc

2 Gnd Ground reference




4.5.3 UART Connector J7

Male RS232/UART connector J7

4.5.4 USB Device Connector J15

Figure 4-27. Micro-B USB Connector J15

Table 4-11. Serial COM1 Connector J5 Signal Descriptions


1, 4, 6, 9 NC NO CONNECTION

2 TXD TRANSMITTED DATA RS232 serial data output signal

3 RXD RECEIVED DATA RS232 serial data input signal

5 GND GROUND

7 RTS READY TO SEND Active-positive RS232 input signal

8 CTS CLEAR TO SEND Active-positive RS232 output signal

Table 4-12. Male RS232/UART Connector J7 Signal Descriptions


1, 4, 6, 7, 8, 9 NC NO CONNECTION

2 TXD TRANSMITTED DATA RS232 serial data output signal

3 RXD RECEIVED DATA RS232 serial data input signal

5 GND GROUND

Table 4-13. Micro-B USB Connector J15 Signal Descriptions


1 Vbus 5v power

2 DM Data -

3 DP Data +

4 Gnd Ground

5 Shield Shield




4.5.5 TFT LCD Connector J8

One 39-pin connector is available on the board to connect the LCD module, backlight and touch screen.

Figure 4-28. LCD Connector J8

Table 4-14. LCD Connector J8 Signal Descriptions

Pin Mnemonic Pin Mnemonic

1 3V3 2 LCD_DB17 (PC7)

3 LCD_DB16 (PC6) 4 LCD_DB15 (PC5)



9 LCD_DB10 (PC0) 10 LCD_DB09 (NC)

11 LCD_DB08 (NC) 12 LCD_DB07

13 LCD_DB06 (NC) 14 LCD_DB05 (NC)



19 LCD_DB00 (NC) 20 3V3

21 RD (PC11) 22 WR (PC8)

23 RS (PC19) 24 CS (PC15)

25 RESET 26 IM0

27 IM1 28 GND

29 LED-A 30 LED-K1

31 LED-K2 32 LED-K3

33 LED-K4 34 Y UP

35 Y DOWN 36 X RIGHT

37 X LEFT 38 NC

39 GND




4.5.6 JTAG Debugging Connector J6

This JTAG connector is a 20-way Insulation Displacement Connector (IDC) keyed box header (2.54 mm male) that mates with IDC sockets mounted on a ribbon cable. Its signal assignment is compatible with the SAM-ICE or any similar third-party interface.

Figure 4-29. JTAG/ICE Connector J6

Table 4-15. JTAG/ICE Connector J13 Signal Descriptions

Pin Mnemonic Description

1 VTref. 3.3V power

This is the target reference voltage. It is used to check if the target has power, to create the logic-level reference for the input comparators and to control the output logic levels to the target. It is normally fed from Vdd on the target board and must not have a series resistor.

2 Vsupply. 3.3V powerThis pin is not connected in SAM-ICE. It is reserved for compatibility with other equipment. Connect to Vdd or leave open in target system.

3nTRST TARGET RESET — Active-low

output signal that resets the target

JTAG Reset. Output from SAM-ICE to the Reset signal on the target JTAG port. Typically connected to nTRST on the target CPU. This pin is normally pulled HIGH on the target to avoid unintentional resets when there is no connection.

4 GND Common ground

5TDI TEST DATA INPUT — Serial data output line, sampled on the rising edge

of the TCK signal

JTAG data input of target CPU. It is recommended that this pin is pulled to a defined state on the target board. Typically connected to TDI on target CPU.

6 GND Common ground

7 TMS TEST MODE SELECT – JTAG mode set input of target CPU. This pin should be pulled up on the target. Typically connected to TMS on target CPU. Output signal that sequences the target’s JTAG state machine, sampled on the rising edge of the TCK signal.

8 GND Common ground

9TCK TEST CLOCK — Output timing

signal, for synchronizing test logic and control register access

JTAG clock signal to target CPU. It is recommended that this pin is pulled to a defined state on the target board. Typically connected to TCK on target CPU.

10 GND Common ground

11RTCK

Input Return test clock signal from the target

Some targets must synchronize the JTAG inputs to internal clocks. To assist in meeting this requirement, a returned and retimed TCK can be used to dynamically control the TCK rate. SAM-ICE supports adaptive clocking which waits for TCK changes to be echoed correctly before making further changes. Connect to RTCK if available, otherwise to GND.


13TDO JTAG TEST DATA OUTPUT —

Serial data input from the targetJTAG data output from target CPU. Typically connected to TDO on target CPU.





4.5.7 SD/MMC - MCI Connector J3

Figure 4-30. SD/MMC Connector J3

15 nSRST RESET — Active-low reset signal. Target CPU reset signal


17 RFU This pin is not connected in SAM-ICE.


19 RFU This pin is not connected in SAM-ICE.


Table 4-15. JTAG/ICE Connector J13 Signal Descriptions (Continued)

Pin Mnemonic Description

Table 4-16. SD/MMC Connector J3 Signal Descriptions


1 RSV/DAT3 2 CDA

3 GND 4 VCC

5 CLK 6 GND

7 DAT0 8 DAT1

9 DAT2 10 Card Detect

11 GND 12




4.5.8 Analog Connector CN1 & CN2

Figure 4-31. Analog Input Connector CN1 and Analog Output CN2, Bottom View

4.5.9 RS485 Connector J14

Figure 4-32. RS485 Connector J14

Table 4-17. Analog Input, Output Connector CN1, CN2 Signal Descriptions

Pin Mnemonic

1, 2, 3, 4 GND

5 Analog input PB1 for CN1 and analog output PB13 for CN2 respectively

Table 4-18. RS485 J14 Signal Descriptions

Pin Mnemonic

1 A - non-inverted RS485 signal A

2 Frame ground

3 B - non-inverted RS485 signal B




4.5.10 Headphone Connector J11

Figure 4-33. Headphone J11

4.5.11 ZigBEE Connector J16

Figure 4-34. ZigBee Connector J16

Table 4-19. Headphone J11 Signal Descriptions

Pin Mnemonic

1 AGND

2 Out left

3

4

5 Out Right

Table 4-20. Connector J16 Signal Descriptions

FunctionSignal Name Port Pin Pin Port

Signal Name Function

Option on Misc. Port Set by Zero Ohm Resistor or Solder Shunts

Reset /RST 1 2 Misc.

EEPROM for MAC address, CAP array settings and serial number

TST: test mode activation

CLKM: RF chip clock output

Interrupt Request

IRQ 3 4 SLP_TR SLP_TR

SPI chip select

/SEL 5 6 MOSI SPI MOSI

SPI MISO MISO 7 8 SCLK SPI CLK

Power Supply

GND GND 9 10 VCC VCC VCCVoltage range: 1.8v to 5.5v, typically regulated to 3.3v




4.5.12 PIO Expansion Port C Connector J12

Figure 4-35. PIO Expansion Connector J12



1 +5V or +3v3 2 +5V or +3v3

3 GND 4 GND

5 PC0 6 PC16

7 PC1 8 PC17

9 PC2 10 PC18

11 PC3 12 PC19

13 PC4 14 PC20

15 PC5 16 PC21

17 PC6 18 NC

19 PC7 20 NC

21 PC8 22 NC

23 PC9 24 NC

25 PC10 26 NC

27 PC11 28 NC

29 PC12 30 NC

31 PC13 32 NC

33 PC14 34 NC

35 PC15 36 NC

37 GND 38 GND

39 3V3 40 3V3




4.5.13 PIO Expansion Port A Connector J13




1 +5V or +3v3 2 +5V or +3v3

3 GND 4 GND

5 NC 6 PA16

7 NC 8 PA17

9 NC 10 PA18

11 NC 12 PA19

13 NC 14 PA20

15 NC 16 PA21

17 PA6 18 PA22

19 PA7 20 PA23

21 PA8 22 PA24

23 PA9 24 PA25

25 PA10 26 PA26

27 PA11 28 PA27

29 PA12 30 PA28

31 PA13 32 PA29

33 PA14 34 PA30

35 PA15 36 PA31

37 GND 38 GND

39 3V3 40 3V3




4.5.14 PIO Expansion Port B Connector J14




1 +5V or +3v3 2 +5V or +3v3

3 GND 4 GND

5 PB0 6 PB8

7 PB1 8 PB9

9 PB2 10 PB10

11 PB3 12 PB11

13 PB4 14 PB12

15 PB5 16 PB13

17 PB6 18 PB14

19 PB7 20 NC

21 GND 22 GND

23 3V3 24 3V3



Section 5

Schematics

5.1 SchematicsThis section contains the following schematics:

Block diagram

General information

Microcontroller

NAND Flash, serial interface

TFT LCD & Touch

Audio & Power Supply

USB, LEDs, push-buttons & ZigBEE



5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

USB FS Device Nand Flash

ZIGBEE IFAD/DA

Power Manage

RS232 & RS485

ATMEL Cortex M3 Processor SAM3S (LQFP100)

SAM3S-EK RevB Block Diagram

2.8 Inch TFT-LCD

User Interface (PIO PortA,B,C)

MicroSD Card

QTouch Input

Microphone

Audio PA

Reset,Debug Logic

REV DATEMODIF. DES. DATE VER.

SCALE 1/1 REV. SHEET

This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.

INIT EDITA

SAM3S-EK17B

XX-XXX-XXNL XXX

Block Diagram

XX-XXX-XXB PP 26-NOV-09




INIT EDITA

SAM3S-EK17B

XX-XXX-XXNL XXX

Block Diagram





INIT EDITA

SAM3S-EK17B

XX-XXX-XXNL XXX

Block Diagram


5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SCHEMATICS CONVENTIONS

JP20 Close to fix in mono speaker mode, no matter stereo plug state

3 J1, R1 External clock resource input

Y1, R3, R7 Backup 12MHz crystal

R6, R8 Isolation between 12MHz clock source and GPIO line

DEFAULT

OPEN

1-2

OPEN

OPEN

CLOSE

CLOSE

CLOSE

CLOSE

OPEN

R9, R10 Isolation between 32KHz clock source and GPIO line

JUMPER and SOLDERDROP

4 R22 Optional write protection on NAND flash

R23

R24, R30

D1 Optional ESD protection for LCD touch panel

R61, R62, RA2, RA3 Optional databus termination for LCD controller

5

RS485 bus termination enable

Differential impedance matching for RS485 cable

1-2

Optional pull up for open drain output on equivalent device

OPEN

OPEN

OPEN

OPEN

CLOSE

3 JP1 Close to select JTAG boundary scan

JP3 Close to reinitialize the Flash contents and some of its NVM bits

JP4 Close for manufacturing test or fast programming mode

JP5, JP6, JP7, JP8 Access for current measurement on each power rail

4 JP9 Nand Flash chip select enable

JP13

JP14, JP15 Sync close to degrade gain stage on microphone input

JP17, JP19 Close to mux RIN/LIN into MONO-IN path within audio PA

5 LCD chip select enable

PAGE REFERENCE FUNCTION

6

JP16, JP21 Close for impedance matching on AD/DA BNC port

JP18 ADC input selection between BNC port and potentiometer

7 JP22, JP23, JP24 DC voltage selection between 3.3V and 5V on PIO expansion ports

JP27 Power consumption measure for ZigBEE module

JP25 Button BP2 disable

SD1 DAC path isolation on sharing channel

SD2

2-3

CLOSE

CLOSE

A

REV DATA

REVISION HISTORY

DEFAULT NO POPULATE PARTSPAGE REFERENCE FUNCTION

Lead PB13 as AUDIO_OUTL channel

Reference guide1

Microcontroller

LCD, Touch items

2

7Audio, AD/DA, Power

PAGE

3

6

Block Diagram

IO Expansion, USB, ZigBEE, LED, Button

45

DESCRIPTION

NAND Flash, RS232, RS485, MCI, JTAG

TABLE OF CONTENTS

NOTE

2009.07 ORIGINAL RELEASED

JP11

MCI

MCI

MCI

MCI

MCI

USB_DDP

ERASE

AUDIO OUT R

AUDIO OUT L

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PB8

PB9

PB11

PB12

PB13

PB10

PB14

PIOB USAGE

MIC INPUT

ANA INPUT

ZB_NPCS2

USER_PB1

JTAG

JTAG

JTAG

JTAG

CLK_12M

CLK_12M

USB_DDM

TDWN_SNSK

TLEFT_SNS

TLEFT_SNSK

TRIGHT_SNS

TRIGHT_SNSK

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

PC8

PC9

PC10

PC11

PC12

PC13

PC14

PC15

PIOC USAGE

PC16

PC17

PC18

PC19

PC20

PC21

PC22

PC23

PC24

PC25

PC27

PC28

PC29

PC26

PC30

PC31

PIOC USAGE

D0

WR_LCD

RD_LCD

USER_PB2

EN_LCD

NAND_NCS0

NSC1_LCD

REGSEL_LCD

LED_RED(POWER)

USB_CNX

TVALID_SNS

TVALID_SNSK

TUP_SNS

TUP_SNSK

TDWN_SNS

D1

D2

D3

D4

D5

D6

D7

NAND_OE

NAND_WE

NAND_ALE

NAND_CLE

NAND_RDYBSY

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

PA8

PA9

PA10

PA11

PA12

PA13

PA14

PA15

PIOA USAGE

PA16

PA17

PA18

PA19

PA20

PA21

PA22

PA23

PA24

PA25

PA27

PA28

PA29

PA26

PA30

PA31

PIOA USAGE

TSLIDR_SL_SNS

TSLIDR_SL_SNSK

TSLIDR_SM_SNS

TSLIDR_SM_SNSK

TSLIDR_SR_SNS

TSLIDR_SR_SNSK

MCI_CD

CLK_32K

CLK_32K

RX_UART0

TX_UART0

TSC_CS

MISO

MOSI

SPCK

ZB_SLPTR

PIO MUXING

TSC_IRQ/ZB_IRQ0

TSC_BUSY/ZB_IRQ1

ZB_RSTN

LED_BLUE

LED_GREEN

RXD1

TXD1

COM1EN

RTS1

CTS1

MCI

JP26

CLOSE

Button BP3 disable

JP10, JP12 OPEN RS485 pull resistor selectors

TEST POINTPAGE REFERENCE FUNCTION

3 TP1, TP2, TP3, TP4 GND

4TP5 UART TXD

5

TP12 Optional audio PA input

TP7 LCD backlight driver anode

TP8, TP9 Aux ADC input for TSC

6

TP6 UART RXD

JP2 Analog reference voltage selection between 3.3V and 2.5V

(1) Resistance Unit: "K" is "Kohm", "R" is "Ohm¸"

(2) "DNP" means the component is not populatedby default

R25

B 2009.11 UPDATED

Disconnect RS485 Receive data from PA21




INIT EDITA

SAM3S-EK27B

XX-XXX-XXNL XXX

Describe

XX-XXX-XX26-NOV-09PPB




INIT EDITA

SAM3S-EK27B

XX-XXX-XXNL XXX

Describe





INIT EDITA

SAM3S-EK27B

XX-XXX-XXNL XXX

Describe


5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

S OCKE T

NOT POPUL ATE D

NOT POPUL ATE D

DNP

PB2

PB3

PB10

PB11

PB4PB6PB7PB5

NRST

PB1

PA0PA1PA2PA3PA4PA5PA6

PA9PA10PA11PA12PA13PA14PA15PA16PA17PA18PA19PA20PA21PA22PA23PA24PA25PA26PA27PA28PA29PA30PA31

PC

0P

C1

PC

2P

C3

PC

4P

C5

PC

6P

C7

PC

8P

C9

PC

10P

C11

PC

12P

C13

PC

14P

C15

PC

16P

C17

PC

18P

C19

PC

20P

C21

PC

22P

C23

PC

24P

C25

PC

26P

C27

PC

28P

C29

PC

30P

C31

XOUT32

PB0

JTAGSEL

XIN32

PB14

PC

12P

A23

PC23PB11

PC24

PC22PB12PB10

PA

19P

C15

PC

13P

A22

PC18JTAGSELPB5

PC20

PB6PC19

PC21PB7

PA

18P

A21

PC

26P

A17

PC

27

PB

3

PB

2P

C31

PB

0

AD

VR

EF

PC

29

PC

30P

B1

PA25PA26PC3

PA24

PC4

PC5

PA12

XIN32XOUT32

PC2PA11

PA9PC1

PA10

PA16PC7

PC6PA14PA15

PA13

PC

28P

A5

PA

4

PA

27P

C8

NR

ST

PA

28

PA

30

PA

3P

C10

PA

29

TE

ST

PC

9

PC

16

PC

11P

A2

PC

14P

A1

PA

0P

C17

PB

4P

A6

PC

0

XIN

PA

20

PC25PB13

XOUT

PA31

PB0

PB6PB7

PB9PB8

PB10PB11

PB1PB2

PB12

PB3

PB14PB13

PB4PB5

PB13

PB14PB12

ADVREF

TEST

XIN32XOUT32

PA7PA8

XIN

XOUT

PB8

PB9

PB13 {6,7}

PB14 {6,7}

VD

DC

OR

E

DGND

DGND

DGND

DGND

VDDIO

DGND

DGND

DGND VDDPLLVDDCORE DGND

VDDINVDDOUT

DGND

VD

DO

UT

VD

DIN

VDDIO

VDDCORE

VDDIO

VDDCORE VDDIO

VDDCORE

VDDIO

VDDIO

VDDPLL

DGND

VDDOUT

DGND

VDDPLL

VDDCORE

VDDIO

VDDIN

+3V3

DGND

DGND

+3V3

+3V3

DGND

DGND

VCC33

+5V

PB2{7}

PB3{7}

PB10{7}

PB11{7}

PB5{4,7}PB7{4,7}PB6{4,7}PB4{4,7}

NRST{4,5,7}

PB1{6,7}

PA[0..31] {4,5,7}

PC[0..31] {4,5,7}

PB[0..14] {4,6,7}

PB0{6,7}




INIT EDITA

SAM3S-EK37B

XX-XXX-XXNL XXX

Microcontroller

XX-XXX-XX26-NOV-09B PP




INIT EDITA

SAM3S-EK37B

XX-XXX-XXNL XXX

Microcontroller





INIT EDITA

SAM3S-EK37B

XX-XXX-XXNL XXX

Microcontroller


R3 DNPR3 DNP

TP3GNDTP3GND

TP1GNDTP1GND

C21

4.7u

FC

214.

7uF

R6 DNPR6 DNP

C12

100n

FC

1210

0nF

R9 DNPR9 DNP

C6

100n

FC

610

0nF

R1 DNPR1 DNP

JP3JP3

+ C2410uF

+ C2410uF

C320pFC320pF


JP5JP5

R4 0RR4 0R

C20

4.7u

FC

204.

7uF

C9

100n

FC

910

0nF

JP1 DNPJP1 DNP

C420pFC420pF

R141RR141R

C19

100n

FC

1910

0nF

JP7JP7

R249.9R 1%R249.9R 1%

C14

100n

FC

1410

0nF

Y1Y1

12

3

C18

100n

FC

1810

0nF

JP2JP2

1

2

3

R8 DNPR8 DNP

C11

100n

FC

1110

0nF

TP2GNDTP2GND

C17

100n

FC

1710

0nF

R7 DNPR7 DNP

J2J212345678910111213141516171819202122232425

26272829303132333435363738394041424344454647484950

51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75

767778798081828384858687888990919293949596979899100

TP4GNDTP4GND

C8

2.2u

FC

82.

2uF

C16

100n

FC

1610

0nF

C5100nFC5100nF

AT91SAM3S-LQFP100

MN1

AT91SAM3S-LQFP100

MN1

PA0_PWMH0_TIOA0_A1774

PA1_PWMH1_TIOB0_A1872

PA2_PWMH2_SCK0_DATRG67

PA3_TWD0_NPCS366

PA4_TWCK0_TCLK055

PA5_RXD0_NPCS353

PA6_TXD0_PCKO52

PA7_RTS0_PWMH349

PA8_CTS0_AD12BTRG48

PA9_URXD0_NPCS146

PA10_UTXD0_NPCS244

PA11_NPCS0_PWMH042

PA12_MISO_PWMH141

PA13_MOSI_PWMH233

PA14_SPCK_PWMH331

PA15_TF_TIOA1_PWML330

PA16_TK_TIOB1_PWML228

PA17_TD_PCK1_PWMH3_AD12B012

PA18_RD_PCK2_A14_AD12B114

PA19_RK_PWML0_A15_AD12B218

PA20_RF_PWML1_A16_AD12B324

PA21_RXD1_PCK1_AD12B815

PA22_TXD1_NPCS3_NCS2_AD12B920

PA23_SCK1_PWMH0_A1922

VD

DC

OR

E85

JTAGSEL77

GN

D45

GN

D95

GN

D70

GN

D26

VD

DIO

27

VD

DIO

69

VD

DIO

91

PB8_XOUT96

PB9_XIN97

PB0_PWMH0_AD12B43

NRST60

VD

DC

OR

E56

ADVREF1

PA25_CTS1_PWMH2_A2338PA24_RTS1_PWMH1_A2034

PB2_URXD1_NPCS2_AD12B67

PB3_UTXD1_PCK2_AD12B79

PB6_TMS_SWDIO79 PB4_TWD1_PWMH2_TDI51

PB5_TWCK1_PWML0_TDO76 PB7_TCK_SWCLK83

TEST61

PB12_PWML1_ERASE87 PB14_NPCS1_PWMH3_DACO1

99

VD

DO

UT

11

PB1_PWMH1_AD12B55

PA26_DCD1_TIOA2_MCDA239

PA27_DTR1_TIOB2_MCDA357

PA28_DSR1_TCLK1_MCCDA59

PA29_RI1_TCLK2_MCCK63

PA30_PWML2_NPCS2_MCDA064

PA31_NPCS1_PCK2_MCDA181

VD

DIN

10

PB10_DDM88

PB11_DDP89

PB13_PWML2_PCK0_DACO093

VD

DIO

98

VD

DC

OR

E36

VD

DC

OR

E16

VD

DP

LL10

0

VD

DIO

50

GN

D2

PC

0_D

0_P

WM

L025

PC

1_D

1_P

WM

L147

PC

2_D

2_P

WM

L243

PC

3_D

3_P

WM

L340

PC

4_D

4_N

PC

S1

37

PC

5_D

535

PC

6_D

632

PC

7_D

729

PC

8_N

WR

0_N

WE

58

PC

9_N

AN

DO

E62

PC

10_N

AN

DW

E65

PC

11_N

RD

68

PC

12_N

CS

3_A

D12

B12

23

PC

13_N

WA

IT_P

WM

L0_A

D12

B10

21

PC

14_N

CS

071

PC

15_N

CS

1PW

ML1

_AD

12B

1119

PC

16_A

21_N

AN

DA

LE73

PC

17_A

22_N

AN

DC

LE75

PC

18_A

0_N

BS

0_P

WM

H0

78

PC

19_A

1_P

WM

H1

80

PC

20_A

2_P

WM

H2

82

PC

21_A

3_P

WM

H3

84

PC

22_A

4_P

WM

L386

PC

23_A

5_T

IOA

390

PC

24_A

6_T

IOB

392

PC

25_A

7_T

CLK

394

PC

26_A

8_T

IOA

413

PC

27_A

9_T

IOB

417

PC

28_A

10_T

CLK

454

PC

29_A

11_T

IOA

5_A

D12

B13

4

PC

30_A

12_T

IOB

5_A

D12

B14

6

PC

31_A

13_T

CLK

5_A

D12

B15

8

C234.7uFC234.7uF

R110RR110R

C13

DN

PC

13D

NP

C7

100n

FC

710

0nF

C22100nFC22100nF

Y2 12MHzY2 12MHz

C1 20pFC1 20pF

JP8JP8

C15

100n

FC

1510

0nF

R10 DNPR10 DNP

Y332.768KHzY332.768KHz

12

3

R132.2KR132.2K

R5 0RR5 0R

JP4 DNPJP4 DNP

R120RR120R

J1J1

12 3

54

C2 20pFC2 20pF

MN2LM4040-2.5

MN2LM4040-2.5

C10

100n

FC

1010

0nF

JP6JP6

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MT29F2G08AADWP

NAND FLASH

USART

ICE INTERFACE

RS 485

SD CARD

UART


PC10PC9PC16PC17

PA28

PA22

PA24

PA25

PA21

PA25PA24PA21PA22

PA23

PA23

PA29

PC18

PC14

PA6

PA26PA27

PA30PA31

+3V3

DGND

+3V3

DGND

+3V3

+3V3

DGND

+3V3

FGND

DGND

+3V3

DGND

+3V3

+3V3

DGND

DGND

+3V3

+3V3 +3V3

DGND

+3V3

DGND

+3V3

DGNDDGND

+3V3 +3V3

FGND

FGND

DGND

PC[0..31]{3,5,7}

PA[0..31]{3,5,7}

NRST{3,5,7}

PA10{3,7}PA9{3,7}

PB5{3,7}

PB7{3,7}PB6{3,7}PB4{3,7}




INIT EDITA

SAM3S-EK47B

XX-XXX-XXNL XXX

NAND FLASH,SERIAL INTERFACE





INIT EDITA

SAM3S-EK47B

XX-XXX-XXNL XXX






INIT EDITA

SAM3S-EK47B

XX-XXX-XXNL XXX



MN3MN3

WE18

N.C66

VCC37

CE9

RE8

N.C1120

WP19

N.C55

N.C11

N.C22

N.C33

N.C44

N.C1221

N.C1322

N.C1423

N.C1524

R/B7

N.C1726

N.C1827N.C1928

I/O029

N.C2134N.C2235

VSS36

PRE38N.C2339

VCC12

VSS13

ALE17

N.C811 N.C710

N.C914

N.C1015

CLE16

N.C1625

N.C2033

I/O130

I/O332I/O231

N.C2747

N.C2646

N.C2545

I/O744I/O643I/O542I/O441

N.C2440

N.C2848

R43100KR43100K

C39100nFC39100nF

R41100KR41100K

C40100nFC40100nF

MN4ADM3485ARZMN4ADM3485ARZ

RO1

RE2

DE3

DI4

VCC8

GND5

A6

B7

TP5SMDTP5SMD

+ C2510uF

+ C2510uF

R36 0RR36 0R

C34100nFC34100nF

C35100nFC35100nF

R39100KR39100K

C36100nFC36100nF

C27100nFC27100nF

R3247KR3247K

R1547KR1547K

J7J7

5

4

3

2

1

9

8

7

6

10 11

RA168KX4RA168KX4

12345 6 7 8

MN5ADM3312EARUMN5ADM3312EARU

C1+6

C1-20

C2+2

C2-4

C3+24

C3-22

VCC3

V+1

V-21

GND23

SD19

EN5

T1IN7

T1OUT18

R1IN15

R1OUT10

T2IN8

T2OUT17

R2IN14

R2OUT11

T3IN9

T3OUT16

R3IN13

R3OUT12

R38 0RR38 0R

R28 0RR28 0R

R46100KR46100K

C314.7uFC314.7uF

C32100nFC32100nF

R35 0RR35 0R

C37100nFC37100nF

R30DNPR30DNP

R1810KR1810K

R21 47KR21 47K

R1647KR1647K

R1710KR1710K

J4J41

2

3

C38100nFC38100nF

R29120RR29120R

C26100nFC26100nF

C33100nFC33100nF

TP6SMDTP6SMD

J5J5

5

4

3

2

1

9

8

7

6

10 11

R34 0RR34 0R

C30100nFC30100nFR26 0RR26 0R

J6J6

VTref1

Vsupply2

nTRST3

GND14

TDI5

GND26

TMS7

GND38

TCK9

GND410

RTCK11

GND512

TDO13

GND614

nSRST15

GND716

DBGRQ17

GND818

DBGACK19

GND920

C41100nFC41100nF

R42100KR42100K

JP11JP11

C291uFC291uF

R40100KR40100K

JP12JP12

R33 0RR33 0R

R44 0RR44 0R

J3TF01AJ3TF01A

DAT21

DAT32

CMD3

VCC4

CLK5

VSS6

DAT07

DAT18

GND10

CD9

Sh111

Sh212

Sh313

JP10JP10

R19 0RR19 0R

R22DNPR22DNP

R47 0RR47 0R

R48 0RR48 0R

R31 0RR31 0R

R37 47KR37 47K

C42100nFC42100nF

R27 0RR27 0R

R23DNPR23DNP

R25 DNPR25 DNP

JP9JP9

MN6MAX3232CSEMN6MAX3232CSE

T1IN11

T2IN10 R1OUT12

R2OUT9

T1OUT14

T2OUT7R1IN13

R2IN8

V+2

C1+1

C1-3

C2+4

C2-5

V-6

VCC16

GND15

R20 0RR20 0R

R24DNPR24DNP

C28100nFC28100nF

R45100KR45100K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

The part is placed as close as possible to J8

NOT POPULATED

LCD_DB10LCD_DB11LCD_DB12LCD_DB13LCD_DB14LCD_DB15LCD_DB16LCD_DB17

LCD

QTOUCH ELEMENTS

LCD TOUCH SCREENLCD BACKLIGHT

2.8" 320x240 TFT LCD DISPLAY

LED_A

LED_K1LED_K2LED_K3LED_K4

PC13

X_RIGHT

X_LEFTY_UP

Y_DOWN

PA12PA13PA14

PA17

PA11

X_RIGHTY_UPX_LEFTY_DOWN

X_LEFTX_RIGHTY_DOWNY_UPLED_K4LED_K3LED_K2LED_K1

LED_A


NRSTPC15

PC19

PC11PC8

PC25

PC24

PC31

PC30

PC29

PC28

PC23

PC22

PC27

PC26

PA1

PA0

PA3

PA2

PA5

PA4


PA5PA4

PA2PA1PA0

PC13


LCD_DB9LCD_DB8LCD_DB7LCD_DB6LCD_DB5LCD_DB4LCD_DB3LCD_DB2LCD_DB1LCD_DB0

LCD_DB0

LCD_DB4

LCD_DB9

LCD_DB5LCD_DB7LCD_DB6LCD_DB8LCD_DB1LCD_DB3LCD_DB2

PA11

PA16

PA3

PC23PC22

+3V3

+3V3

DGND

DGND

DGND

DGND

DGND

+3V3

+3V3

+3V3

AGND_TP

+3V3

DGND

+3V3

DGND

AGND_TP

DGND

NRST{3,4,7}

PC[0..31]{3,4,7}

PA[0..31]{3,4,7}




INIT EDITA

SAM3S-EK57B

XX-XXX-XXNL XXX

TFT-LCD & QTouch





INIT EDITA

SAM3S-EK57B

XX-XXX-XXNL XXX

TFT-LCD & QTouch





INIT EDITA

SAM3S-EK57B

XX-XXX-XXNL XXX

TFT-LCD & QTouch


R62100KR62100K

R70 0RR70 0R

R53 1KR53 1K

R67 0RR67 0R

R66 0RR66 0R



1

2

345

R54 1KR54 1K

C4922nFC4922nF

R680RR680R

R5610KR5610K

C574.7uFC574.7uF

R50 1KR50 1K

JP13JP13

C551uFC551uF

C5022nFC5022nF

R60 1KR60 1K

RA3DNPRA3DNP

1234 5

678

R61 DNPR61 DNP

R65100KR65100K

MN8AAT3155ITP-T1MN8AAT3155ITP-T1

C1+10

C1-9

EN/SET11

C2+7

C2-6

OUTCP8

IN5

GND4

D13

D22

D31

D412

C4622nFC4622nF

R51 1KR51 1K

+ C4310uF

+ C4310uF

C60100nFC60100nF

C58100nFC58100nF


PINsonBOT

PIN 39

PIN 1

FTM280C34D-8bit

PINsonBOT

PIN 39

PIN 1

FTM280C34D-8bit

R72100KR72100K

R69 0RR69 0R

S1DNPS1DNP

SL

SM

SR

SR

R57 1KR57 1K

C44100nFC44100nF

C5122nFC5122nF

R52 1KR52 1K

C614.7uFC614.7uF

R6447KR6447K

TP9SMDTP9SMD

B1BN03K314S300RB1BN03K314S300R

J8FH26-39S-0.3SHWJ8FH26-39S-0.3SHW

VDD1

DB172

DB163

DB154

DB145

DB136

DB127

DB118

DB109

DB910

DB811

DB712

DB613

DB514

DB415

DB316

DB217

DB118

DB019

VDD20

RD21

WR22

RS23

CS24

RESET25

IM026

IM127

GND28

LED-A29

LEDK130

LEDK231

LEDK332

LEDK433

Y+34

Y-35

X+36

X-37

NC38

GND39

C561uFC561uF

R55 1KR55 1K

R584.7KR584.7K

C4722nFC4722nF

C541uFC541uF

C45100nFC45100nF

R63 DNPR63 DNP

C4822nFC4822nF

K1DNPK1DNP

R711RR711R

RA2DNPRA2DNP

1234 5

678

R59 0RR59 0R

R4947KR4947K

C5322nFC5322nF

C59100nFC59100nF

TP8SMDTP8SMD

TP7SMDTP7SMD

R740RR740R

C5222nFC5222nF

R73100KR73100K

MN7ADS7843EMN7ADS7843E

XP2

YP3

XM4

YM5

DCLK16

DIN14

DOUT12

CS15

BUSY13

PENIRQ11

VREF9

VCC11

VCC210

GND6

IN37

IN48

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Potentiometer

SOLDER DROP 2 pins open.Normal

JP14 and JP15 should be setor removed together

AD12B5

DAC01

AUDIO IN

DAC

ADC

AUDIO OUT

AUDIO_OUTL

AUDIO_OUTL

AGND

AGND AGND

AVDD

AGND

VDD_AMP

AGND

AGND

AGND

DGND

+5V

DGND

+5V

DGND

DGND

DGND

AGND

AGND AGND

AGND

AVDD

AGND

AGND

DGND

AVDD

AGND

VCC33

+5V

AGND

VCC33

DGND

VDD_AMP

AGND

+3V3

DGND

VCC33+5V

DGND

DGND

DGND

PB0 {3,7}

PB1 {3,7}

PB14 {3,7}

PB13{3,7}




INIT EDITA

SAM3S-EK67B

XX-XXX-XXNL XXX






INIT EDITA

SAM3S-EK67B

XX-XXX-XXNL XXX






INIT EDITA

SAM3S-EK67B

XX-XXX-XXNL XXX



C721nFC721nF

JP19JP19

+ C75100uF

+ C75100uF

JP18JP18

1

2

3

C82100nFC82100nF

R801KR801K

C88 0.47uFC88 0.47uF

+ C6522uF

+ C6522uF

C64100nFC64100nF

R90100KR90100K

C93470pFC93470pF

C90 2.2uFC90 2.2uF

C914.7uFC914.7uF

C671uFC671uF

+C81 220uF+C81 220uF

C74100nFC74100nF

R841KR841K

R103 100KR103 100K

R8747KR8747K

R791KR791K

R781KR781K

R95 1KR95 1K

MN14MIC5219-3.3YMMMN14MIC5219-3.3YMM

IN2

EN1

BYP4

GND5

GND6

GND7

GND8

OUT3

CN1BNCCN1BNC

1234

5

R77470RR77470R

MN10BNX002-01MN10BNX002-01

SV1

SG2

CV3

CG14

CG25

CG36

B2 BN03K314S300RB2 BN03K314S300R

C7122nFC7122nF

R830RR830R

C871uFC871uF

R99 47KR99 47K

R88470RR88470R

JP20JP20

C76100nFC76100nF

R98 33KR98 33K

+ C6622uF

+ C6622uF

TB10RTB10R

C6322uFC6322uF

C62100pFC62100pF

MN9ZEN056V130A24LSMN9ZEN056V130A24LS

1

2

3

C774.7uFC774.7uF

C86 0.47uFC86 0.47uF

R851KR851K

JP21JP21

MN13TPA0223DGQMN13TPA0223DGQ

VDD3

RIN5

MONO-IN1

LIN9

LO/MO-10

RO/MO+6

ST/MN7

SHUTD0WN2

BYPASS4

GND8

PA

D11

JP16JP16

R92102K 1%R92102K 1%

+ C8010uF

+ C8010uF

C85 0.47uFC85 0.47uF

R10949.9R 1%R10949.9R 1%

R100 33KR100 33K

R105 33KR105 33K

C7322uFC7322uF



VIN2

VOUT4

SD1

GN

D1

3

ADJ5

GN

D2

6

SD1SD1

1 2

R75 47KR75 47K

MN11TS922MN11TS922

IN1-2

IN1+3

OUT27

IN2-6

IN2+5

GND4

VCC8

OUT11

JP14JP14

+C83 220uF+C83 220uF

R1060RR1060R

CN2BNCCN2BNC

1234

5

R76 47KR76 47K

J11EARJACKJ11EARJACK5

4321R97 1KR97 1K

R93100KR93100K

VR110KVR110K

13

2

R102 100KR102 100KTP12SMDTP12SMD

C84 0.47uFC84 0.47uF

R9649.9R 1%R9649.9R 1%

SD2SD2

1 2

R89169K 1%R89169K 1%

R910RR910R

B3BN03K314S300R

B3BN03K314S300R

JP15JP15

C8910nFC8910nF

J9MP179P 2.1mmJ9MP179P 2.1mm

12

3

JP17JP17

C691nFC691nF

J10J1012

R8647KR8647K

R104 47KR104 47K

R101 100KR101 100K

R821KR821K

C681uFC681uF

MIC1SVB6050MIC1SVB6050

12

R940RR940R

C791uFC791uF

C7810nFC7810nF

+ C9210uF

+ C9210uF

R81100RR81100R

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

IRQ0_ZBEEIRQ1_ZBEESPIO_NPCS2#MISO

MOSISPCK

SLP_TRZB_RSTN

PIO EXPANSION

USB

LEDS

ZIGBEE

BUTTONS

PA13

PC0PC1PC2PC3PC4PC5PC6PC7PC8PC9PC10PC11PC12PC13PC14PC15

PC19

PC17

PC21

PC16

PC20

PC18

PB6

PB1

PB3

PB7

PB4

PB0

PB5

PB2

PB14

PB9

PB11PB12

PB8

PB13

PB10

PA6

PA9

PA11

PA14PA13

PA7PA8

PA12

PA10

PA15

PA22

PA27

PA23

PA29PA30

PA25

PA21

PA28

PA24

PA26

PA31

PA16

PB2PA12 PA14

PA15PA17PA18

PB3

PC12

PA19

PA20

PC21 PC20

PB10

PB11


+3V3 +3V3 +3V3+3V3

DGND DGND

DGND

DGND DGND

DGND

+3V3

+3V3 +3V3

DGND

DGND

+3V3

DGND

DGND

+5V +3V3 +5V +5V+3V3 +3V3

+3V3 +5V

DGND

DGND FGND

FGND

PC[0..31]{3,4,5}

PB[0..14]{3,4,6}

PA[0..31]{3,4,5}

NRST {3,4,5}




INIT EDITA

SAM3S-EK77B

XX-XXX-XXNL XXX

MISC





INIT EDITA

SAM3S-EK77B

XX-XXX-XXNL XXX

MISC





INIT EDITA

SAM3S-EK77B

XX-XXX-XXNL XXX

MISC


C9410pFC9410pF

JP23JP23

1

2

3

R110 47KR110 47K

C9518pFC9518pF

R120 0RR120 0R

R116 27RR116 27R

5V D- D+ ID G

J15USB Micro B

5V D- D+ ID G

J15USB Micro B

1 2 3 4

7

5

689

J16J161 23 45 67 89 10

JP26JP26

R119 0RR119 0R

D4 Red-ledD4 Red-led

R113220RR113220R


JP22JP22

1

2

3


R118 0RR118 0R

J14J141 23 45 67 89 10

11 1213 1415 1617 1819 2021 2223 24

R112 68KR112 68K Q1IRLML2502

Q1IRLML2502

1

32

J13J131 23 45 67 89 10

11 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 40

J12J121 23 45 67 89 10

11 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 40

JP27JP27R121 0RR121 0R

BP1BP11

423

JP24JP24

1

2

3

R115 100KR115 100K

C962.2nFC962.2nF

C972.2uFC972.2uF

D3 Green-ledD3 Green-led

BP3BP31

423

R117220RR117220R

R111220RR111220R D2 Blue-ledD2 Blue-led

R114 27RR114 27R

JP25JP25BP2BP21

423

Section 6

Troubleshooting

6.1 Self-Test

A test package software is available to implement a functional test for each section of the board. Refer to the SAM3S-EK page on www.atmel.com.

6.2 Board Recovery

Closing JP3 and powering the board will assert ERASE and clear GPNVM bit 1, and thereby selects the boot from the ROM by default. The MCU will boot from the internal ROM to enable a SAM-BA connection through the UART. Connect the SAM3S-EK UART port (J3) to a PC COM port through an RS232 cross-over cable.

You can then run the SAM-BA application from that PC to program the internal Flash of the MCU as well as the GPNVM bit 1.



Section 7

Revision History

7.1 Revision History

Table 7-1.

Document CommentsChange Request Ref.

11031C Note 2 added to Section 4.3.9 ”JTAG/ICE” 7637

11031B A note added at the end of Section 4.3.4, ” Reset Circuitry”. 7565

11031A First issue.




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Web Sitewww.atmel.comwww.atmel.com/AT91SAM

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