SAMA5D27 SOM1 Kit1 User's Guide - Microchip Technologyww1.microchip.com/downloads/en/DeviceDoc/DS50002667A.pdf · SAMA5D27 SOM1 Kit1 SAMA5D27 SOM1 Kit1 User's Guide Scope This user's

SAMA5D27 SOM1 Kit1 SAMA5D27 SOM1 Kit1 User's Guide

Scope

This user's guide provides detailed information on the overall design of the SAMA5D27 SOM1 Kit1 anddescribes how to use the kit.

The kit is the evaluation platform for the SAMA5D27 SIP (System-In-Package) and SOM (System-On-Module), and comprises:

a baseboard a SAMA5D27 SOM soldered on the baseboard a SAMA5D27 SIP soldered on the SOM a USB cable

See the figure below.

Figure 1.SAMA5D27 SOM1 Kit1 Overview

SIP (System-In-Package)SOM (System-On-Module)

Baseboard

2017 Microchip Technology Inc. User Guide DS50002667A-page 1

Table of Contents

Scope.............................................................................................................................. 1

1. Object of Declaration................................................................................................. 3

2. Introduction................................................................................................................42.1. Document Layout......................................................................................................................... 42.2. Reference Documents..................................................................................................................4

3. Product Overview...................................................................................................... 53.1. Kit Contents..................................................................................................................................53.2. Features....................................................................................................................................... 53.3. Specifications............................................................................................................................... 63.4. Power Sources.............................................................................................................................6

4. Baseboard Components............................................................................................84.1. Baseboard Overview....................................................................................................................84.2. Function Blocks..........................................................................................................................104.3. External Interfaces..................................................................................................................... 284.4. Debugging Capabilities.............................................................................................................. 334.5. PIO Usage on Expansion Connectors........................................................................................38

5. Installation and Operation........................................................................................455.1. System and Configuration Requirements...................................................................................455.2. Baseboard Setup........................................................................................................................45

6. Errata.......................................................................................................................466.1. Incorrect NRST and WKUP Push Button Markings....................................................................46

7. Appendix: Schematics and Layouts........................................................................ 47

8. Revision History.......................................................................................................56

The Microchip Web Site................................................................................................ 57

Customer Change Notification Service..........................................................................57

Customer Support......................................................................................................... 57

Microchip Devices Code Protection Feature................................................................. 57

Legal Notice...................................................................................................................58

Trademarks................................................................................................................... 58

Quality Management System Certified by DNV.............................................................59

Worldwide Sales and Service........................................................................................60

SAMA5D27 SOM1 Kit1


1. Object of DeclarationEU Declaration of Conformity for SAMA5D27 SOM1 Kit1

This declaration of conformity is issued by the manufacturer.

The development/evaluation tool is designed to be used for research and development in a laboratoryenvironment. This development/evaluation tool is not a Finished Appliance, nor is it intended forincorporation into Finished Appliances that are made commercially available as single functional units toend users under EU EMC Directive 2004/108/EC and as supported by the European Commission's Guidefor the EMC Directive 2004/108/EC (8th February 2010).

This development/evaluation tool complies with EU RoHS2 Directive 2011/65/EU.

This development/evaluation tool, when incorporating wireless and radio-telecom functionality, is incompliance with the essential requirement and other relevant provisions of the R&TTE Directive1999/5/EC and the FCC rules as stated in the declaration of conformity provided in the module datasheetand the module product page available at www.microchip.com.

For information regarding the exclusive, limited warranties applicable to Microchip products, please seeMicrochips standard terms and conditions of sale, which are printed on our sales documentation andavailable at www.microchip.com.

Signed for and on behalf of Microchip Technology Inc. at Chandler, Arizona, USA.

SAMA5D27 SOM1 Kit1


http://www.microchip.com/http://www.microchip.com/

2. Introduction

2.1 Document LayoutThe document is organized as follows:

Introduction Product Overview Important information about the kit Board Components Specifications of the kit and high-level description of the major components

and interfaces Installation and Operation Instructions on how to get started with the kit Errata Appendix: Schematics and Layouts Kit schematics and layout diagrams

2.2 Reference DocumentsThe following Microchip documents are available and recommended as supplemental referenceresources:

Type Document Title Available Ref. No./Product

Datasheet SAMA5D2 www.microchip.com/SAMA5D2 DS60001476

Datasheet SAMA5D2 System-On-Module(SOM)www.microchip.com/ATSAMA5D27-

SOM1 DS60001521

Datasheet SAMA5D2 System-In-Package(SIP) www.microchip.com/SAMA5D2 SIP DS60001484

SAMA5D27 SOM1 Kit1


http://www.microchip.com/design-centers/32-bit-mpus/sama5-new/sama5d2-serieshttp://www.microchip.com/wwwproducts/en/ATSAMA5D27-SOM1http://www.microchip.com/wwwproducts/en/ATSAMA5D27-SOM1http://microchip.com/sama5d2sips

3. Product Overview

3.1 Kit ContentsThe kit includes the following:

One baseboard with soldered SOM One USB cable

3.2 FeaturesThe kit comprises a baseboard with a soldered SAMA5D27 SOM1 module. The module features aSAMA5D27-D1G-CU SIP embedding a 1-Gbit DDR2 SDRAM. The SOM offers a reliable and cost-effective embedded platform for building end products, as well as a small form factor, complemented bymany connectivity interfaces. The SOM is a fully-featured industrially-certified single board computerdesigned for integration into customer applications.

The SOM module is a purpose-built small footprint hardware platform equipped with a wide array of high-speed connectivity engineered to support various applications such as IoT endpoints, wearables,appliances or industrial equipment.

The SOM integrates a 1-Gbit DDR2 SDRAM, a QSPI memory and a 10/100 Mbps Ethernet controller.128 GPIO pins are provided by the SOM for general use in the system. All GPIO pins are independentand can be configured as inputs or outputs, with or without pull-up/pull-down resistors.

The baseboard features a wide range of peripherals, as well as a user interface and expansion options,including two mikroBUS click interface headers to support over 300 MikroElektronika click boards andone Pmod interface.

Table 3-1.Baseboard Features

Characteristics Specifications Components

Memory One QSPI Flash (unmounted) Tested with Macronix MX25L25673GM2I-08G

Crypto One CryptoAuthentication device ATECC508

USB Com Port One USB hostOne USB device

One USB HSIC

Connector type CConnector type microAB

2-pin header (not populated)

Ethernet One Ethernet interface RJ45 connector

CAN One CAN interface ATA6561

Video One LCD RGB 24-bit interfaceOne ISC 12-bit interface

50-pin FPC connector2x15 male connector

Storage One standard SD card interfaceOne microSD card interface

With 3.3V/1.8V power switch

Debug port One J-Link-OB and J-Link-CDC

One JTAG interface

Microchip SAM3U micro-controller withembedded J-Link firmware

SAMA5D27 SOM1 Kit1


Characteristics Specifications Components

Board Monitor One RGB (Red, Green, Blue) LEDFour push button switches

Power ON, Reset, Wakeup, User Free

Expansion One tamper connectorOne Pmod connector

Two mikroBUS interfaces

10-pin male connector6-pin female connector

2x8-pin female connector

Board Supply From USB A and/or USB J-Link-OB 5 VDC

Power saving SuperCap

Refer to www.microchip.com for:

Sample code and technical support Linux software and demos

3.3 SpecificationsTable 3-2.Kit Specifications

Characteristic Specification

Ordering code ATSAMA5D27-SOM1-EK1

Board supply voltage USB-powered

Temperature Operating: 0C to +70CStorage: 40C to +85C

Relative humidity 0 to 90% (non-condensing)

Baseboard dimensions 135 90 20 mm

RoHS status Compliant

3.4 Power SourcesTwo options are available to power up the baseboard:

USB powering through the USB Micro-AB connector (J17 - default configuration) Powering through the USB Micro-AB connector on the J-Link-OB Embedded Debugger interface

(J10)

The two power sources can coexist. A priority mechanism manages the automatic switching between thetwo. The priority source is J-Link (J10), the secondary source is the USB port (J17).

Table 3-3.Electrical Characteristics

Electrical Parameter Value

Input voltage 5VCC

Maximum input voltage 6VCC

SAMA5D27 SOM1 Kit1


http://www.microchip.com/

Electrical Parameter Value

Maximum 3.3VDC current available 1.2A

I/O voltage 3.3V only

SAMA5D27 SOM1 Kit1


4. Baseboard ComponentsThis section covers the specifications of the SAMA5D27 SOM1 Kit1 baseboard and provides a high-leveldescription of the baseboard's major components and interfaces. This document is not intended toprovide a detailed documentation about the processor or about any other component used on thebaseboard. It is expected that the user will refer to the appropriate documents of these devices to accessdetailed information.

4.1 Baseboard OverviewThe fully-featured SAMA5D27 SOM1 Kit1 baseboard integrates multiple peripherals and interfaceconnectors, as shown in the figure below.

Figure 4-1.SAMA5D27 SOM1 Kit1 Baseboard Overview

The following picture illustrates the kit block diagram.

Figure 4-2.SAMA5D27 SOM1 Kit1 Block Diagram

PCB JTAGInterface

SPIFlash

System Supplies POWERREGULATOR

GPIO, SHDN

UART

MPU JTAGInterface

JTAG

LCD

ISC

TWI

FLEXCOM

RJ45

ETH

CAN

CAN

mikroBUSInterface

mikroBUSInterface

GPIO

USB A&B

SDHC0

SDHC1

RGBLeds

USBDetection

DEBUGInterface

Push Button

Reset, WkupDisBoot, User

PmodInterface

PIOBU Connector

ISC Connector

3v3, 1v8

Power Cap VDDBU

JTAG SWITCH

USB-AConnector

USB-BConnector

uSDConnector SD CardConnector

5V

GPIO

USBPower Switch

3.3V, 1.8V

FPC Connector

POWERMONITOR SAMA5D27-SOM1

DDR2, QSPI, EEPROM,ETHERNET PHY, GPIOsJLINK-OB

JLINK-CDC

DualLED

Function Select

QSPI

GPIOFunction Select

Power Switch

CRYPTO

ECC508

TriState

JLINK Power5V/3.3V

USBConnector

SAMA5D27 SOM1 Kit1


4.1.1 Default Jumper SettingsThe figure below shows the default jumper settings. Jumpers in red are configuration items and currentmeasurement points. The following table describes the functionality of the jumpers.

Figure 4-3.Default Jumper Settings

Table 4-1.Jumper Settings

Jumper Default Function

J1 Closed VDD_MAIN_5V current measurement

J2 Closed VDD_3V3 SOM current measurement

J4 Closed VDDBU current measurement

J7 Open Enables J-Link-OB (closed=disable)

J8 Open

Erases SAM3U firmware code (closed=erase at power-up)

Warning: Must remain open. If closed, the SAM3U contents are erasedand J-Link functionality is discarded.

J9 Open Enables JTAG-CDC (closed=disable)

J13 Open Disables SOM boot memories (closed=disable)

SAMA5D27 SOM1 Kit1


Jumper Default Function

J22 Closed Enables 3.3V power mikroBUS1 (closed=enable)

J28 Closed Enables 3.3V power mikroBUS2 (closed=enable)

4.1.2 Baseboard ConnectorsThe following table describes the interface connectors on the SAMA5D27 SOM1 Kit1 baseboard.

Table 4-2.Baseboard Interface Connectors

Connector Interfaces to

J5 CLK_AUDIO test point (not populated)

J6 PCB-edge JTAG connector for factory-programming the J-Link-OB

J10 USB-A MicroAB, J-Link-OB port

J11 MPU SAMA5D27 JTAG 10-pin IDC connector

J12 Standard SDMMC0 connector

J14 microSD connector

J15 Ethernet RJ45 connector

J16 CAN 3-pin screw connector

J17 USB-A MicroAB connector

J18 HSIC 2-point header

J19 USB-B type C connector

J20-J23 Jumper to select Pmod functions

J21 Pmod connector

J24-25 mikroBUS1 connectors

J26 Expansion TFT LCD connector for display module

J27 ISC connector

J29-J30 mikroBUS2 connectors

J31 Tamper and analog comparator connector

J32 SHDN test point (not populated)

4.2 Function Blocks

4.2.1 SAMA5D27 SOM1The SAMA5D27 SOM1 main features are as follows:

Ultra-small SIP (SAMA5D27-D1G-CU) embedding an ultra-low-power SAMA5D27 Arm Cortex-A5 processor and a 1 Gbit DDR2 SDRAM memory

SST26VF064 64 Mb QSPI Flash 24AA02E48 2 Kb serial E2PROM with preprogrammed EUI node identity

SAMA5D27 SOM1 Kit1


MIC2800 power management device KSZ8081RNA Ethernet Phy 10/100 MHz RMII

Refer to the SAMA5D27 SOM1 datasheet for more information.

Figure 4-4.SAMA5D27 SOM1 Block Diagram

MPU + DDR2 1GbSAMA5D27-SiP

LFBGA28914 x 14 mm

Pitch 0.8 mm

64Mbit Serial QUAD I/OFlash Memory

SST26VF064B-104I/MF

2K Serial EEPROMwith EUI-48 Node Identity

24AA02E48T-I/OT

10BASE-T / 100BASE-TXPHY With RMII Support

KSZ8081RNAIA

Power ManagementUnit

MIC2800-G4JYML

VDDSDHC VDDISC VDDBU

MAIN3.3V

TWI Interface

103 Mixable I/O

CLAS

S-D

Ster

eo

eMM

C In

terfa

ce

QSP

I Int

erfa

ce

Cam

era

Inte

rface

Up to

6 *

PTC

Butto

ns

Up to

4 *

ADC

Inpu

ts

TWI I

nter

face

Up to

4 *

UART

2 * S

PI In

terfa

ces

Up to

4 *

FLEX

COM

LCD

Inte

rface

up

to 2

4-bi

t

SSC

Inte

rface

Mon

o PD

MIC

Inte

rface

Up to

2 *

CAN

IS In

terfa

ce

SDIO

Inte

rface

SD-C

ARD

Inte

rface

ExternalQSPI

Connection

JTAG & DBGU Interfaces DEBUG

SYSTEM

MISC

USB Dev.

USB Host

HSIC

BACKUP7 * PIOBU

RXDWAKEUP

RESET

SHUTDOWN

CLK_AUDIO

COMPP / COMPN

Disable Boot

4.2.2 Power Supply Topology and Power Distribution

4.2.2.1 Input Power OptionsAs described previously, the board power source can come through either a USB connector (J10 or J17)connected to a PC or a 5VDC-USB power supply unit. Such USB power source is sufficient to supply theboard in most applications. It is important to note that when the USB-powered operation is used, theUSB-B Host port has a limited powering capability for the device connected to it down the way. If theUSB-B Host port is required to provide full powering capabilities to a target device, then it isrecommended to use an external DC-USB power supply unit as main power source for the whole systemrather than a PC or a USB hub.

The baseboard embeds a local power management stage comprising two sets of load switches,respectively implemented by MOSFET DMP2160 and DC/DC converter MIC23451.

The following figure is a schematic of the power options.

SAMA5D27 SOM1 Kit1


Figure 4-5.Input Powering

VBUS_JLINK

VDD_MAIN_5V

VBUS_USBA

R8100K

Q1-2DMP2160

5

8 43

J1TSW-102-07-G-S

1 2

Q2-2

DMP2160

5

8 43

C4100nF

R310K

C9100nF

Q1-1DMP2160

2

716

Q2-1

DMP2160

2

716

R12100KDNP

R1100K

C1100nF

Note: PC/USB-powered operation eliminates additional wires and batteries. It is the preferred mode ofoperation for any project that requires only a 5V source at up to 500 mA.

Jumper J1 is used to perform MAIN_5V current measurements on the baseboard.

4.2.2.2 Power Supply Requirements and RestrictionsDetailed information on the device power supplies is provided in tables SAMA5D2 Power Supplies andPower Supply Connections in the SAMA5D2 Series datasheet.

4.2.2.3 Power-up and Power-down ConsiderationsPower-up and power-down considerations are described in section Power Considerations of theSAMA5D2 Series datasheet.

Caution: The power-up and power-down sequences provided in the SAMA5D2 Seriesdatasheet must be respected for reliable operation of the device. These are respected by theon-board MIC23451.

4.2.2.4 Power ManagementThe baseboard power management uses a MIC23451 PMIC, which is a triple synchronous buck regulatorwith HyperLight Load mode featuring a power good indicator. The triple DC-DC step down powerregulator delivers two outputs: 3.3V/2A and 1.8V/2A.

While the external power is being applied, the baseboard can be shut down by software and then wokenup by action on the PB2 push button, which activates the WKUP signal.

The figure below shows the power management scheme.

SAMA5D27 SOM1 Kit1


Figure 4-6.Baseboard Power Management

BB_PWR_GOOD

VOUT1

VOUT2 VDD_SDHC_1V8

VDDIN_3V3

VOUT3 VDD_3V3

VDD_MAIN_5V

VOUT2

VOUT1

VOUT3

VDD_SDHC_3V3

PD8

R1300R

C210uF

R9158K

R16 10K

R11309K

L2

180ohm at 100MHz

1 2

C64.7uF

L1

180ohm at 100MHz

1 2

J1TSW-102-07-G-S

1 2

R10 10K

L6

1uH

R17 0RDNP

R6301K

R571K5

C84.7uF

R19 0RDNP

R4 100R

U1

MIC23451

PVIN125

PVIN25

PVIN38

AVIN13

AVIN26

AVIN39

PG120

PG216

PG313

EN121

EN219

EN315

SW126

SW24

SW37

SNS122

SNS218

SNS312

FB123

FB217

FB314

PGN

D1

1

PGN

D2

2

PGN

D3

10

AGN

D1

11

AGN

D2

24

EP1

28

EP2

27

C310uF

R13 10K

R2309K

C74.7uF

L8

1uH

J2TSW-102-07-G-S

1 2

R7 10KDNP

R1471K5

C104.7uF

C510uF

R15 10KDNP

R18 10K

L7

180ohm at 100MHz

1 2

L3

1uH

L5

180ohm at 100MHz

1 2

One PIO (PD8) is used to check the status of the main regulator.

Table 4-3.Power Good Signal

PIO Mnemonic Signal Description

PD8 BB_PWR_GOOD High level = power is establishedand at correct level

4.2.2.5 Supply Group ConfigurationThe main regulator provides the 3.3V for the SOM and all power supplies required by the baseboard:

3.3V SOM (VDDIN_3V3) 3.3V VDDSDHC (3.3V or 1.8V) 3.3V baseboard (VDD_3V3) 3.3V VDDBU

Figure 4-7.SOM Power LinesVDDIN_3V3

VDDBU

VDDSDHC

VDDIN_3V3

C212.2uFDNP

C17100nF

C162.2uFDNP

ATSAMA5D27-SOM1

U3F

VDDBU55

VDDIN_3V3_116

VDDIN_3V3_217

VDDISC15

VDDSDHC65

GND_110

GND_218

GND_326

GND_431

GND_539

GND_642

GND_743

GND_850

GND_956

GND_1062

GND_1166

GND_1269

GND_1372

GND_1475

GND_1588

GND_1689

GND_1798

GND_18107

GND_19130

GND_20131

GND_21149

GND_22166

GND_23171

GND_24176

GND_01

C18100nF

C24100nF

C192.2uFDNP

C22100nF

C232.2uFDNP

C20100nF

4.2.2.6 Backup Power SupplyThe baseboard features a power source in order to permanently power the backup area of the SAMA5D2device (refer to the SAMA5D2 Series datasheet). A super capacitor (C14) sustains such permanentpower to VDDBU when all system power sources are off.

SAMA5D27 SOM1 Kit1


Figure 4-8.VDDBU Powering Options

(Super)-Capacitorenergy storage

VDDBUVDD_3V3

D1

BAT54C

31

2

J4TSW-102-07-G-S

1 2

+ C140.2F/3.3V

C13100nF

D2

RB160M-60TR

R20 100R

4.2.3 Shutdown CircuitryOn the baseboard, this circuitry is implemented but inhibited by default (R131 is not populated).

The SHDN signal, output of the shutdown controller, signals the shutdown request to the power supply.This output signal is supplied by VDDBU that is present in Backup mode

The shutdown controller manages the main power supply and is connected to the ENABLE input pin ofthe DC/DC converter providing the main power supplies of the system.

Figure 4-9.Shutdown Controller

POWERON

VDDBU

VDD_MAIN_5V

SHDN

R132100K

R131 0RDNP

R12810K

Q6BSS1381

3

2

Q7BSS1381

3

2

R129100K

R127 10K

PB3

4.2.4 Push Button SwitchesThe baseboard features four push buttons:

One reset push button (PB1). When pressed and released, the baseboard is reset. One wakeup push button (PB2) connected to the SAMA5D27 WKUP pin, used to exit the processor

from Backup mode. One power-on button (PB3).

Figure 4-10.System Push Buttons

NRST

WAKE UP

VDDBU

VDDBU

NRST

WKUP

R126100KDNP

R23 100R

R24 100R

R12110K

PB2

PB1

One user momentary push button (PB4) connected to PIO PA29, and optionally to PIOBU1.

The wakeup is available only if the shutdown controller is used (see figure Shutdown Controller).

SAMA5D27 SOM1 Kit1


Figure 4-11.User Push Button

PIOBU1

PA29

PB4

R72 100RDNP

R73 100R

4.2.5 Additional MemoriesOne additional memory, QSPI device U9, can be soldered on the baseboard. This QSPI Flash memoryuses the same PIOs as the SOM QSPI. Such configuration makes it possible to choose between twobootable memories.

The figure below illustrates the QSPI memory implementation.Figure 4-12.Optional QSPI Serial Data Flash on Baseboard

QSPI1_SCK

QSPI1_IO0

QSPI1_IO1

QSPI1_IO2

QSPI1_IO3

CS_QSPI1

VDD_3V3

VDD_3V3

PB5

PB7

PB8

PB9

PB10

U9

MX25L25673GM2I-08GDNP

SI/SIO05

SO/SIO12

SIO23

SIO37

VCC8

CS#1

SCLK6

GND4

R5310K

C52100nF

R5410K

Table 4-4.QSPI Signal Descriptions

PIO Mnemonic Shared PIO Signal Description

PB5 QSPI1_SCK QSPI on SOM Clock

PB6 QSPI1_CS QSPI on SOM Chip select

PB7 QSPI0_IO0 QSPI on SOM Data0




4.2.5.1 CS Disable BootOne jumper (J13) controls the selection (CS#) of the bootable memory components (QSPI) using a non-inverting 3-state buffer.

Figure 4-13.CS Disable Boot

QSPI1_CS

(SOM)

PB6 CS_QSPI1

VDD_3V3

VDD_3V3

DISABLE_BOOT

PB6

J13

TSW-102-07-G-S1 2

C55100nF

R6010K

R5910K

U10

NL17SZ125DNP

1 OE2 IN3 GND

4OUT

5VCC

The rule of operation is:

PB1 (RESET) pressed and J13 open = booting from QSPI on SOM PB1 (RESET) pressed and J13 closed = booting from QSPI on baseboard if fitted. The QSPI on

SOM is disabled.

Refer to the SAMA5D2 Series datasheet for more information on standard boot strategies andsequencing.

SAMA5D27 SOM1 Kit1


4.2.6 Secure Digital Multimedia Card (SDMMC) InterfaceThe SD (Secure Digital) Card is a non-volatile memory card format used as a mass storage memory inmobile devices.

4.2.6.1 Secure Digital Multimedia Card (SDMMC) ControllerThe baseboard features two Secure Digital Multimedia Card (SDMMC) interfaces that support theMultiMedia Card (e.MMC) Specification V4.41, the SD Memory Card Specification V3.0, and the SDIOV3.0 specification. It is compliant with the SD Host Controller Standard V3.0 Specification.

The SDMMC0 interface is connected to a standard SD card interface. The SDMMC1 interface is connected to a microSD card interface.

4.2.6.2 SDMMC0 Card Connector (J12)A standard MMC/SD card connector, connected to SDMMC0, is mounted on the top side of thebaseboard. The SDMMC0 communication is based on a 12-pin interface (clock, command, write protect,power switch and data (8)). A card detection switch is included.

The figure below illustrates the SDMMC0 interface implementation.

Figure 4-14.SDMMC0

SDMMC0_CD

SDMMC0_DA1SDMMC0_DA0

SDMMC0_CK

SDMMC0_CDASDMMC0_DA3SDMMC0_DA2

SDMMC0_DA4SDMMC0_DA5SDMMC0_DA6SDMMC0_DA7

SDMMC0_WP

VDDSDHC

VDD_3V3

PA0

PA1

PA2PA3

PA4PA5

PA6PA7PA8PA9

PA12

PA13

R520R

J12

SD/MMCPlus CARD

8

5

76

43219

141516

13121110

R5610K

C5310uFR58

10KRR268K

RR168K

C54100nFR57

10K

SAMA5D27 SOM1 Kit1


Figure 4-15.Standard SD Socket J12 Location

The table below describes the pin assignment of SDMMC connector J12.

Table 4-5.Standard SD Socket J12 Pin Assignment

Pin No Mnemonic PIO Signal Description

1 SDMMC0_DAT3_PA5 PA5 Data line

2 SDMMC0_CMD_PA1 PA1 Command/response line

3 GND GND

4 VDDSDHC (3.3V or1.8V) Power line

5 SDMMC0_CK_PA0 PA0 Clock line

6 SDMMC0_CD_PA13 PA13 Card detect






SAMA5D27 SOM1 Kit1





14 SDMMC0_WP_PA12 PA12 Write protect signal

15 GND GND

16 GND GND

Table 4-6.SDMMC1 Power Command

PIO Mnemonic Signal Description

PA11 SDMMC0_VDDSEL Select 3.3V or 1.8V

4.2.6.3 SDMMC1 Card Connector (J14)A microSD card connector, connected to SDMMC1, is mounted on the top side of the baseboard. TheSDMMC1 communication is based on a 6-pin interface (clock, command and four data). A card detectionswitch is included. The microSD connector can be used to connect any microSD card for mass storage.

Figure 4-16.SDMMC1 microSD

SDMMC1_CD

SDMMC1_DAT0SDMMC1_DAT1

SDMMC1_CK

SDMMC1_CDASDMMC1_DAT3SDMMC1_DAT2

VDD_3V3

PA18PA19

PA20PA21

PA22

PA28

PA30

R6210K

C57100nF

SW1

SW2J14

DM3AT-SF-PEJM5

8

5

76

4321

9

131211

10

14

R61 0R

R6310K

C5610uFRR3

68K

SAMA5D27 SOM1 Kit1


Figure 4-17.microSD Socket J14 Location

The table below describes the pin assignment of microSD connector J14.

Table 4-7.microSD Socket J14 Pin Assignment


1 SDMMC1_DAT2 PA20 Data bit 2


3 SDMMC1_CDA PA28 Command

4 VCC 3.3V supply voltage

5 SDMMC1_CK PA22 Clock

6 GND Common ground



9 SW1 GND Ground

10 SDMMC1_CD PA30 Card detection switch

11 GND Common ground


SAMA5D27 SOM1 Kit1





4.2.6.4 CryptoAuthenticationATECC508A is a member of the CryptoAuthentication family of crypto engine authentication devices withhighly secure hardware-based key storage.

The ATECC508A features a flexible command set enabling use in many applications, includingnetwork/IoT node protection, anti-counterfeiting, firmware or media protection, secure data storage anduser password checking.

The device (U11) is mounted in an 8-lead UDFN package.

For more information, refer to the ATECC508A datasheet on www.microchip.com.

Figure 4-18.CryptoAuthentication ATECC508

TWD0

TWCK0

VDD_3V3

PD21

PD22

U11

ATECC508A

NC11

NC22 NC3

3GND4

SDA5

SCL6

NC47

VCC8

C58100nF

Table 4-8.ATECC508 PIO Signal Descriptions

PIO Mnemonic Shared Signal Description

PD21 TWD0 SOM E2PROM24AA02E48

TWI data

PD22 TWCK0 SOM E2PROM24AA02E48

TWI clock

4.2.7 Communication InterfacesThis section describes the signals and connectors related to the ETH, USB and CAN communicationinterfaces.

4.2.7.1 Ethernet 10/100 (GMAC) PortThe on-board SOM integrates a 10/100 Mbps Ethernet controller (KSZ8081RNA) allowing directconnection to any 10/100 Mbps Ethernet-based Local Area Network, for full interaction with local serversand wide area networks such as the Internet.

ETH signals from the SOM are connected to a RJ45 MagJack. Additionally, for monitoring and controlpurposes, a LED functionality is carried on the RJ45 connector to indicate link status.

SAMA5D27 SOM1 Kit1


http://www.microchip.com/

Figure 4-19.Ethernet PHY

LINK ETH_LED0

TX+

RX-

RX+

TX-

EARTH_ETHEARTH_ETH

GND_ETH

VDD_3V3

ETH_LED0

TX+

TX-

RX+

RX-C64100nF

C63100nF

R69 470R

1

2

3

6

4

5

7

8

75

75

75 75

1nF

TD+

TD-

CT

NC

RD-

CT

TX+

TX-

RX+

RX-

RD+

Left Green LED Right yellow LED

J151

2

7

8

3

6

5

4

9101112

1314

1516

Figure 4-20.Ethernet RJ45 Connector J15 Location

The table below describes the pin assignment of Ethernet connector J15.

Table 4-9.Ethernet RJ45 Connector J15 Pin Assignment

Pin No Mnemonic Signal Description

1 TX+ Transmit positive differential pair

2 TX- Transmit negative differential pair

3 RX+ Receive positive differential pair

4 Decoupling capacitor

SAMA5D27 SOM1 Kit1



5 Decoupling capacitor

6 RX- Receive negative differential pair

7 NC

8 EARTH / GND Common ground

9 ACT LED (A) LED activity (not used)

10 ACT LED (K) LED activity (not used)

11 LINK LED (K) LED link connection

12 LINK LED (A) LED link connection



15 NC

16 NC

4.2.7.2 USB InterfacesThe USB (Universal Serial Bus) is a hot-pluggable general-purpose high-speed I/O standard for computerperipherals. The standard defines connector types, cabling, and communication protocols forinterconnecting a wide variety of electronic devices. The USB 2.0 Specification defines data transfer ratesas high as 480 Mbps (also known as High Speed USB). A USB host bus connector uses 4 pins: a powersupply pin (5V), a differential pair (D+ and D- pins) and a ground pin.

The baseboard features three USB communication ports named USB-A to USB-C:

USB-A device interface One USB device standard micro-AB connector. This port offers a VBUS detection function through the R81-R83 resistor ladder. The USB-A port is used as a secondary power source and as a communication link for the

baseboard, and derives power from the PC over the USB cable. In most cases, this port islimited to 500 mA.

USB-B (host port B high- and full-speed interface) One USB host type C connector. The USB-B host port is equipped with a 500 mA high-side power switch.

USB-C (High-Speed Inter-Chip/HSIC port) One USB high-speed host port with an HSIC interface. The port is connected to a single 2-pin header (not populated).

4.2.7.3 USB-A InterfaceThe figure below shows the USB implementation on the USB-A port terminated on a micro USB typemicroAB connector.

The USB-A port (J17) features a VBUS insert detection function through ladder-type resistors R70 andR71.

SAMA5D27 SOM1 Kit1


Figure 4-21.USB-A Type microAB Connector

USBA_VBUS_5V

Top/BotTop/Bot

EARTH_USB_A

VBUS_USBA

USBA_DMUSBA_DP

PD20R70 100K

VBUS

SHD

DMDPID

GND

J17

Micro AB

12345

8 6

11 7

9

10

C6520pF C12

100nF

R71200K

Table 4-10.USB-A PIO Signal Description

PIO Mnemonc Shared Signal Description

PD20 USBA_VBUS_5V VBUS insertiondetection

Figure 4-22.USB-A Type microAB Connector J17 Location

The table below describes the pin assignment of USB-A connector J17.

SAMA5D27 SOM1 Kit1


Table 4-11.USB-A Connector J17 Pin Assignment


1 VBUS 5V power

2 DM Data minus

3 DP Data plus

4 ID On-the-go identification

5 GND Common ground

4.2.7.4 USB-B InterfaceThe figure below shows the USB implementation on the USB-B port terminated on USB Type Cconnector J19.

Figure 4-23.USB-B Type C Connector

Top/BotTop/Bot

USBB_VBUS_5V

EARTH_USB_B

EARTH_USB_B

VDD_3V3USBB_DPUSBB_DM

R7936K

C69330pF

J19

USB C

VBUS1A4

GN

D8

28G

ND

525

GND3B12 GND2A12 GND1A1

VBUS4B4

VBUS2A9

VBUS3B9

GND4B1

TX1+A2

TX1-A3

RX1+B11

RX1-B10

D1+A6

D1-A7

D2+B6

D2-B7

CC1A5

TX2+B2

TX2-B3

RX2+A11

RX2-A10

SBU1A8

SBU2B8

CC2B5

GN

D7

27G

ND

626

R7836K

C70330pF

SAMA5D27 SOM1 Kit1


Figure 4-24.USB-B Type C Connector J19 Location

The table below describes the pin assignment of USB-B connector J19.

Table 4-12.USB-B Connector J19 Pin Assignment


A1 GND Ground return

A2 SSTXp1 SuperSpeed differential pair #1, TX, positive (NOT USED)

A3 SSTXn1 SuperSpeed differential pair #1, TX, negative (NOT USED)

A4 VBUS Bus power

A5 CC1 Configuration channel

A6 DP1 USB 2.0 differential pair, position 1, positive

A7 DN1 USB 2.0 differential pair, position 1, negative

A8 SBU1 Sideband use (SBU)

A9 VBUS Bus power

A10 SSRXn2 SuperSpeed differential pair #2, RX, negative (NOT USED)

A11 SSRXp2 SuperSpeed differential pair #2, RX, positive (NOT USED)

A12 GND Ground return

SAMA5D27 SOM1 Kit1



B12 GND Ground return

B11 SSRXp1 SuperSpeed differential pair #1, RX, positive (NOT USED)

B10 SSRXn1 SuperSpeed differential pair #1, RX, negative (NOT USED)

B9 VBUS Bus power

B8 SBU2 Sideband use (SBU)

B7 DN2 USB 2.0 differential pair, position 2, negative

B6 DP2 USB 2.0 differential pair, position 2, positive

B5 CC2 Configuration Channel

B4 VBUS Bus power

B3 SSTXn2 SuperSpeed differential pair #2, TX, negative (NOT USED)

B2 SSTXp2 SuperSpeed differential pair #2, TX, positive (NOT USED)

B1 GND Ground return

USB-B Power SwitchThe USB-B Host port is equipped with a 500 mA high-side power switch for self-powered and bus-powered applications. If the client device is bus-powered, the carrier can supply a 5V, 500mA power tothe client device. The USBB_EN_5V_PA27 signal controls the power switch and current limiter, theMicrochip MIC2025, which in turn supplies power to a bus-powered client device. Per the USBspecification, bus-powered USB 2.0 devices are limited to a maximum of 500 mA. The MIC2025 limits thecurrent and indicates an overcurrent with the USBB_OVCUR_PD19 signal.

Figure 4-25.USB-B Power Switch

EN: Active HighUSBB_POWR_EN

USBB_OVCUR

USBB_VBUS_5V

VDD_MAIN_5V

VDD_3V3

PD19

PA27

R13810K

U13

MIC2025

EN1

FLG2

NC14

OUT_28

OUT_16

GND3

IN7

NC25

C6710uF

L12

180ohm at 100MHz

1 2

C68100nF

C66100nF

R7710K

Table 4-13.Power Switch PIO Signal Descriptions


PA27 USBB_POWR_EN USBB_EN_5V Power switch enable(active high)

PD19 USBB_OVCUR Indicates overcurrent(open drain)

4.2.7.5 HSIC InterfaceHigh-Speed Inter-Chip (HSIC) is a standard for USB chip-to-chip interconnect with a 2-signal (strobe,data) source synchronous serial interface using 240 MHz DDR signaling to provide only high-speed 480Mbps data rate.

The interface operates at high speed, 480 Mbps, and is fully compatible with existing USB softwarestacks. It meets all data transfer needs through a single unified USB software stack.

SAMA5D27 SOM1 Kit1


The HSIC interface is connected to two-point header J18. This connector is not mounted.

Figure 4-26.HSIC Interface J18Top/BotTop/Bot HSIC_DATAHSIC_STRB

J18

TSW-102-07-G-SDNP

12

4.2.7.6 CAN InterfaceThis section lists the signals related to the Controller Area Network (CAN) interface.

The CAN interface transmits and receives signals from the SOM. CAN PIOs PC26 and PC27 areconnected to the CAN transceiver (ATA6561) and the output signals from the transceiver are connectedto the screw connector (J16) physically located on top of the baseboard.

Figure 4-27.CAN Interface

CANTX1

CANRX1

VDD_3V3

VDD_MAIN_5V

PC26

PC27

U12

ATA6561-GBQW

TXD1

GND2

VCC3

RXD4

VIO5

CANL6CANH7

STBY8

PAD9

R6662R

C59100nF

R680R

C61100nF

J16

Screw 3x1

1

2

3

R6762R

C604.7uF

R650R

C6215pF

Figure 4-28.CAN Connector J16 Location

SAMA5D27 SOM1 Kit1


Table 4-14.CAN Connector J16 Pin Assignment

Pin Mnemonic Signal Description

1 CANH Differential positive

2 CANL Differential negative

3 GND Ground

4.3 External Interfaces

4.3.1 LCD TFT InterfaceThe baseboard provides a FPC connector with 24 bits of data and control signals to the LCD interface.Other signals are used to control the LCD and are available on connector J26: TWI, SPI, two GPIOs forinterrupt, 1-wire and power supply lines.

This connector is used to connect LCD display type TM43xx series or TM7000 series from PDA Inc(www.pdaatl.com).

A 50-pin FPC (J26) header is provided on the baseboard to interface the LCD module with 24-bit parallelRGB.

The connector provides two PIOs as interrupts, one SPI and a TWI port to interface the MaXTouch touchcontroller or QTouch button controller embedded on the LCD module.

In order to operate correctly out of the processor with various LCD modules, two voltage lines areavailable: 3.3V and 5VCC (default). Both are selected by 0R resistors R81 and R83.

Figure 4-29.LCD Expansion Header Interface

SPI0_ SPCKSPI0_ MOSISPI0_ MISOSPI0_NPCS0

LCDDAT0

LCDDAT6LCDDAT5LCDDAT4


LCDDAT11LCDDAT10LCDDAT9LCDDAT8

LCDDAT7

LCDDAT16




LCDDENLCDHSYNCLCDVSYNCLCDPCK

LCDDAT23

IRQ1IRQ2LCDPWM

LCDDISPTWD_LCDTWCK_LCD

VDD_3V3VDD_MAIN_5V

PB12PB13PB14

PB15PB16PB17PB18

PB19PB20PB21PB22

PB23PB24PB25PB26

PB27PB28PB29PB30

PB31PC0PC1PC2

PC5PC6

PC7

PC8PA14

PC4

PA15PA16PA17

PD1PC25

LCD_PWM_PC3

NRST

PB11

PA17

J26

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950

5251

R81 0R DNP

R119 100R

R85 0R

R83 0R

SAMA5D27 SOM1 Kit1


http://www.pdaatl.com

Figure 4-30.LCD Connector J26 Location

The table below describes the pin assignment of LCD connector J26.

Table 4-15.LCD Connector J26 Pin Assignment

Pin No Signal PIO Signal RGB Interface Function

1 ID PA17 ID Shared with SPI_NPCS0 pin 40

2 GND GND GND GND

3 LCDDAT0 PB11 D0 Data line (BLUE0)




7 GND GND





12 GND GND GND

SAMA5D27 SOM1 Kit1



13 LCDDAT8 PB19 D8 Data line (GREEN0)




17 GND GND





22 GND GND GND

23 LCDDAT16 PB27 D16 Data line (RED0)




27 GND GND


29 LCDDAT21 PC0 D21 Data line (RED5)



32 GND GND GND

33 LCDPCK PC7 PCLK Pixel clock

34 LCDVSYNC PC5 VSYNC/CS Vertical sync

35 LCDHSYNC PC6 HSYNC/WE Horizontal sync

36 LCDDEN PC8 DATA_ENABLE Data enable

37 SPI_SPCK PA14 SPI_SCK SPI clock

38 SPI_MOSI PA15 SPI_MOSI SPI Master OUT Slave IN

39 SPI_MISO PA16 SPI_MISO SPI Master IN Slave OUT

40 SPI_NPCS0 PA17 SPI_CS SPI chip select

41 LCDDISP PC4 ENABLE Display enable signal

42 TWD PD4 TWI_SDA I2C data line (maXTouch)

43 TWCK PD5 TWI_SCL I2C clock line (maXTouch)

44 GPIO PD1 IRQ1 maXTouch interrupt line

SAMA5D27 SOM1 Kit1



45 GPIO PC25 IRQ2 Interrupt line for other I2C devices

46 LCDPWM PC3 PWM Backlight control

47 RESET nRST RESET Reset for both display and maXTouch

48 Main_5V/3V3 VCC VCC 3.3V or 5V supply (R81/R83 selected)

49 Main_5V/3V3 VCC VCC 3.3V or 5V supply (R81/R83 selected)

50 GND GND GND GND

4.3.2 Image Sensor (ISC) InterfaceThis section describes the signals and connectors related to the ISC interface.

The Image Sensor Controller (ISC) system manages incoming data from a parallel or serial CSI-2 basedCMOS/CCD sensor. The system supports a single active interface, as well as the ITU-R BT 656/1120 422protocol with an 8-bit or 10-bit data width and raw Bayer format. The internal image processor includesadjustable white balance, color filter array interpolation, color correction, gamma correction, 12-bit to 10-bit compression, programmable color space conversion, as well as horizontal and vertical chrominancesubsampling module.

Figure 4-31.ISC Interface

ISC_D10ISC_D8ISC_D6ISC_D4ISC_D2ISC_D0ISC_PCKISC_HSYNCISC_VSYNCISC_MCK

ISC_PWD

ISC_D11ISC_D9ISC_D7ISC_D5ISC_D3

ISC_RST

ISC_D1

TWD_ISC

PC22

PC21

PC19

TWCK_ISC

PC18PC20

VDD_3V3

PC9PC10 PC11PC12 PC13PC14 PC15PC16 PC17

PC23

PC24

PD6 PD7

J27

TSW-115-07-G-D

1 23 45 67 89 10

11 1213151719

14161820

21 2223 2425 2627 2829 30

SAMA5D27 SOM1 Kit1


Figure 4-32.ISC Connector J27 Location

The table below describes the pin assignment of ISC connector J27.

Table 4-16.ISC Connector J27 Pin Assignment

SAMA5D27 Signal Pin No Signal SAMA5D27

Function PIO PIO Function

3.3V power VDD_3V3 1 2 GND Ground

3.3V power VDD_3V3 3 4 GND Ground

Reset PD6 ISC_RST 5 6 ISC_PWD PD7 Powerdown

TWI clock PD5 TWCK_ISC 7 8 TWD_ISC PD4 TWI data

Ground GND 9 10 ISC_MCK PC24 Masterclock

Ground GND 11 12 ISC_VSYNC

PC22 Verticalsync

Ground GND 13 14 ISC_HSYNC

PC23 Horizontalsync

Ground GND 15 16 ISC_PCK PC21 Clock

SAMA5D27 SOM1 Kit1


SAMA5D27 Signal Pin No Signal SAMA5D27


Ground GND 17 18 ISC_D0 PC9 Data0

Data1 PC10 ISC_D1 19 20 ISC_D2 PC11 Data2





Data11 PC20 ISC_D11 29 30 GND Ground

Note: ISC and LCD share the same TWI interface.

4.3.3 RGB LEDThe baseboard features one RGB LED which can be controlled by the user. The three LED cathodes arecontrolled via GPIO PWM or timer/counter pins.

Figure 4-33.RGB LED Indicators

LED_Red

LED_Green

LED_blue

VDD_3V3

PB1

PA31

PA10

R74 2K2

R13710K

Q9BSS138

1

3

2

R136 100R

D5

RGB

Red1

Green4

Blue3

Anode2

Q10BSS138

1

3

2

Q8BSS138

1

3

2

R135 100R

R76 1K

R13310K

R134 100R

R75 2K2

Table 4-17. RGB LED PIOs

Signal Shared PIO Function

LED_RED PA10 TIOA1

LED_GREEN PWM MBUS1 PB1 PWML1

LED_BLUE PWM MBUS2 PA31 PWML0

4.4 Debugging CapabilitiesThe baseboard includes two main debugging interfaces to provide debug-level access to the SAMA5D2:

One UART through USB J-Link-CDC Two JTAG interfaces, one connected from the MPU using connector J11 and one through the J-

Link-OB interface USB port J10

SAMA5D27 SOM1 Kit1


4.4.1 Debug JTAGThis section describes the signals and connectors related to the JTAG interface.

A 10-pin JTAG header is provided on the baseboard to facilitate software development and debuggingusing various JTAG emulators. The interface signals have a voltage level of 3.3V.

Figure 4-34.JTAG Interface

JTAG_TDO

NRST

JTAG_TMS

JTAG_TDI

JTAG_TCK

RTCK_IN

VDD_3V3

VDD_3V3

R48100K

R47100K

R46100K

R51 100R

J11

FTSH-105-01-F-DV-K

1 23 45 67 89 10

R50 0RDNP

R12010K

Figure 4-35.JTAG Connector J11 Location

The table below describes the pin assignment of JTAG connector J11.

Table 4-18.JTAG/ICE Connector J11 Pin Assignment


1 VTref. 3.3V power This is the target reference voltage (main 3.3V).

2 TMS TEST MODE SELECT JTAG mode set input into target processor

3 GND Common ground

4TCK TEST CLOCK - Output timing signal,for synchronizing test logic and controlregister access

JTAG clock signal into target processor

SAMA5D27 SOM1 Kit1



5 GND Common ground

6 TDO JTAG TEST DATA OUTPUT - Serialdata input from the target JTAG data output from target processor

7 RTCK - Input return test clock signal fromthe target

Some targets with a slow system clock mustsynchronize the JTAG inputs to internal clocks. Inthe present case, such synchronization isunneeded and TCK is merely looped back intoRTCK.

8TDI TEST DATA INPUT - Serial data outputline, sampled on the rising edge of the TCKsignal

JTAG data input into target processor

9 GND Common ground

10 nRST RESET Active-low reset signal. Target processor resetsignal.

4.4.2 Embedded Debugger (J-Link-OB) InterfaceThe baseboard includes a built-in SEGGER J-Link-On-Board device. The functionality is implementedwith an ATSAM3U4C microcontroller in an LQFP100 package. The ATSAM3U4C provides JTAGfunctions and a bridge USB/Serial debug port (CDC). One dual LED D4 mounted on the baseboardshows the status of the J-Link-On-Board device.

J-Link-OB-ATSAM3U4C was designed in order to provide an efficient, low-cost, on-board alternative tothe standard J-Link.

The internal J-Link-OB connects to the target only after it receives a first command; otherwise, it remainsdisabled.

The USB J-Link-OB port is used as a secondary power source and as a communication link for thebaseboard, and derives power from the PC over the USB cable. This port is limited in most cases to 500mA. A single PC USB port is sufficient to power the baseboard.

SAMA5D27 SOM1 Kit1


Figure 4-36.J-Link-OB Interface

TRESIN

Top/BotTop/Bot

JLINKSAM3U

NRST_3U

TDI_3UTDO_3UTCK_3UTMS_3U

ENSPI

ENSPI

TRSTINTRSTOUT

TRESOUT

3U_PA26

LED1_3U

TDI_INTX_3U

TMS_IN

TCK_OUTTMS_OUT

TDO_INTDI_OUT

TCK_IN

TCK_OUT

LED2_3U

RX_3U

XinXout

Xout

Xin

VDDout

NRST

VDDout

3U_PA25

RTCK_IN

Xin

VDD_3V3_3U

VDD_3V3_3U

EARTH0

VDD_3V3_3U

VDD_3V3_3U

VDD_3V3_3U

VDD_3V3_3UVBUS_JLINK

VDD_3V3_3U

VDD_3V3_3U

NRST

C34100nF

R40 39R

D31N414812

C25 10nF

R139 0R

Y1

12MhzDNP

1

2 3

4

C334.7uF

R39 100K

C71100nF

R41 39R

C31100nF

R43 220RVBUS

SHD

DMDPID

GNDJ10

Micro AB

12345

8 6

11 7

9

10

R37 6K8

R34 10K

C40100nF

C27 10pF

C41100nF

U4ATSAM3U4CA-AU

VDD

ANA

1

ADVREF2

GN

DAN

A3

AD12BVREF4

PA22/PGMD125

PA306

PB3

7

PB4

8

VDD

CO

RE_

39

PA13/PGMD510

GN

D2

61

PA15/PGMD712

PA16/PGMD813

PA17/PGMD914

PB16

15PB

1516

PA18/PGMD1017

PA19/PGMD1118

PA20/PGMD1219

PA21/PGMD1320

PA23/PGMD1521

XIN3250

PA2423

PA2524

PA2625

PA0/PGMNCMD26

PA1/PGMRDY27

PA2/PGMNOE28

PA3/PGMNVALID29

PA4/PGMM030

PA5/PGMM131

PA6/PGMM232

NRST57

VDD

CO

RE_

434

GN

D1

35

VDD

IO_3

36

VDD

CO

RE_

559

DFSDM80

GN

D3

89

VDD

UTM

I79

VDD

IN53

FWUP42

ERASE43

TEST44

XIN75

XOUT3249

VDD

IO_4

22

TDI51

VDD

OU

T52

PA12/PGMD441

TDO/TRACESWO54

TMS/SWDIO55 TCK/SWCLK56

PA7/PGMM333

PB24

58

PA8/PGMD037

VDD

IO_2

60

PA14/PGMD611

PB23

62PB

2263

PB14

69

PB10

70PB

971

GN

DPL

L72

PB8

100

PB7

99PB

698

PB13

95PB

1294

PB11

93

PB2

92PB

191

PB0

90

PA10/PGMD239

VDD

IO_1

88

VDD

CO

RE_

187

PA3186

PA2985PA2884

VDD

CO

RE_

283

GN

DU

TMI

82

DFSDP81

DHSDM77

DHSDP76

NRSTB47

XOUT74

VDD

PLL

73

PA11/PGMD340

PA9/PGMD138

PB20

65PB

1966

PB18

67PB

1768

PB5

97

PA2796

PB21

64

VDD

BU45

GN

DBU

46

VBG78

JTAGSEL48

C45100nF

J812

C2610nF

R33 150R

C298.2pFDNP

C36100nF

L9

180ohm at 100MHz

1 2

R31100R

C43100nF

Green

Red

D4

Bi Color

C39100nF

C35100nF

C384.7uF

R42 220R

C32100nF

C30100nF

R30 100R

R36 0R DNP

C37100nF

BOT TOPSideSide

J6

pads on PCB

1 23 4

7 89 10

11 121315

1416

C42100nF

12Mhz

Y2

ASE-12.000MHZ-LC-TNC

1GND

2VCC

4OUT

3

R35 100R

C44100nF

R29 0R

C288.2pFDNP

4.4.2.1 Disabling J-Link-OB (ATSAM3U4C)Jumper J7 disables the J-Link-OB-ATSAM3U4C JTAG functionality. When the jumper is installed, itgrounds pin 25 (PA26) of the ATSAM3U4C that is normally pulled high.

Jumper J7 not installed: J-Link-OB-ATSAM3U4C is enabled and fully functional. Jumper J7 installed: J-Link-OB-ATSAM3U4C is disabled and an external JTAG controller can be

used through the 10-pin JTAG port J11.

Jumper JP9 disables only the J-Link functionality. The debug serial com port that is emulated through aCommunication Device class (CDC) of the same USB connector remains operational (if J9 is open).

Figure 4-37.Enabling/Disabling J-Link-OB and J-Link-CDC

Disable JLINK JTAGDisable JLINK CDC

3U_PA263U_PA25

VDD_3V3_3UVDD_3V3_3U

R3210K

J9

TSW-102-07-G-S

12

J7

TSW-102-07-G-S

12

R3810K

Jumper J7 disables the JTAG functionality only. The debug serial com port that is emulated through aCDC of the same USB connector remains operational.

When J7 is on and the J-Link-OB-ATSAM3U4C JTAG disabled, the JTAG function is available throughconnector J11. A quad analog switch (NLAS3899B) is used to select and isolate the JTAG interface.

Table 4-19.J-Link-OB and J-Link-CDC Jumper J7 Settings

Jumper J7 J-Link-OB JTAG MPU

Open Active Inactive

Closed Inactive Active

SAMA5D27 SOM1 Kit1


Table 4-20.J-Link-OB and J-Link-CDC Jumper J9 Settings

Jumper J9 J-Link-CDC

Open Active

Closed Inactive

Figure 4-38.JTAG Switch

SOM_TDI

SOM_TD0

SOM_TMS

SOM_TCKJTAG_TDI

3U_PA26 TCK_OUTTCK_IN

3U_PA26

TMS_OUTTMS_IN

TDI_OUTTDI_IN

TDO_IN

JTAG_TCK

JTAG_TDOJTAG_TMS

VDD_3V3_3U

PD28

PD29

PD30

PD27

R45 150R

U8

NLAS3899B

NCA1

CO

MA

16

GN

D6

NOD11

VCC

14N

OA

15

A B IN2

NC

D13

COMD12

NOB3

COMB4

NC

B5

C D IN10

NCC9

NO

C7

CO

MC

8

C48100nF

R44 150R

R49 150R

4.4.3 Hardware UART via J-Link-CDCIn addition to the J-Link-OB functionality, the ATSAM3U4C microcontroller provides a bridge to a debugserial port (UART DBGU) of the processor on a SOM board. The port is made accessible over the sameUSB connection used by JTAG by implementing Communication Device Class (CDC), which allowsterminal communication with the target device.

This feature is enabled only if microcontroller pin 24 (PIO PA25) is not grounded. The pin is normallypulled high and controlled by jumper J9.

Jumper J9 not installed: the J-Link-CDC is enabled and fully functional. Jumper J9 installed: the J-Link-CDC device is disabled.

The USB Communications Device Class (CDC) enables to convert the USB device into a serialcommunication device. The target device running USB-Device CDC is recognized by the host as a serialinterface (USB2COM, virtual COM port) without the need to install a special host driver (since the CDC isstandard). All PC software using a COM port work without modifications with this virtual COM port. UnderWindows, the device shows up as a COM port; under Linux, as a /dev/ACMx device. This enables theuser to use host software which was not designed to be used with USB, such as a terminal program.

Figure 4-39.Debug COM Port Isolation

DBGU_TXD

DBGU_RXDTX_3U

RX_3U

3U_PA25

VDD_3V3_3U

VDD_3V3_3U

PD3

PD2

C47100nF

U5

NL17SZ126

1 OE2 IN3 GND

4OUT

5VCC

C46100nF

U6

NL17SZ126

1 OE2 IN3 GND

4OUT

5VCC

SAMA5D27 SOM1 Kit1


Table 4-21.Debug COM Port PIOs Signal Descriptions


PD2 DBGU_RXD - Receive data

PD3 DBGU_TXD - Transmit data

Figure 4-40.J-Link-OB and CDC USB Connector J10 Location

The table below describes the pin assignment of USB connector J14.

Table 4-22.USB Connector J14 Pin Assignment


1 VBUS 5V power

2 DM Data minus

3 DP Data plus

4 ID Not used

5 GND Common ground

4.4.3.1 Baseboard Edge ConnectorThis connector (J6) is used to upgrade or download code to the ATSAM3U4C microcontroller JLINK-OB.The J-Link-OB software is factory-programmed.

4.5 PIO Usage on Expansion ConnectorsThis section describes the signals and connectors related to the PIO usage on expansion connectors.

SAMA5D27 SOM1 Kit1


The baseboard includes numerous peripherals. Many of these are connected to the GPIO block so thatthe I/O pins can be configured to carry out many alternative functions. This provides great flexibility toselect a function multiplexing scheme for the pins that satisfy the interface need for a particularapplication.

Note that most pins are configured as GPIO inputs, with a 100 Kohm pull-up resistor, after reset.

4.5.1 PIOBU InterfaceThe baseboard features eight tamper pins for static or dynamic intrusion detection, UART reception, andtwo analog pins for comparison.

For a description of intrusion detection, refer to the SAMA5D2 datasheet, chapter "Security Module".

Figure 4-41.PIOBU ConnectorPIOBU2PIOBU4PIOBU6PIOBU7

PIOBU3PIOBU5RXDCOMPP

COMPN

R113 330R

R118 0R

R111 330R

R114 330RR112 330R

R117 0RR115 0R

R110 330R

R116 330R

J31

FTS-105-01-L-DV

1 23 45 67 89 10

Figure 4-42.PIOBU Connector J31 Location

The table below describes the pin assignment of PIOBU connector J31.

SAMA5D27 SOM1 Kit1


Table 4-23. PIOBU Connector J31 Pin Assignment

Signal Pin No. Signal

PIOBU2 1 2 PIOBU3

PIOBU4 3 4 PIOBU5

PIOBU6 5 6 RXD

PIOBU7 7 8 COMPP

COMPN 9 10 GND

4.5.2 mikroBUS InterfacesThe SAMA5D27 SOM1 Kit1 hosts two pairs of 8-pin female headers acting as mikroBus interfaces. ThemikroBUS standard defines the main board sockets and add-on boards (a.k.a. "click boards") used forinterfacing microprocessors with integrated modules with proprietary pin configuration and silkscreenmarkings. The pinout consists of three groups of communication pins (SPI, UART and TWI), fouradditional pins (PWM, interrupt, analog input and reset) and two power groups (+3.3V and GND on theleft, and 5V and GND on the right 1x8 header).

Figure 4-43.mikroBUS1 Interface Connectors

TX_mBUS1RX_mBUS1INT_mBUS1PWM_mBUS1

RST_mBUS1AN_mBUS1

TWCK_mBUS1TWD_mBUS1MOSI_mBUS1

MISO_mBUS1SPCK_mBUS1NPCS1

VDD_3V3

VDD_MAIN_5V

PB1PB2PD25

PB0PB3PB4

J22

TSW-102-07-G-S

12

R800RDNP

J2512345678

J2412345678

SAMA5D27 SOM1 Kit1


Figure 4-44.mikroBUS1 Connectors J24 and J25 Location

The table below describes the pin assignment of mikroBUS1 connectors J24 and J25.

Table 4-24.mikroBUS1 Connectors J24 and J25 Pin Assignment

SAMA5D27

J24 Signal Pin No. J25 Signal

SAMA5D27


Analog input PD25 AN 1 1 PWM PB1 PWM

Reset PB2 RST 2 2 RST PB0 Interrupt

SPI clock PD0 SPCK 3 3 RX PB3 UART receive

SPI MISO PC30 MISO 4 4 TX PB4 UART transmit

SPI MOSI PC29 MOSI 5 5 TWCK PA23 TWI clock

SPI chip select PC28 NPCS 6 6 TWD PA24 TWI data

3.3VCC 3.3V 7 7 +5V NC 5V supply

GROUND GND 8 8 GND _ GROUND

SAMA5D27 SOM1 Kit1


Figure 4-45.mikroBUS2 Interface Connectors

TX_mBUS2RX_mBUS2INT_mBUS2PWM_mBUS2

RST_mBUS2AN_mBUS2

TWCK_mBUS2TWD_mBUS2

MISO_mBUS2MOSI_mBUS2

NPCS0SPCK_mBUS2

VDD_3V3

VDD_MAIN_5V

PA26PA31PD26PA25PD23PD24

R1090RDNP

J2912345678

J3012345678

J28

TSW-102-07-G-S

12

Figure 4-46.mikroBUS2 Interface Connectors J29 and J30 Location

The table below describes the pin assignment of mikroBUS2 connectors J29 and J30.

Table 4-25.mikroBUS2 Connectors J29 and J30 Pin Assignment

SAMA5D27

J29 Signal Pin No. J30 Signal

SAMA5D27


Analog input PD26 AN 1 1 PWM PA31 PWM

Reset PA26 RST 2 2 RST PA25 Interrupt

SPI clock PC31 SPCK 3 3 RX PD23 UART receive

SPI MISO PC30 MISO 4 4 TX PD24 UART transmit

SPI MOSI PC29 MOSI 5 5 TWCK PA23 TWI clock

SPI chip select PC28 NPCS 6 6 TWD PA24 TWI data

3.3VCC 3.3V 7 7 +5V NC 5V supply

GROUND GND 8 8 GND _ GROUND

SAMA5D27 SOM1 Kit1


4.5.3 Pmod InterfacePmod devices are Digilents line of small I/O interface boards that offer an ideal way to extend thecapabilities of programmable logic and embedded control boards. They allow sensitive signal conditioningcircuits and high-power drive circuits to be placed where they are most effective - near sensors andactuators.

The Pmod interface on the baseboard is a 6-pin connector. The 6-pin version provides four digital I/Osignal pins, one power pin and one ground pin.

Note: The Pmod interface is shared with the ISC interface. Thus, the ISC and Pmod interfaces cannotbe used at the same time.

Figure 4-47.Pmod Interface Connector

PMOD_3PMOD_2PMOD_1

PMOD_4

VDD_3V3

J21

SSQ-106-02-G-S-RA

123456

Figure 4-48.Pmod Connector J21 Location

4.5.3.1 Pmod ConfigurationA set of jumpers, J20 and J23, is used to configure this type of interface. The table below describes thejumper configuration to select one of the Pmod functions (SPI, TWI or USART).

SAMA5D27 SOM1 Kit1


Figure 4-49.Pmod Jumper Configuration

PMOD_1

PMOD_2Flexcom3_IO0_MOSI

PMOD_3

Flexcom3_IO3_NPCS0

PMOD_4Flexcom3_IO4_NPCS1

PC19 Flexcom3_IO1_MISO

PC20 Flexcom3_IO0_MOSI

PC21 Flexcom3_IO3_NPCS0

PC22 Flexcom3_IO4_NPCS1

PC18 Flexcom3_IO2_SPCK

Flexcom3_IO2_SPCK

Flexcom3_IO1_MISO

PC18

PC19

PC20

PC21

PC22

R82 39R

J23

TSW-103-07-G-S

123

J20

TSW-106-07-G-S

123456R84 22R

R87 22R

R86 22R

R88 22R

Figure 4-50.Pmod Jumpers J20 and J23 Location

Table 4-26.Pmod Configuration Mode

Jumper J20 Jumper J23 Selected Function

1-2, 3-4, 5-6 1-2 SPI

2-3, 4-5 TWI

1-2, 3-4, 5-6 2-3 USART

SAMA5D27 SOM1 Kit1


5. Installation and Operation

5.1 System and Configuration RequirementsThe SAMA5D27 SOM1 Kit1 requires the following:

Personal Computer USB cable (included in the kit box)

5.2 Baseboard SetupFollow these steps to verify proper operation of the kit:

1. Unpack the baseboard, taking care to avoid electrostatic discharge.2. Check the default jumper settings.3. Connect the USB Micro-AB cable to connector J10 (JLINK-OB).4. Connect the other end of the cable to a free port of your PC.5. Open a terminal (console 115200, N, 8, 1) on your Personal Computer.6. Reset the baseboard. A startup message appears on the console.

SAMA5D27 SOM1 Kit1


6. Errata

6.1 Incorrect NRST and WKUP Push Button MarkingsThe PCB silkscreen markings for push buttons PB1 (NRST) and PB2 (WKUP) were inverted. PB1/NRSTis actually located to the left of PB2/WKUP, as shown in the figure below. However, the producedbaseboards have been patched with stickers, which currently convey correct information to the user. Thisinformation is given in case the stickers get removed and/or to clarify the actual baseboards' appearanceversus the design files printouts.

Figure 6-1.NRST Push Button Location

NRST

SAMA5D27 SOM1 Kit1


7. Appendix: Schematics and LayoutsThis appendix contains the following schematics and layouts:

Title and Revision History Block Diagram PIO Muxing Table Power Supply SAMA5D27 - SOM JTAG and DBGU SD and QSPI Ethernet and USB Expansion and Connectors

Figure 7-1.Title and Revision History5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

030201

SHEET NAMESHEETSchematic: SAMA5D27-SOM1-EK1

0807060504

09

Power SupplyPIO MuxingBlock DiagramTitle & Revision History

Expansion & Connectors

SD & QSPIJTAG & DBUGSAMA5D27SOM

Ethernet & USB

DATESAMA5D27-SOM-BB_ REVA6 Mar 2017

REVISION DESCRIPTIONRevision History

Prototype ReleaseSAMA5D27-SOM1-EK1_REVB10 Aug 2017 New Release

REV DATEMODIF. DES. DATE VER.

SCALE 1/1 REV. SHEETINIT EDIT

19B

XX-XXX-XXPPn XXX

SAMA5D27-SOM1-EK1

06-MAR-17

Title & Revision History

A10-AUG-17PPnRevBB XXX XX-XXX-XX



19B

XX-XXX-XXPPn XXX

SAMA5D27-SOM1-EK1

06-MAR-17





19B

XX-XXX-XXPPn XXX

SAMA5D27-SOM1-EK1

06-MAR-17



SAMA5D27 SOM1 Kit1


Figure 7-2.Block Diagram5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

USB AOTG

POWER

5V INPUT

USB A,B,C

LCDConnector

ResetWAKE UP

PushButtons

ISCConnector

JTAG EmbeddeddebuggerUser LEDsPush Buttons PIO

CANinterface

PIO A,B,C,DPIO A,B,C,D

MICROCHIPATSAMA5D27-SOM1

PIO A

SD/MMC0CardInterface

SD/MMC1 SD

Cardinterface

Ethernet10/100M bps

Power rails

VBAT

USBDEVICE

JTAGConnectorSheet 6

Sheet 85V INPUT

Sheet 9 Sheet 8

Sheet 7

Sheet 8

Sheet 4

Sheet 4

PIO A

mikroBUS 1&2

USB BHost

USB CHSIC

PMU orSuper Cap

Sheet 4

Pmod

QSPIPIO B



29B

XX-XXX-XXPPn XXX

SAMA5D27-SOM1-EK1

06-MAR-17

Block Diagram




29B

XX-XXX-XXPPn XXX

SAMA5D27-SOM1-EK1

06-MAR-17

Block Diagram




29B

XX-XXX-XXPPn XXX

SAMA5D27-SOM1-EK1

06-MAR-17

Block Diagram


SAMA5D27 SOM1 Kit1


Figure 7-3.PIO Muxing Table5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

NANANANANANA

NANA

NA NASOM_TMS

PIODPIOD

TWD0TWCK0

NA

SOM_TD0

USBB_OVCURUSBA_VBUS_5V

PD31

SOM_TDI

PD21

PD16PD17PD18PD19PD20

PD30

PD23PD24PD25PD26

PD22

PD27PD28PD29

PD8

PD10

PD12PD13PD14

PD11

PD15

PD9 AN_mBUS1TX_mBUS2RX_mBUS2

BB_PWR_GOOD

SOM_TCKAN_mBUS2

PIO Muxing & Jumper setting

12

910

345678

11121314151617181920212223242526272829303132333435363738394041424344454647484950

NC



GND

GNDLCDDAT8LCDDAT9LCDDAT10LCDDAT11GNDLCDDAT12LCDDAT13LCDDAT14LCDDAT15

GND


GND

LCDDAT20LCDDAT21LCDDAT22LCDDAT23GND

IRQ2

TWD1

LCD

VCCVCC

GND

LCDDISP

LCDVSYNC

LCDDEN

SPI0_ MISO

SPI0_ SPCK

LCDDAT0

NRST

IRQ1TWCK1

LCDPWM

LCDHSYNC

LCDPCK

SPI0_ MOSI

SPI0_NPCS0

GNDSDMMC0_CDASDMMC0_CK

SDMMC0_DA5SDMMC0_DA4SDMMC0_DA3SDMMC0_DA2SDMMC0_DA1SDMMC0_DA0

SDMMC0_WPSDMMC0_VDDSEL USBB_POWR_EN


SPI0_NPCS0SPI0_ MISO

SPI0_ MOSISPI0_ SPCKSDMMC0_CD

TWCK_mBUS1&2SDMMC1_CKSDMMC1_DAT3SDMMC1_DAT2SDMMC1_DAT1SDMMC1_DAT0

SDMMC1_CDA

LED_Red RST_mBUS2INT_mBUS2TWD_mBUS1&2

LED_Green/PWM_mBUS1INT_mBUS1

LED_blue/PWM_mBUS2SDMMC1_CDUser Button

QSPI1_IO0QSPI1_CSQSPI1_SCKTX_mBUS1RX_mBUS1RST_mBUS1


QSPI1_IO2QSPI1_IO1

LCDDAT6LCDDAT5

LCDDAT4LCDDAT3

LCDDAT12LCDDAT11LCDDAT10LCDDAT9LCDDAT8LCDDAT7

LCDDAT17LCDDAT16LCDDAT15LCDDAT14LCDDAT13

LCDDAT21

QSPI1_IO3


LCDVSYNCLCDDISPLCDPWMLCDDAT23LCDDAT22

ISC_D6ISC_D5ISC_D4

ISC_D2ISC_D1ISC_D0LCDDENLCDPCKLCDHSYNC

CANRX1

ISC_D9ISC_D8ISC_D7

ISC_D3

SPCK_mBUS1&2NPCS0_mBUS1

MISO_mBUS1&2MOSI_mBUS1&2

PIOAPIOA

PIOC

PIOCPIOBPIOB

PA17PA18

PA21PA20PA19

PA16

PA24PA23PA22

PA27PA26

PA31

PA25

PA30PA29PA28

PB3PB4

PB0

PB5PB6PB7

PB1PB2

PB13

PB8

PB12PB11PB10PB9

PB15PB14

PB16PB17PB18

PC5

PC0PC1

PC7PC8PC9

PC2PC3PC4

PC10PC11PC12PC13

PC6

PC14PC15

PC16PC17

PC19PC20PC21

PC29

PC22PC23PC24PC25

PC18

PC31

PC26PC27PC28

PC30

PB19

PB21

PB29PB28

PB22PB23PB24

PB26

PB30

PB20

PB31

PB25

PB27PA11PA12

PA6PA7PA8PA9PA10

PA1PA2PA3PA4PA5

PA0

PA13PA14PA15

ISC_PCKISC_D11ISC_D10

IRQ2ISC_MCKISC_HSYNCISC_VSYNC

CANTX1

JUMPER DESCRIPTION

J2

J4J7

J1 CLOSE

USAGE USAGE USAGE USAGE USAGE

USAGE USAGE USAGE

PART DEFAULT FUNCTION

Disable JLINK JTAG

I VDD_3V3 Measurement

I VDDBU Measurement

Disable JLINK CDC

DBGU_TXDTWD_LCD_ISCTWCK_LCD_ISCISC_RST

IRQ1DBGU_RXD

ISC_PWD

NPCS1_mBUS2PD0

PD2PD3PD4PD5PD6

PD1

PD7

CLOSE

OPEN ERASE SAM3UOPEN

J8

J9Disable boot

OPENOPENJ13

I VDD_MAIN_5V Measurement

CLOSE

J22J28

POWER SELECTPOWER SELECT

CLOSECLOSE



39B

XX-XXX-XXPPn XXX

SAMA5D27-SOM1-EK1

06-MAR-17

PIO Muxing




39B

XX-XXX-XXPPn XXX

SAMA5D27-SOM1-EK1

06-MAR-17

PIO Muxing




39B

XX-XXX-XXPPn XXX

SAMA5D27-SOM1-EK1

06-MAR-17

PIO Muxing


SAMA5D27 SOM1 Kit1


Figure 7-4.Power Supply5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

(Super)-Capacitorenergy storage

BB_PWR_GOOD

Through Holes

System Button

SDMMC0_VDDSEL

NRST

WAKE UP

POWERON

OPTIONAL

IN=0: S1 ClosedIN=1: S2 Closed

VOUT1

VDDBU

VOUT2 VDD_SDHC_1V8

VDDIN_3V3

VOUT3 VDD_3V3

VBUS_JLINK

VDD_MAIN_5V

VOUT2

VOUT1

VOUT3

VDD_3V3

VBUS_USBA

VDDBU

VDDBU

VDDBU

VDD_MAIN_5V

VDDSDHC

VDD_3V3

VDD_SDHC_3V3

VDD_SDHC_3V3 VDD_SDHC_1V8

PD8

NRST

WKUPPA11

SHDN



49B

XX-XXX-XXPPn XXX

SAMA5D27-SOM1-EK1

06-MAR-17

Power Supply




49B

XX-XXX-XXPPn XXX

SAMA5D27-SOM1-EK1

06-MAR-17

Power Supply




49B

XX-XXX-XXPPn XXX

SAMA5D27-SOM1-EK1

06-MAR-17

Power Supply


R1300R

R8100K

U2

ADG849

S26

S14

IN1

D5

VDD

2G

ND

3

MH3PTH

1

C210uF

R126100KDNP

R23 100R

D1

BAT54C

31

2

Q1-2DMP2160

5

8 43

R9158K

Z2

11.1

R132100K

R16 10K

R131 0RDNP

R11309K

C15100nF

L2

180ohm at 100MHz

1 2

MH1PTH

1

C64.7uF

L1

180ohm at 100MHz

1 2

R21 0RDNP

J1TSW-102-07-G-S

1 2

R10 10K

L6

1uHQ2-2

DMP2160

5

8 43

R17 0RDNP

R25 0R

R12810K

R6301K

Q6BSS1381

3

2

Q7BSS1381

3

2

C4100nF

R129100K

J4TSW-102-07-G-S

1 2

R310K

MH4PTH

1

R571K5

C84.7uF

Z3

11.1

R19 0RDNP

R4 100R

C9100nF

U1

MIC23451

PVIN125

PVIN25

PVIN38

AVIN13

AVIN26

AVIN39

PG120

PG216

PG313

EN121

EN219

EN315

SW126

SW24

SW37

SNS122

SNS218

SNS312

FB123

FB217

FB314

PGN

D1

1

PGN

D2

2

PGN

D3

10

AGN

D1

11

AGN

D2

24

EP1

28

EP2

27

C310uF

R13 10K

R24 100R

MH2PTH

1

R2309K

C74.7uF

+ C140.2F/3.3V

L8

1uH

Q1-1DMP2160

2

716

R12110K

J2TSW-102-07-G-S

1 2

R7 10KDNPQ2-1

DMP2160

2

716

R1471K5

R22 0RDNP

R2610K

Z4

11.1

C104.7uF

R15 10KDNP

C510uF

R18 10K

Z1

11.1

R127 10K

L7

180ohm at 100MHz

1 2R12100KDNP

C13100nF

PB2

L3

1uH

PB3

PB1

D2

RB160M-60TR

L5

180ohm at 100MHz

1 2

R1100K

R20 100R

C1100nF

SAMA5D27 SOM1 Kit1


Figure 7-5.SAMA5D27 - SOM5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SDMMC0_DA4SDMMC0_DA5SDMMC0_DA6SDMMC0_DA7

SDMMC0_CD


SDMMC0_CKSDMMC0_CDA


SDMMC0_WP

SDMMC1_CD


SDMMC1_CK

SDMMC1_CDA


QSPI1_SCKQSPI1_CSQSPI1_IO0QSPI1_IO1QSPI1_IO2QSPI1_IO3

ISC_D11

ISC_D9

ISC_D7

ISC_D5

ISC_D3

ISC_RST

ISC_D1

ISC_D10

ISC_D8

ISC_D6

ISC_D4

ISC_D2

ISC_D0

ISC_PCK

ISC_HSYNCISC_VSYNC

ISC_MCK

ISC_PWD

TWD_LCD_ISCTWCK_LCD_ISC

SPI0_ SPCKSPI0_ MOSISPI0_ MISOSPI0_NPCS0

LCDDAT0

LCDDAT6LCDDAT5LCDDAT4LCDDAT3LCDDAT2LCDDAT1



LCDDAT22LCDDAT21


LCDDEN

LCDHSYNCLCDVSYNC

LCDPCK

LCDDAT23

IRQ1

IRQ2

LCDPWMLCDDISP

BB_PWR_GOOD

USBB_OVCURUSBA_VBUS_5V

TWD_mBUS1&2TWCK_mBUS1&2

SPCK_mBUS1&2MISO_mBUS1&2MOSI_mBUS1&2

NPCS0_mBUS1

NPCS1_mBUS2

CANTX1CANRX1

LED_Red

LED_blue

DBGU_TXDDBGU_RXD

INT_mBUS2

PWM_mBUS2

RST_mBUS2AN_mBUS2

TX_mBUS1RX_mBUS1

INT_mBUS1PWM_mBUS1

RST_mBUS1

AN_mBUS1

USBB_POWR_EN

SDMMC0_VDDSEL

SOM_TDISOM_TD0SOM_TMS

SOM_TCK

TX_mBUS2RX_mBUS2

LED_Green

TWD0TWCK0

User Button

PC3

SHDN

VDDIN_3V3

VDDBU

VDDSDHC

VDDIN_3V3

PC0

PA0PA1PA2PA3PA4PA5PA6PA7PA8PA9PA10PA11PA12PA13PA14PA15PA16PA17PA18PA19PA20PA21PA22PA23PA24PA25PA26

PA31PA28

PA30PA31

PC1PC2

PC4PC5PC6PC7PC8PC9PC10PC11PC12PC13PC14PC15PC16PC17PC18PC19PC20PC21PC22PC23PC24PC25PC26PC27PC28PC29PC30PC31

PB1PB2PB3PB4PB5PB6PB7PB8PB9PB10PB11PB12PB13PB14PB15PB16PB17PB18PB19PB20PB21PB22PB23PB24PB25PB26PB27PB28PB29PB30PB31

PD0PD1PD2PD3PD4PD5PD6PD7PD8

PD19PD20

PD23PD24PD25PD26PD27PD28PD29PD30

HSIC_DATAHSIC_STRB

USBB_DPUSBB_DM

USBA_DMUSBA_DP

NRST

WKUP

DISABLE_BOOT

TX+TX-

RX+RX-

ETH_LED0

PIOBU2

PIOBU4

PIOBU6PIOBU7

PIOBU3

PIOBU5

RXDCOMPPCOMPN

PIOBU1

PA27

LCD_PWM_PC3

PB0PB1

PD21PD21PD22

PA29

SHDN



59B

XX-XXX-XXPPn XXX

SAMA5D27-SOM1-EK1

06-MAR-17

SAMA5D27SOM




59B

XX-XXX-XXPPn XXX

SAMA5D27-SOM1-EK1

06-MAR-17

SAMA5D27SOM




59B

XX-XXX-XXPPn XXX

SAMA5D27-SOM1-EK1

06-MAR-17

SAMA5D27SOM


J32TSW-101-07-G-S

DNP

1

C212.2uFDNP

ATSAMA5D27-SOM1

U3E

DIS_BOOT126

CLK_AUDIO61 COMPN

64COMPP63

USBA_DP68

USBB_DM70

STROBE73

USBA_DM67

USBB_DP71

DATA74NRST

60

PIOBU133

PIOBU244

PIOBU348

PIOBU447

PIOBU546

PIOBU659

PIOBU745

RXD32

SHDN35

WKUP49

ETH-TXP41

ETH-TXM40

ETH-RXP38

ETH-RXM37

ETH-LED036

RFU0129

RFU1147

RFU2153

C17100nF

ATSAMA5D27-SOM1

U3A

PA0080

PA0176

PA0283

PA0381

PA0484

PA0585

PA0686

PA0779

PA0878

PA0977

PA1082

PA1187

PA1292

PA1391

PA14111

PA15109

PA16112

PA17108

PA18105

PA19101

PA20104

PA21103

PA22106

PA23102

PA2499

PA2597

PA26100

PA2790

PA2895

PA2996

PA3094

PA3193

ATSAMA5D27-SOM1

U3C

PC00145

PC01141

PC02146

PC03142

PC04136

PC05137

PC06140

PC07139

PC08138

PC092

PC109

PC11175

PC123

PC134

PC148

PC1512

PC16174

PC175

PC18172

PC196

PC2014

PC217

PC2211

PC23170

PC2413

PC25173

PC26115

PC27114

PC28117

PC29118

PC30120

PC31116

C162.2uFDNP

C18100nF

J5TSW-101-07-G-S

DNP

1

C24100nF

ATSAMA5D27-SOM1

U3B

PB01122

PB02124

PB03123

PB04125

PB05134

PB06127

PB07133

PB08128

PB09132

PB10135

PB11148

PB12151

PB13155

PB14150

PB15162

PB16154

PB17157

PB18152

PB19158

PB20156

PB21164

PB22161

PB23160

PB24168

PB25159

PB26169

PB27163

PB28167

PB29144

PB30165

PB31143

PB00119

ATSAMA5D27-SOM1

U3F

VDDBU55

VDDIN_3V3_116

VDDIN_3V3_217

VDDISC15

VDDSDHC65

GND_110

GND_218

GND_326

GND_431

GND_539

GND_642

GND_743

GND_850

GND_956

GND_1062

GND_1166

GND_1269

GND_1372

GND_1475

GND_1588

GND_1689

GND_1798

GND_18107

GND_19130

GND_20131

GND_21149

GND_22166

GND_23171

GND_24176

GND_01

C192.2uFDNP

R2810K

C22100nF

C232.2uFDNP

C20100nF

ATSAMA5D27-SOM1

U3D

PD00121

PD01113

PD0223

PD0324

PD0427

PD0521

PD0622

PD0725

PD0828

PD1958

PD2057

PD2119

PD2220

PD2330

PD2429

PD25110

PD2634

PD2753

PD2851

PD2952

PD3054

R27 39R

SAMA5D27 SOM1 Kit1


Figure 7-6.JTAG and DBGU5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

JTAG Interface

JTAG switches

TRESIN

JLINK-OB interface

SOM_TDI

SOM_TD0

SOM_TMS

SOM_TCK

Routing USB

Max trace-length mismatchbetween USB signals pairsshould be no greater than 3.8mm

90 ohms differential traceimpedance

Top/BotTop/Bot

DBGU_TXD

DBGU_RXD

Disable JLINK JTAGJLINKSAM3U

Disable JLINK CDC

Debug Com Port isolation

JTAG_TDO

NRST

JTAG_TMS

JTAG_TDI

NRST_3U

TDI_3UTDO_3UTCK_3UTMS_3U

JTAG_TDI

3U_PA26

ENSPI

ENSPI

TRSTINTRSTOUT

TRESOUT

3U_PA26

LED1_3U

TDI_INTX_3U

TMS_IN

TCK_OUTTMS_OUT

TDO_INTDI_OUT

TCK_IN

TCK_OUT

LED2_3U

RX_3U

TCK_OUTTCK_IN

3U_PA26

TMS_OUTTMS_IN

TDI_OUTTDI_IN

TDO_IN

XinXout

Xout

Xin

VDDout

JTAG_TCK

JTAG_TDOJTAG_TMS

NRST

JTAG_TCK

TX_3U

RX_3U

3U_PA26

VDDout

3U_PA25 3U_PA25

RTCK_IN

RTCK_IN

3U_PA25

Xin

VDD_3V3

VDD_3V3

VDD_3V3_3U

VDD_MAIN_5VVDD_3V3_3U

VDD_3V3_3U

EARTH0

VDD_3V3_3U

VDD_3V3_3U

VDD_3V3_3U

VDD_3V3_3U

VDD_3V3_3U

VDD_3V3_3U

VBUS_JLINK

VDD_3V3_3U

VDD_3V3_3U

VDD_3V3_3U

VDD_3V3_3U

VDD_3V3_3U

PD28

PD29

PD30

PD27

NRST

PD3

PD2



69B

XX-XXX-XXPPn XXX

SAMA5D27-SOM1-EK1

06-MAR-17

JTAG & DBUG




69B

XX-XXX-XXPPn XXX

SAMA5D27-SOM1-EK1

06-MAR-17

JTAG & DBUG




69B

XX-XXX-XXPPn XXX

SAMA5D27-SOM1-EK1

06-MAR-17

JTAG & DBUG


R3210K

R40 39R

C34100nF

C47100nF

C25 10nF

R48100K

D31N414812

R39 100K

C334.7uF

Y1

12MhzDNP

1

2 3

4

R139 0R

C492.2uF

C71100nF

C31100nF

R41 39R

J9

TSW-102-07-G-S

12

R37 6K8

VBUS

SHD

DMDPID

GNDJ10

Micro AB

12345

8 6

11 7

9

10

R43 220R

C40100nF

R46100K

R47100K

R45 150R

R34 10K

C41100nF

R51 100R

C27 10pF

R33 150R

C2610nF

U5

NL17SZ126

1 OE2 IN3 GND

4OUT

5VCC

J812

C45