Semiconductor Memories - users.jyu.fiusers.jyu.fi/~loberg/FYSE410slides/FYSE410LECTURE18.pdf · Character Generators. Stored Programs. Combinational Logic. Semiconductor Memories

Semiconductor Memories

Classification of Memory Devices

Introduction

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Read Write Memories Non Volatile RWM Read Only Memory

Static RAM

Dynamic RAM

Random Access Non-Random Access

FIFO

LIFO

Shift Register

EPROM

EEPROM

FLASH

Mask-programmed Programmable (PROM)

"Combinational Logic"

1

nm ×2ROM

n outputs (data) m inputs (address Ai = 2m combinations)

Mm =2

mm 2×decoder

0W1W

1−MW2−MW

0A1A

1−mA2−mA

Encoder

Memory matrix

0D1D1−nD 2−nD

n-bit data m-bit address

Linear, one-dimensional addressing Word-lines

Address lines

Data lines

mnmnmn

=><

ROM Cell

Wj

Di

memory core

To Sense Amplifiers

ROM (Read Only Memory)


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Linear Addressing

2

The Cell is designed so that a 0 or 1 is presented to the bit line Di upon activation of its word line Wj .

ROM Cell

Wj

Di

Diode-based ROM Cell

MOSFET-based ROM Cell

BJT-based ROM Cell

ROM Cell


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Diode-based ROM Cell

ROM Cell

Wj

Di

1 0 Wj

Di Di-1

Cell content is 1

Cell content is 0

R R ( ) DWjDi VVV −= 1)1(

CWj

CDi CDi-1

VD

Current

Disadvantage of the diode cell : No isolation between the word line Wj and the bit line Di .

The Wj driver must provide quite high current to charge capacitance Ctot .

∑=

+≈n

1iDiWj(max)tot CCC

n = number of data bits This approach works only for small memories.

Passive cell device

( And discharge CWj )


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ROM Cell

4


ROM Cell

Wj

Di

1 0

Wjtot CC ≈(max)

Word-line driver : Charge and discharge the word-line capacitance CWj .

NMOS transistor Qi : All output-driving current. Charge the bit-line capacitance CDi .

Active cell device

Wj

Di Di-1

Cell content is 1 Cell content

is 0

R R DD)1(Di VV ≈

CWj

CDi CDi-1

Current VDD

Qi

D

S

G

"Source follower implementation" OR ROM


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ROM Cell

5


ROM Cell

Wj

Di

0 1

Active cell device

Wj

Di Di-1

Cell content is 0

Cell content is 1

0V )0(Di ≈

CWj

CDi CDi-1

Current

VDD

D

S

G

DD)1(Di VV ≈

Pull-up devices

NOR ROM "Pull-down device implementation"

Qi Word-line driver : Charge and discharge the word-line capacitance CWj .

NMOS transistor Qi : Discharge the bit-line capacitance CDi .

NMOS

VDD

Default value of the output is 1 Good isolation between word and bit line


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ROM Cell

6

BJT-based ROM Cell

Used in early bipolar roms

Mask programmable connections

Multiple Emitter Transistor

Wj

Wj+1

Wj+2

Wj+3 D0 D1 D2

R

OR ROM

2m multiple-emiter transistors if linear addressing is used.

Wj

Wj+1

Wj+2

VDD

VDD

D0 D3 D1 D2

Wj+3


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ROM Cell

7

Only one mask layer, the contact mask, is used to program the memory array.

The precence of a metal contact to the bit line creates a 0-cell, while its absence indicate a 1-cell.

NOR ROM

Threshold programming

NOR ROM The threshold (VTO) of the transistor (1-cell) is selectively raised to value higher than the voltage swing of the word line Wj .

(VTO = 7V for 5V supply voltage)

Think about mass-production

Programming the ROM Cell


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8

mm 2×decoder

0W1W

1−MW2−MW

0A1A

1−mA2−mA

Memory matrix

0D1D7D 6D

8-bit data

m-bit address

M m = 2

long if m is large

short Aspect ratio of the memory is not close to the unity.

Problems

The shape of storage array is an unacceptable.

Solution is 2-dimensional addressing

X Y

Aspect ratio of the memory is close to the unity. Smaller decoders. An example of one-dimensional addressing

One-dimensional addressing


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A0 AK-1

K2N ⋅

K2N ⋅

Sense Amps/Drivers

Column decoder

Row

dec

oder

AK

Am-1

Km2 −

The number of word lines

Storage Cell

Bit line

Word line

N Output bits DN-1 - D0

An example of 2048 bit ROM (512x4 organization)

A6 A7

328424 3 =⋅=⋅

Sense Amps/Drivers

Row

dec

oder

A0

A5

6426 = The number of word lines

4 Output bits

D0

W0

W63

A8

D1 D2 D3

8X1 8X1 8X1 8X1

The number of bit lines

Four 8X1 Multiplexers

2k-bit memory

64 X 32 matrix

CS

Two-dimensional addressing


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Two 512 X 4-bit ROM One 512 X 8-bit ROM

A8 - A0

A8 - A0 A8 - A0

CS CS

D0 D3 D4 D7

D3 - D0 D3 - D0 512X4 512X4

Word Expansion


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A8 - A0

A8 - A0 A8 - A0

CS CS D3 - D0 D3 - D0 512X4 512X4

D0 D1 D2 D3

A8 - A0

CS D3 - D0 512X4

A8 - A0

CS D3 - D0 512X4

2-to

-4

deco

der A9

A10

0

3

2kX4-bit Address space "Glue logic"

Address Expansion


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Applications

Look-up Tables

Sequence Generators

Waveform Generators

Character Generators

Stored Programs

Combinational Logic


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13

Write Once device : OTP ROM (One Time Programmable)

This is most often accomplished by introducing fuses in the memory cell. (nichrome, polysilicon, or other conductors)

UV EPROM (NVRW memory) without erasing window. Cheap plastic package.

PROM Cell structure allows the customer to program the memory one time.

Programmable ROMS (PROMS)


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Nonvolatile Read-Write Memories

Introduction

14

NVRW memories The memory core consists of an array of modified transistors which are programmed by selectively disabling or enabling some of them.

The threshold of the transistor is altered electrically.

The memory must be erased before next programming round.

The Floating-Gate Transistor

Several Times Writable : NVRW memories (Nonvolatile Read-Write Memories)


Introduction


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Programmable ROMS (PROMS)

15

The structure is similar to a traditional MOS device, except that an extra polysilicon strip is inserted between the gate and channel.

Schematic Symbol

Programming

S

D

G

V20V20 Electrons are trapped on the floating gate.

It results in higher VTO

GATE FLOATING GATE

oxtoxt

+n +npSubstrate

Device cross-section of the FAMOS

Source Drain

2SiO

Floating-gate Avalanche-injection MOS Memory Cell Type (FAMOS)

Erasing

UV light


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16

UV-EPROM

EPROM is erased by shining ultraviolet light on the Cells through the transparent window in the package.

The example UV-EPROM chip

Cell Array

Pin 1 Pin 40

Pin Configuration

Typical programming time :

word/s105 µ−

Mainly because of UV erasing.

Erasing takes time typically up to 1 hour.

Ceramic Packages

"Off-system" erasure procedure.

Erasable-Programmable ROM (EPROM)


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Erase/Write cycles is generally limited to a maximum of one thousand.

17

Electrically-Erasable-Programmable ROM (EEPROM, E2PROM)

FLOTOX transistor

GATE FLOATING GATE

nm10

+n +npSubstrate

Source Drain

2SiO

nm3020−

Schematic Symbol

Memory Cell Type (FLOTOX)

The number of Erasing and Programming cycle is limited


©Loberg


18

Read-Write Memories

Read and Write time : Independent of memory location. Memory access time

Memory cycle time Minimum interval of time reguired between successive memory operations.

Volatile Nonvolatile Local Power

Supply

Inside the package

Large dimensions

Static RAM

Dynamic RAM

Static memory cell

Dynamic memory cell

CS

Basic one-transistor cell Needs refreshing

S

Q R

Q Q Q

Basic Storage Cells NMOS CMOS

Introduction


©Loberg 19

Linear selection Assumption :

S Q Read Data Out

R

Write Data In

Write Enable

X Address

Write Operation : Write Data In

Write Enable

X Address

0 1

S R Q 0 1

Read Data Out 0 1

Read Operation : Set X Address to 1.

Static RAM Cell


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Read-Write Memories

20

Static RAM Cell Linear selection

S Q

R

Write Data In DI

Write Enable WE

X Address

OC

Read Data Out DO

nxm dec.

DO DI

WE

+VCC

m x 1 organized RAM

iX

Address Lines


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Read-Write Memories

21

R

QQ

S

DDV+

S

Q R

Q NMOS NOR gates

R

QQ

S

DDV+

S

Q R

Q CMOS NOR gates


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Read-Write Memories

Static RAM Cell

22

iX1Q

DDV+

iX2Q

3Q 4Q5Q 6Q To R/W=1 of all

cells in column j To R/W=0 of all cells in column j

A static CMOS memory cell

Q Q

iX iX

The 6-MOS Memory Cell


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Read-Write Memories

Static RAM Cell

23

2-dimensional addressing of RAM Cell

0-0

1-0 1-1

0-1

127-0 127-1

1-127

0-127

127-127

7-to-128 column decoder

7-to

-128

row

dec

oder

A0-A6

A7-A13

To R/W 1 amplifiers

To R/W 0 amplifiers

X0

X1

X127

Y0 Y1 Y127

1-bit line for column 1

0-bit line for column 1


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Read-Write Memories

Static RAM Cell

24

2-dimensional addressing of RAM Cell

To R/W=1 of all cells in column 1


1X1Q

DDV+

1X2Q

3Q 4Q

5Q 6Q

7Q 8Q

13Q

15Q

1Y

DDV+

9Q

11Q 16Q

14Q

12Q

10Q

17Q

0-bit data line

1-bit data line

W0Write 1Write

W

W/R R/W 1 amplifiers R/W 0 amplifiers

Read 0 Read 1

1N 2N

Storage Cell (1-1) containing 6 NMOS transistors

Millman fig. 9-12

WE

Write 1

Write 0

Y1

X1

Read 0

Read 1

RAM Cell (1-1)

0-bit dataline 1-bit dataline

11917 Q,Q,Q

121017 Q,Q,Q

1513 Q,Q

1614 Q,Q


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Read-Write Memories

Static RAM Cell

25

WE

W

S

Write Enable

Write ( Data Input, Din )

Sense ( Data Output, Dout )

Assumption : Cell contains a bit 1

1Q2Q Conducts (ON)

(OFF)

V0VandVV 2NDD1N ≈≈



1X1Q

DDV+

1X2Q

3Q 4Q

5Q 6Q

7Q 8Q

13Q

15Q

1Y

DDV+

9Q

11Q 16Q

14Q

12Q

10Q

17Q

0-bit data line

1-bit data line

W0Write 1Write

W


Read 0 Read 1

S

WE

W

1N 2N

S

1 0 0 1


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Read-Write Memories

Static RAM Cell Cell contains a bit 1

26

Assumption : Cell contains a bit 0

1Q2Q

Conducts (ON)

(OFF)

V0VandVV 1NDD2N ≈≈



1X1Q

DDV+

1X2Q

3Q 4Q

5Q 6Q

7Q 8Q

13Q

15Q

1Y

DDV+

9Q

11Q 16Q

14Q

12Q

10Q

17Q

0-bit data line

1-bit data line

W0Write 1Write

W


Read 0 Read 1 S

WE

W

0 1 0 1

1N 2N

W


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Read-Write Memories

Static RAM Cell Cell contains a bit 0

27

READ CYCLE

0WE =

caret'don1Write0Write ==

⇒

17Q ( OFF )

Due to the current through Q8 and Q4, the voltage drop over Q12 is practicaly VDD .

1S =



1X1Q

DDV+

1X2Q

3Q 4Q

5Q 6Q

7Q 8Q

13Q

15Q

1Y

DDV+

9Q

11Q 16Q

14Q

12Q

10Q

17Q

0-bit data line

1-bit data line

W0Write 1Write

W


Read 0 Read 1

S=1

WE=0

W

1N 2N

S=0

1 0 0 1

off

1 0

0

Current to the Ground

1 1

1

1

0

Voltage Drop over Q12

W

Zero Current

14Q (OFF) ⇒

V0V 14GS ≈

1YX 11 ==


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Read-Write Memories

The Read Cycle of the (1-1) RAM Cell (2-dimensional addressing) Static RAM Cell

28

WRITE CYCLE

0W,1Wand1WE ===

1YX 11 ==

( )57681017 QQQQQQ ( ON )



1X1Q

DDV+

1X2Q

3Q 4Q

5Q 6Q

7Q 8Q

13Q

15Q

1Y

DDV+

9Q

11Q 16Q

14Q

12Q

10Q

17Q

0-bit data line

1-bit data line

W0Write 1Write

W


Read 0 Read 1

S

WE=1

W=1

1N 2N

S

1 0 0 1

off

1 0

0

Current to the Ground

1 1

1

1

0


W=0

Zero Current

( 1 to Cell )

on on


on

on on V0V 2N ≈ ⇒ OFFQ1 =

DD1N VV ≈

0WE0YX 11

===End of WR-cycle

8765 QQQQ ( OFF )

ONQOFFQ 21 == Cell=1


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Read-Write Memories

The Write (-1-) Cycle of the (1-1) RAM Cell (2-dimensional addressing) Static RAM Cell

29

One-MOSFET Dynamic RAM-Cell

C1

iX

jY

To R/W amplifiers

Data bit or Column line

Row line

C2

Basic one-transistor cell

One data bit line ( )1VYX ji ==WRITE CYCLE

Data bit line : ( ) ( )1VV1V 1C =⇒

Data bit line : ( ) ( )0VV0V 1C =⇒

( )1VYX ji ==READ CYCLE

Write amplifier set the level of the data bit line

The read amplifier (sense amp.) detects the voltage level of the data bit line: 1C

21

1 VCC

CV+

=

112 VVCC <<⇒>>

is capacitance of the data bit line

Where 2C

Read cycle destroys the content of memory cell Write original content back

Leackage current Refresh time ms


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Read-Write Memories

Dynamic RAM Cell

30

The End

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Semiconductor Memories - users.jyu.fiusers.jyu.fi/~loberg/FYSE410slides/FYSE410LECTURE18.pdf · Character Generators. Stored Programs. Combinational Logic. Semiconductor Memories