Visit www.gansystems.com for the latest version of this user’s guide.

This evaluation kit is designed for engineering evaluation in a controlled

lab environment and should be handled by qualified personnel ONLY.

High voltage will be exposed on the board during the test and even brief

contact during operation may result in severe injury or death.

Never leave the board operating unattended. After it is de-energized,

always wait until all capacitors are discharged before touching the board.

This product contains parts that are susceptible to damage by electrostatic

discharge (ESD). Always follow ESD prevention procedures when

handling the product.

The GS665XXX-EVBDB daughter board style evaluation kit consists of two GaN Systems 650V GaN

Enhancement-mode HEMTs (E-HEMTs) and all necessary circuits including half bridge gate drivers,

isolated power supplies and optional heatsink to form a functional half bridge power stage. It allows

users to easily evaluate the GaN E-HEMT performance in any half bridge-based topology, either with the

universal mother board (P/N: GS665MB-EVB) or users’ own system design.

Serves as a reference design and evaluation tool as well as deployment-ready solution for easy in-

system evaluation.

Vertical mount style with height of 35mm, which fits in majority of 1U design and allows

evaluation of GaN E-HEMT in traditional through-hole type power supply board.

Current shunt position for switching characterization testing

Universal form factor and footprint for all products

The daughter board and universal mother board ordering part numbers are below:

Part Number GaN E-HEMT P/N: Description

GS66502B-EVBDB GS66502B GaN E-HEMT 650V/7.5A, 200mΩ

GS66504B-EVBDB GS66504B GaN E-HEMT 650V/15A, 100mΩ

GS66508B-EVBDB GS66508B GaN E-HEMT 650V/30A, 50mΩ

GS66508T-EVBDB GS66508T GaN E-HEMT top side cooled 650V/30A, 50mΩ

GS66516T-EVBDB GS66516T GaN E-HEMT top side cooled 650V/60A, 25mΩ

GS665MB-EVB Universal 650V Mother Board

The daughter board GS665XXX-EVBDB circuit diagram is shown in Figure 1. The control logic inputs on

2x3 pin header J1 are listed below:

Pin Descriptipon

ENA Enable input. It is internally pulled up to VCC, a low logic disables all the PWM gate

drive outputs.

VCC +5V auxillary power supply input for logic circuit and gate driver. On the daughter

board there are 2 isolated 5V to 9V DC/DC power supplies for top and bottom switches.

VDRV Optional 9V gate drive power input. This pin allows users to supply separate gate drive

power supply. By default VDRV is connected to VCC on the daughter board via a 0 ohm

jumper FB1. If bootstrap mode is used for high side gate drive, connect VDRV to 9V

PWMH High side PWM logic input for top switch Q1. It is compatible wth 3.3V and 5V

PWML Low side PWM logic input for bottom switch Q2. It is compatible wth 3.3V and 5V

0V Logic inputs and gate drive power supply ground return.

The 3 power pins are:

VDC+: Input DC Bus voltage

VSW: Switching node output

VDC-: Input DC bus voltage ground return. Note that control ground 0V is isolated from VDC-.

Si8271 Iso.

Gate DriverQ1

Q2Si8271 Iso.

Gate Driver

Iso. DC/DC

or Bootstrap

Iso. DC/DC

VDC+

VSW

VDC-

VCC

ENABLE

JP1

C4-10

PWMH

PWML

A. 2x GaN Systems 650V E-HEMT GS66508B, 30A/50mΩ

B. Decoupling capacitors C4-C11

C. Isolated gate driver Silab Si8271GB-IS

D. Optional current shunt position JP1.

E. Test points for bottom Q2 VGS.

F. Recommended probing positions for Q2 VDS.

G. Optional bootstrap circuit D1/R1 (unpopulated).

H. 5V-9V isolated DC/DC gate drive power supply

This daughter board includes two GaN Systems E-HEMT GS66508B (650V/30A, 50mΩ) in a

GaNPx™ B type package. The large S pad serves as source connection and thermal pad. The pin

4 is the kelvin source connection for gate drive return.

Silab Si8271GB-IS isolated gate driver is chosen for this design. This driver is compatible with 6V

gate drive with 4V UVLO and has CMTI dv/dt rating up to 200V/ns. It has separated source and

sink drive outputs which eliminates the need for additional diode.

GaN E-HEMT switching speed and slew rate can be directly controlled by the gate resistor. By

default the turn-on Rgate (R6/R12) is 10Ω and Rg_off (R7/R14) is 1Ω. User can adjust the values

of gate resistors to fine tune the turn-on and off speed.

FB1/FB2 are footprints for optional ferrite bead. By default they are populated with 0Ω jumpers.

If gate oscillation is observed, it is recommended to replace them with ferrite bead with Z=10-

20Ω@100MHz.

5V-9V isolated DC/DC converters are used for gate drive. 9V output is then regulated down to

6V for gate driver.

By default gate drive supply input VDRV is tied to VCC +5V via 0Ω jumper (FB1). Remove FB1 if

separate gate drive input voltage is to be used.

The board has option for users to experiment with non-isolated bootstrap circuit with following

circuit changes:

o Remove PS2 and short circuit pin 2 to 5 and pin 1 to 4.

o Populate D1/ R1 (not supplied): D1 is the high voltage bootstrap diode (for example ES1J)

and use 1-2Ω 0805 SMD resistor on R1. Depopulate PS1, LED1 and replace C2 with 1uF

capacitor.

o Remove 0Ω jumper at FB1 and supply +9V at VDRV.

U2

SI8271GB-IS

VI1

VDDI2

GNDI3

EN4

GNDA5

VO-6

VO+7

VDD8PWMH

R83.3K

Q1G

ENABLE

FB2

0R

Q1

GS66508B

1

2

4

3

R6

10R

R7

1R

Q1_GOUT

PWMH_INR5

10R Q1_VO+

Q1_VO-

GNDH

C12

1uF

VDDH_+6V

C131uF

VCC_+5V

0V

The board provides an optional current shunt position JP1 between the source of Q2 and power

ground return. This allows drain current measurement for switching characterization test such as

Eon/Eoff measurement.

The JP1 footprint is compatible with T&M Research SDN series coaxial current shunt

(recommended P/N: SDN-414-10, 2GHz B/W, 0.1Ω)

If current shunt is not used JP1 must be shorted. JP1 affects the power loop inductance and its

inductance should be kept as low as possible. Use a copper foil or jumper with low inductance.

D1

600V 1ADO-214AC

R1

0RR0805

DNPDNP

PS1

PES1-S5-S9-M

GND1

VIN2

+VO5

0V4

NC

8

U1

LP2985IM5-6.1IN

1

GN

D2

ON/OFF3

BYP4

OUT5

GNDH

0V

VDRV

C14.7uFC0805

VDDH_+6V

C34.7uFC0805

GNDH

R43.3K

C24.7uFC0805

R33.3K

LED1

LED-0603

VDDH_+9V

PS2

PES1-S5-S9-M

GND1

VIN2

+VO5

0V4

NC

8

GNDL

U3

LP2985IM5-6.1IN

1

GN

D2

ON/OFF3

BYP4

OUT5

0V

VDRV

C144.7uFC0805

VDDL_+6V

C154.7uFC0805

GNDL

C164.7uFC0805

R93.3K

LED2

LED-0603

VDDL_+9V

FB1

0R

VDRV VCC_+5V

R103.3K

1. When measuring VSW with current shunt, ensure all channel probe grounds and current shunt

BNC output case are all referenced to the source end of Q2 before the current shunt. The

recommended setup of probes is shown as below.

2. The output of coaxial current shunt can be connected to oscilloscope via 50Ω termination

impedance to reduce the ringing.

3. The measured current is inverted and can be scaled by using: Id=Vid/Rsense.

1. GS66508B has a thermal pad at the bottom side for heat dissipation. The heat is transferred to the

bottom side of PCB using thermal vias and copper plane.

2. A heatsink (35x35mm size) can be attached to the bottom side of board for optimum cooling.

Thermal Interface Material (TIM) is needed to provide electrical insulation and conformance to

VGL

VSL

VSW

BNC case

To oscilloscope

probe input (use

50Ω termination)

BNC tip

VDS

VGS

ID

the PCB surface. The daughter board evaluation kit supplies with a sample 35x35mm fin heatsink

(not installed), although other heatsinks can also be used to fit users’ system design.

3. A thermal tape type TIM (Berguist® Bond-Ply 100) is chosen for its easy assembly. The supplied

heatsink has the thermal tape pre-applied so simply peel off the protective film and attach the

heatsink to the back of board as marked in Figure 3.

4. Two optional mounting holes as shown in Figure 9 are provided for mounting customized

heatsink using screws.

5. Using the supplied heatsink and TIM, the overall junction to ambient thermal resistance RthJ-A is

~9°C/W with 500LFM airflow.

6. Forced air cooling is recommended for power testing.

°

GaN Systems provides a universal 650V mother board (ordering part number: GS665MB-EVB, sold

separately) that can be used as the basic evaluation platform for all the daughter boards.

The universal 650V mother board evaluation kit includes following items:

1. Mother board GS665MB-EVB

2. 12VDC Fan

The board can be powered by 9-12V on J1. On-board voltage regulator creates to 5V for daughter board

and control logic circuits. J3 is used for external 12VDC fan.

12V INPUT

(+)5V Power Supply

CIN

VSW

PWM control & dead

time circuit

Daughter Board

Probing point for VSW

For Ext.

12VDC Fan

Airflow direction

Optional CoutVDC- VOUT

VDC-

VDC+

The top and bottom switches PWM inputs can be individually controlled by two jumpers J4 and J6. Users

can choose between a pair of complementary on-board internal PWM signals (non-inverted and inverted,

controlled by J7 input) with dead time or external high/low side drive signals from J5 (users’ own control

board).

An on-board dead time generation circuit is included on the mother board. Dead time is controlled by

two RC delay circuits, R6/C12 and R5/C11. The default dead time is set to about 100ns. Additionally two

potentiometers locations are provided (TR1/TR2, not included) to allow fine adjustment of the dead time

if needed.

0V

D1 PMEG2005EB

SOD523

R6

1K00

TR12K C11100pF

0V

R5

1K00

C10

1uF

C9

0.1uF

+5V

J7112538

1

2345

R4100RR1206

R2100RR1206

U2A

74VHC132

31

2

14

7

0V

R1

49R9

0V

D2 PMEG2005EB

SOD523

TR22K

C12100pF

0V

U2B

74VHC132

4

56

U2C

74VHC132

9

108

U2D

74VHC132

12

1311

TP7

TP8

DNP

DNP

PWM OUTPUT

INVERTED PWM OUTPUT

R3

49R9

DNPDNP

R7

49R9

Test points are designed in groups/pairs to facilitate probing:

Test points Name Description

TP1/TP2 +5V/0V 5V bias power

TP7/TP8 PWMIN/0V PWM input signal from J7

TP4/TP3/TP13 PWMH/PWML/0V High/low side gate signals to daughter board

TP9/TP10 VDC+/VDC- DC bus voltage

TP11/TP12 VOUT/VDC- Output voltage

TP6/TP5 VSW/VDC- Switching node output voltage (for HV oscilloscope

probe)

CON1-CON7 mounting pads are designed to be compatible with following mounting terminals:

#10-32 Screw mount,

Banana Jack PCB mount (Keystone P/N: 575-4), or

PC Mount Screw Terminal (Keystone P/N: 8191)

An external power inductor (not included) can be connected between VSW (CON1) and VOUT (CON4/5)

or VDC+ (CON2/3) for double pulse test. Users can choose their inductor size to meet the test

requirement. Generally it is recommended to use power inductor with low inter-winding capacitance to

obtain best switching performance. For the double pulse testing we use 2x 60uH/40Amp inductor (CWS,

P/N: HF467-600M-40AV) in series. C14 is designed to accommodate a film capacitor as output filter.

CON1

Q1

CON2

Q2

VDC-

CON4

CON3

LOUT

400V DC

+

VDC+

CON7CON6

VSW

CON5

+5V

0V

PWM

INPUT

(J7)

VDS

IL

ISW

VGL

+6V

0VVDS

VGL

IL

t0 t1 t2 t3TON1

Double pulse test allows easy evaluation of device switching performance at high voltage/current

without the need of actually running at high power. It can also be used for switching loss (Eon/Eoff)

measurement and other switching characterization parameter test.

The circuit configuration and operating principle can be found in Figure 13:

1. The output inductor is connected to the VDC+.

2. At t0 when Q2 is switched on, the inductor current starts to ramp up until t1. The period of first

pulse Ton1 defines the switching current ISW = (VDS*TON1) / L.

3. t1-t2 is the free wheeling period when the inductor current IL forces Q1 to conduct in reverse.

4. t1 (turn-off) and t2 (turn-on) are of interest for this test as they are the hard switching trasients for

the half bridge circuit when Q2 is under high switching stress.

5. The second pulse t2-t3 is kept short to limit the peak inductor current at t3.

The double pulse signal can be generated using programmable signal generaotor or microcontroller/DSP

board. As this test involves high switching stress and high current, it is recommended to set the double

pulse test gate signal as single trigger mode or use long repetition period (for example >50-100ms) to void

excess stress to the switches. Q1 can be kept off during the test or driven synchronously (J4 set to OFF or

INT_INV) and Q2 is set to INT (or EXT position if PWM signal is from J5).

CON1

Q1

CON2

Q2

VDC-

CON4

CON3

LOUT

400V DC

+

VDC+

CON7

CON6

VSW

CON5

COUT RLoad

This is standard half bridge configuration that can be used in

following circuits :

Synchronous Buck DC/DC

Single phase half bridge inverter

ZVS half bridge LLC

Phase leg for full bridge DC/DC or

Phase leg for a 3-phase motor drive

Jumper setting:

J4 (Q1): INT

J6 (Q2): INT_INV

CON1

Q1

CON2

Q2

VDC-

CON4

CON3

LIN

VDC+

CON7CON6

VSW

CON5

INPUT

VIN

When the output becomes the input and the load is

attached between VDC+ and VDC-, the board is

converted into a boost mode circuit and can be used for:

Synchronous Boost DC/DC

Totem pole bridgeless PFC

Jumper setting:

J4 (Q1): INT_INV

J6 (Q2): INT

The daughter board allows users to easily evaluate the GaN performance in their own systems. Refer to

the footprint drawing of GS665XXX-EVBDB as shown below:

1 3 5

2 4 6

78 9

1. All units are in mm.

2. Pin 1-6: Dia. 1mm

3. Pin 7-9: 1.91mm (75mil) mounting hole for Mill-max Receptacle P/N: 0312-0-15-15-34-27-10-0.

Follow the instructions below to quickly get started with your evaluation of GaN E-HEMT. Equipment

and components you will need:

Four-channel oscilloscope with 500MHz bandwidth or higher

high bandwidth (500MHz or higher) passive probe

high bandwidth (500MHz) high voltage probe (>600V)

AC/DC current probe for inductor current measurement

12V DC power supply

Signal generator capable of creating testing pulses

High voltage power supply (0-400VDC) with current limit.

External power inductor (recommend toroid inductor 50-200uH)

1. Check the JP1 on daughter board GS665XXX-EVBDB. Use a copper foil and solder to short JP1.

2. Install GS665XXX-EVBDB on the mother board. Press all the way down until you feel a click. Connect

probe between VGL and VSL for gate voltage measurement.

3. Set up the mother board:

a. Connect 12VDC bias supply to J1.

b. Connect PWM input gate signal (0-5V) to J7. If it is generated from a signal generator ensure

the output mode is high-Z mode.

c. Set J4 to OFF position and J7 to INT.

d. Set High voltage (HV) DC supply voltage to 0V and ensure the output is OFF. Connect HV

supply to CON2 and CON6.

e. Use HV probe between TP6 and TP5 for Vds measurement.

f. Connect external inductor between CON1 and CON3. Use current probe to measure inductor

current IL.

4. Set up and check PWM gate signal:

a. Turn-on 12VDC power.

b. Check the 2 LEDs on the daughter board. They should be turned on indicating the isolated

9V is present.

c. Set up signal generator to create the waveforms as shown in Figure 13. Use equation ISW =

(VDS*TON1) / L to calculate the pulse width of the first pulse and ensure the Isw_max is ≤30A at

400VDC.

d. Set the operation mode to either single trigger or Burst mode with repetition period of 100ms.

e. Turn on the PWM output and check on the oscilloscope to make sure the VGL waveform is

present and matches the PWM input.

5. Power-on:

a. Turn on the output of the HV supply. Start with low voltage and slowly ramp the voltage up

until it reaches 400VDC. During the ramping period closely observe the the voltage and

current waveforms on the oscilloscope.

6. Power-off:

a. After the test is complete, slowly ramp down the HV supply voltage to 0V and turn off the

output. Then turn off the 12V bias supply and signal generator output.

Figure 16 shows the hard switching on waveforms at 400V/30A. A Vds dip can be seen due to the rising

drain current (di/dt in the power loop ΔV=Lpxdi/dt, where Lp is the total power loop inductance). After

the drain current reaches the inductor current, the Vds starts to fall. The Vgs undershoot spike is caused

by the miller feedback via Cgd under negative dv/dt.

Due to the low gate charge and small RG(OFF) , GaN E-HEMT gate has limited control on the turn-off

dv/dt. Instead the Vds rise time is determined by how fast the turn-off current charges switching node

capacitance (Coss).

The low Coss of GaN E-HEMT and low parasitic inductance of GaNPX™ package together with

optimized PCB alyout, enables a fast and clean turn-off Vds waveform with only 50V the turn-off Vds

overshoot at dv/dt > 100V/ns. The measured rise time is 3.9ns at 400V and 30A hard turn-off。

A T&M search coaxial current shunt (SDN-414-10, 0.1Ω) is installed for switching loss measurement as

shown below.

The switching energy can be calculated from the measured switching waveform Psw = Vds*Id. The

integral of the Psw during switching period is the measured switching loss. The channel deskewing is

critical for measurement accurary. It is recommended to manually deskew Id against Vds as shown in

Figure 20. The drain current spike is caused by charging the high side switch Coss (Qoss loss).

The switching loss measurements with drain current from 0 to 30A can be found in Figure 22. The turn-

on loss dominates the overall hard switching loss. Eon at 0A is the Qoss loss caused by the Coss at high

side switch.

The turn-off loss remain almost constant from 0A up to 20A about 8uJ. the measured Eoff matches well

with the Eoss @400V, which indicates that turn-off energy is dominated by Eoss, the energy required to

charge Coss from 0V to bus voltage. This energy is not part of loss at turn-off, but actually part of turn-on

loss at next hard switching turn-on period. This means that with the fast turn-off speed the GaN E-HEMT

can achieve near zero turn-off switching loss.

°

The board is converted to a synchronous buck DC/DC converter and demonstrates efficiency 99% at

1.5kW. With forced air cooling, the peak device temperature TJ_MAX was measured at 80°C at 1kW output.

TP

1

TP

TH

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M

PS

2 PE

S1-S

5-S

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GN

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NC8

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GN

DL

U3 L

P2985IM

5-6

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1

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OU

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TP

2

TP

TH

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M

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VD

RV

TP

4

TP

TH

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14

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2

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RV

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P2985IM

5-6

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1

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F3

BY

P4

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GN

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GS

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3

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Q2

GS

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1

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4

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R7

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C1

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VD

RV

VC

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C-

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MH

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R5

10R

Q1_V

O+

Q1_V

O-

GN

DH

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3.3

K

R10

3.3

K

C2

4.7

uF

C0805

R11

10R

PW

ML_IN

C9

C10

C12

1uF

C11

0.1

uF

1kV

C1812

PG

ND

VIN

-

Q2S

C8

VD

DH

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C13

1uF

VC

C_+5V

0V

R3

3.3

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LE

D1

LE

D-0

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VD

DH

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AB

LE

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3.3

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3

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N

GaN Systems Inc. (GaN Systems) provides the enclosed product(s) under the following AS IS conditions:

This evaluation board/kit being sold or provided by GaN Systems is intended for use for ENGINEERING

DEVELOPMENT, DEMONSTRATION, and OR EVALUATION PURPOSES ONLY and is not considered by GaN

Systems to be a finished end-product fit for general consumer use. As such, the goods being sold or provided are

not intended to be complete in terms of required design-, marketing-, and/or manufacturing-related protective

considerations, including but not limited to product safety and environmental measures typically found in end

products that incorporate such semiconductor components or circuit boards. This evaluation board/kit does not fall

within the scope of the European Union directives regarding electromagnetic compatibility, restricted substances

(RoHS), recycling (WEEE), FCC, CE or UL, and therefore may not meet the technical requirements of these directives,

or other related regulations.

If this evaluation board/kit does not meet the specifications indicated in the User’s Guide, the board/kit may be

returned within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE

EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES,

EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS

FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL

BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.

The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user

indemnifies GaN Systems from all claims arising from the handling or use of the goods. Due to the open construction

of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic

discharge.

No License is granted under any patent right or other intellectual property right of GaN Systems whatsoever. GaN

Systems assumes no liability for applications assistance, customer product design, software performance, or

infringement of patents or any other intellectual property rights of any kind.

GaN Systems currently services a variety of customers for products around the world, and therefore this

transaction is not exclusive.

Please read the User’s Guide and, specifically, the Warnings and Restrictions notice in the User’s Guide prior to

handling the product. Persons handling the product(s) must have electronics training and observe good

engineering practice standards.

This notice contains important safety information about temperatures and voltages. For further safety concerns,

please contact a GaN Systems’ application engineer.

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information: GaN Systems:

  GS66508B-EVBDB1