Smoke Detector Controller E520 - Mouser Electronics · Smoke Detector Controller E520.32 Preliminary Information – Oct 09, 2012 3 Recommended Operating Conditions • Parameters

Smoke Detector Controller E520.32Preliminary Information – Oct 09, 2012

Features• Designed for network addressable optical

smoke detectors• 2-wire programmable bus operation with

8V ... 50V supply• Low quiescent current (88 µA)• Embedded 8-bit micro controller with

4-KB FLASH (µ-code) and 128 Byte RAM• 28+4 Byte E²PROM for configuration data• Configurable 200mA LED driver• Configurable modulation current (240mA)• Photo current input range: 1.5 ... 45 nA• Input bandpass filter: 0.45 .. 4.5 kHz• Thermistor input• 4 digital general purpose IOs• JTAG debug and programming interface• Minimum number of external components• Complies to Russian norm NPB 58-97

Applications• Simplifies design of addressable smoke

detectors required by legislation• Fully programmable smoke detectors with

minimum of external components

Brief Functional DescriptionThe device provides a high current driver for a transmitter LED and a high impedance I-V conversion for the photo current of the receiver diode. Optimized response of both amplifier and ADC allow short transmitter pulses while keeping high detection efficiency. The amplifier's band pass filter characteristics remove noise from the signal.Transmitter pulses and signal acquisition as well as signal evaluation are controlled by the embedded micro controller allowing the user to take full control over the system performance with the user defined program code running from FLASH memory.The configurable address allows bus operation with up to 255 detectors on one bus.

Ordering InformationProduct ID Temperature Range Package

E520.32 -55°C to +85°C SOIC14

Typical Operating Circuit

This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice.

ELMOS Semiconductor AG Data Sheet QM-No. 25DS0063E.02, 1 / 77

Ln0

red

LED1

100µF10V

Detector module

Bus

RV

ϑ

(optional)

ELM

OS

520.

32

D5 LN24

DSUP

DIN

LED

RED

VTSEN

VTDRV LN0

Ln24

C1:

PD

LED2

RT

(opt

iona

l)


Block Diagram and Application Example

Fig. 1: Block Diagram

Symbol ParameterPD SFH2500/FALED1 SFH4500LED2 WP710A10LSRDC1 tantalum capacitor 100 uF x 6V, typ B45196-H1107-M309 20%RV resistor 150k, typ B54101 2%RT thermistor 100k, typ B57891M0104 1%

Table 1: Application Circuit Parameters (proposal)

Pin Configuration

Fig. 2: Package top view, not to scale



DSUP

Supply/Reference

AMP 10 bit ADC

5 bitDAC

4

RTϑ

D5

DIN

LED

RED

VTSEN

VTDRV

LN24

GPIO / JTAG

LN0

GPIO / JTAG LED Driver 8 bit uC

RED AMP

RED DriverRV

Alarm DriverCommunication

Transceiver

4KB FLASH

128B RAM

28B+4B E²PROM

Oscillator

POR

PDLED1

LED2

C1

IO0LN24

IO3

D5REDDIN

VTDRVDSUP

LN0LED

TEN

IO2IO1

1 14

7 8 VTSEN


Pin DescriptionNo Name Type Description1 LED A_O Transmitter LED driver output2 LN0 S Negative bus / supply connection , Ground (reference potential)3 D5 A_O Tank capacitor charging output4 RED A_IO Indicator red LED driver output and alarm simulation input5 DIN A_I Receiver diode current input6 DSUP A_O Receiver diode supply output7 VTDRV A_O Temperature half bridge driver output8 VTSEN A_I Temperature measurement channel input9 TEN D_I Test/debug enable; three level pad; pull down

10 IO3 D_IO General purpose IO 3 , if TEN=1 JTAG clock (TCK); pull up11 IO2 D_IO General purpose IO 2 , if TEN=1 JTAG test mode select (TMS); pull

up12 IO1 D_IO General purpose IO 1 , if TEN=1 JTAG data input (TDI); pull up13 IO0 D_IO General purpose IO 0 , if TEN=1 JTAG data output (TDO); pull up14 LN24 HV_S Positive bus / supply connection

Explanation of Types:A = Analog, D = Digital, S = Supply, I = Input, O = Output, B = Bidirectional, HV = High VoltageESD:More details according this topic are described in the "ESD" chapter (ch. 2).




1 Absolute Maximum RatingsStresses beyond these absolute maximum ratings listed below may cause permanent damage to the device. These are stress ratings only; operation of the device at these or any other conditions beyond those listed in the operational sections of this document is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.

All voltages referred to V(LN0). Currents flowing into terminals are positive, those drawn out of a terminal are negative.No. Description Condition Symbol Min Max Unit

1 Bus Supply voltage Continuous VLN24 -0.3 +50 V2 Bus Supply voltage reverse polarity

protection, current limitation via pin LN24

70mA≦

VLN24 -40 +50 V

3 Bus Supply voltage tPULSE < 100 ns,tPULSE,PERIOD > 10 µs,max. 75 consecutive pulses (1 burst),tBURST,PERIOD > 300 ms, overvoltage protection

VLN24 +60 V

4 Voltage at digital I/O pins VDPIN -0.3 5.5 V5 Input current at digital pins IDPIN -20 +20 mA6 Voltage at analog pins VAPIN -0.3 VD5+0.

3V

7 Input current at analog pins IAPIN -20 +20 mA8 Voltage at pin DIN VAPDIN -0.3 3.6 V9 Junction temperature J -55 +90 °C10 Ambient temperature AMB -55 +85 °C11 Storage temperature 1) STO -55 +90 °C12 Power dissipation average PTOT,AVG 20 mW

Table 1-1: Maximum Ratings1) Storage is not considering packing materials such as tapes, reels, dry packs, foils, etc. Please

contact ELMOS for packing material specifications. Packaged devices before soldering: For moisture sensitive devices refer to JEDEC standard J-STD-033 for handling and using details. Storage at temperatures > 90°C for more than 96 h may affect the solderability of the devices.

2 Electro-Static Discharge (ESD)Description Condition Symbol Min Max Unit

ESD HBM Protection at all Pins 1) VESD(HBM) -2 2 kV

ESD CDM Protection at all Pins 2) VESD(CDM) -500 500 V

ESD CDM Protection at Edge Pins 2) VESD(CDM)C -750 750 V1) According to AEC-Q100-002 (HBM) chip level test: C = 100pF, R = 1.5kΩ 2) According to AEC-Q100-011 (CDM) chip level test




3 Recommended Operating Conditions• Parameters are guaranteed within the range of recommended operating conditions unless otherwise specified.• Operation beyond recommended operating conditions is not qualified and may affect device reliability.• All voltages are referred to V(LN0) = 0V.• Currents flowing into the circuit have positive values.

No. Description Condition Symbol Min Typ Max Unit1 Bus supply voltage 1) VLN24 8 24 50 V2 Operating ambient

temperatureAMB,B -25 75 °C

3 Extended operating ambient temperature

VD5 V≧ TH,MON5 AMB,B,EXT -55 85 °C

4 Photo diode capacitance 2 V V≦ REVERSE ≦ 5 V

CPD 11 25 pF

5 External tank capacitor pin D5 to LN0 C1 80 100 330 µF6 D5 resistive load pin D5 to VTDRV RLOAD 1000 Ω7 VTDRV sink pulse current t < 50 µs;

duty cycle < 10-3

IVTDRV 0 6 mA

8 DSUP source current IDSUP -10 0 µATable 3-1: Recommended Operating Conditions

1) During bus communication VLN24 can decrease down to to 0V




4 Electrical Characteristics

4.1 Analog Characteristics

4.1.1 Supply and References(VLN24 = 8V to 50V, Tamb = -25°C to +75°C, unless otherwise noted. Typical values are at VLN24 = 24V and Tamb = +25°C. Positive currents flow into the device pins.)

No. Description Condition Symbol Min Typ Max UnitSupply Interface

1 Supply voltage, pin LN24 Normal operation1)

VLN24 8 24 50 V

2 Supply current, pin LN24 SUP_MODE = 00b

ILN24,0 88 µA

3 Supply current, pin LN24 SUP_MODE= 01b

ILN24,1 130 µA


ILN24,2 180 µA


ILN24,3 220 µA

6 LN24 monitor threshold voltage, falling edge, pin LN24

1)

VTH,LN24LOW,FALL 7.1 V

7 LN24 monitor threshold voltage, rising edge, pin LN24

1)

VTH,LN24LOW,RISE 7.4 V

8 LN24 monitor detection delay, pin LN24 1)

falling edge,VLN24 6.7 V≦

tLN24LOW 3.4 ms

9 Output voltage, pin D5 ID5_CONST=-30µA,SUP_MODE=00b,No ext.capacitor

VD5 4.8 5.2 5.5 V

10 Startup delay, pin D5 2) step 0V to 24V on LN24 ,C1 = 100uF

TSTARTDELAY 10 s

11 Supply monitor threshold voltage

VD5 rising VTH,MON5 4.4 4.64 4.8 V

12 Supply monitor hysteresis VTH,MON5_HYST 20 120 mVPhoto Diode Supply

13 Output voltage -0.1µA ≤ IDSUP < 0µA

VDSUP 4.3 4.6 VD5 V

Table 4.1.1-1: Supply Parameters1) During bus communication VLN24 can be decreased down to 0 V.2) Not tested in production.




4.1.2 Physical Interface via Bus Terminal LN24(VLN24 = 8V to 50V, Tamb = -25°C to +75°C, unless otherwise noted. Typical values are at VLN24 = 24V and Tamb = +25°C. Positive currents flow into the device pins.)

No. Description Condition Symbol Min Typ Max Unit1 Programmable detection

threshold voltage range for modulation type 1 1) 2)

PROT_THR = 00000b ... 11010b

VTH,MOD1,RANGE 8 34 V

2 Threshold voltage programming step for modulation type 1 2)

PROT_THR = 00000b ... 11010b

VTH,MOD1,STEP 0.5 1 1.5 V

3 Input threshold for modulation type 2 3)

PROT_THR = 11011b

VTH,MOD2,27 4.0 4.4 4.8 V

4 '' PROT_THR = 11100b

VTH,MOD2,28 8.5 9.5 10.0 V

5 '' PROT_THR = 11101b

VTH,MOD2,29 10.0 11.5 12.5 V

6 '' PROT_THR = 11110b

VTH,MOD2,30 13.0 14.5 15.5 V

7 '' PROT_THR = 11111b

VTH,MOD2,31 17.5 20 21.0 V

8 Maximum programmable modulation current 1)

VLN24 ≥ 8V IMOD_MAX 180 240 mA

9 Modulation current programming step 1)

VLN24 ≥ 8V IMOD_STEP 7.6 mA

10 Voltage drop at modulator ILN24 = 100mA,TXD_CUR[4:0]=11111b, TXD=H

VMOD_DROP 0.7 1.2 1.7 V

11 “ ILN24 = 50mA,TXD_CUR[4:0]=11111b, TXD=H

VMOD_DROP_50 0.35 0.6 0.85 V

Table 4.1.2-1: Physical Interface Parameters1) Design parameter, not tested in production.2) Modulation type 1 is for protocols where LN24 is always ≥ 8 V.3) Modulation type 2 is for down modulation, where LN24 can reach 0 V.

4.1.3 LED Driver for Smoke Chamber(VLN24 = 8V to 50V, Tamb = -25°C to +75°C, unless otherwise noted. Typical values are at VLN24 = 24V and Tamb = +25°C. Positive currents flow into the device pins.)

No. Description Condition Symbol Min Typ Max Unit1 Maximum LED current

programming 2)VLED ≥ 1.5 V ILED_MAX 200 mA

2 LED current programming step 1) , 2)

5 bit resolution,VLED ≥ 1.5 V,TJ = 25°C

ILED_STEP 6.45 mA

3 LED current temperature coefficient 2)

VLED ≥ 1.5 V ILED_TEMP 0.3 % / K

Table 4.1.3-1: LED Driver Parameters1) Tolerance is given as a fraction of the ideal set value2) Design parameter, not tested in production




4.1.4 Smoke Detection and Temperature Measurement Channel(VLN24 = 8V to 50V, Tamb = -25°C to +75°C, unless otherwise noted. Typical values are at VLN24 = 24V and Tamb = +25°C. Positive currents flow into the device pins.)

No. Description Condition Symbol Min Typ Max UnitPhoto Current Detector (AMP)

1 Full scale input current range 2) IDIN 1.5 45 nA2 Detector conversion factor

programmable range 2)FCONV 0.02 0.7 V/nA

3 Detector conversion factor programming step, see 5.2.2.2

AMP_GAIN = 1100b to 0000b,f = 1 kHz 1)

FCONV,STEP +0.8 +2 +3.2 dB

4 Detector conversion factor temperature drift 2)

FCONV,TEMP -10 +10 %

5 Input bandpass lower corner frequency 2)

-3 dB @ fAMP,L fAMP,L 0.45 kHz

6 Input bandpass upper corner frequency 2)

-3 dB @ fAMP,H fAMP,H 4.5 kHz

Temperature Measurement Channel (VTSEN, VTDRV)7 Input voltage range 2) VVTSEN 0 VREF2

- 0.3V

8 Switch on-resistance VTDRV ON_TEMP = H,IVTDRV < 6mA

RVTDRV,ON 6 14 35 Ω

9 Time before sampling 2) TTEMP,AP 10 µs10 Input capacitance 2) 3) CIN 5 pF

10-Bit AD ConverterReference voltage 2) VREF2 2.4 VSampling time 2) 4) TSAMP 2 µsConversion time 2) 4) TCONV 8 µsResolution 2) N 10 LSB

Table 4.1.4-1: Smoke Detector and Temperature Parameters1) Tolerance is given as a fraction of the ideal set value2) Design parameter, not tested in production3) Capacitance is loaded from 0 V to VVTSEN during sampling time TSAMP 4) Timing specification is referenced to fOSC8M = 8 MHz




4.1.5 RED Light Interface(VLN24 = 8V to 50V, Tamb = -25°C to +75°C, unless otherwise noted. Typical values are at VLN24 = 24V and Tamb = +25°C. Positive currents flow into the device pins.)

No. Description Condition Symbol Min Typ Max Unit1 Red LED source current Transmit mode IRED -10 -5.5 -3 mA2 Red LED current pulse

duration 1)Transmit mode,duty cycle < 2⋅10-3

tRED,DUR 1 2 3 ms

3 Input voltage high threshold Receive mode VTH,RED_H 0.3 V4 Input voltage low threshold Receive mode VTH,RED_L 0.2 V5 Input impedance Receive mode,

VRED < 0.4 V,TJ = 25°C

RRED,IN 0.7 1 1.3 MΩ

6 Temperature coefficient fo input impedance 1)

RRED,IN_TEMP 0.4 % / K

Table 4.1.5-1: RED Light Interface Parameters1) Design parameter, not tested in production

4.1.6 Oscillators(VLN24 = 8V to 50V, Tamb = -25°C to +75°C, unless otherwise noted. Typical values are at VLN24 = 24V and Tamb = +25°C. Positive currents flow into the device pins.)

No. Description Condition Symbol Min Typ Max Unit1 Frequency of slow oscillator trimmed fOSC100K 96 100 104 kHz2 Frequency of fast oscillator trimmed fOSC8M 7.2 8 8.8 MHz3 Startup time of fast oscillator 1) 90% FOSC8M TSTART,OSC8M 2 µs

Table 4.1.6-1: Oscillator Parameters1) Design parameter, not tested in production




4.2 Digital Characteristics

4.2.1 Central Processing Unit (CPU)No. Description Condition Symbol Min Typ Max Unit

1 Data bus width BBUS 8 Bit2 Address bus width BADR 16 Bit3 Bus clock frequency FBUS 4 MHz4 Stackpoint bit width BSTACK 6 Bit5 Number interrupt vectors NINT 86 RAM memory size NRAM 128 Byte

EEPROM7 Memory size NEEPROM 28+4 Byte8 Data retention time 1) tRET 10 year9 Endurance 1) NEND 105 Prog.

cycles10 Wake-up time 1) tWAKEUP,EE 50 µs11 Erase or write time 1) tPROG,EE 9.2 ms12 Shutdown write time 1) tSDWR,EE 3.2 ms

Flash Memory13 Memory size NFLASH_4k 4 KByte14 Wake-up time 1) tWAKEUP,FL 20 µs

Table 4.2.1-1: CPU and Memory Features1) Design parameter, not tested in production

4.2.2 PeripheryNo. Description Condition Symbol Min Typ Max Unit

Measurement Control Unit1 LED current pulse duration duty cycle < 10-3 TLED 100 µs

Physical Interface Control Unit2 Protocol bit time range TBIT 0.15 2.5 ms

Red Light Interface Control Unit 1) 3 Red light test alarm trigger

periodALPER = 00b TALARM,0 670 750 830 µs

4 '' ALPER = 01b TALARM,1 450 500 550 µs5 '' ALPER = 10b TALARM,2 290 330 370 µs6 '' ALPER = 11b TALARM,3 220 250 280 µs7 Red light pulse duration TRED,DUR 2 ms

Table 4.2.2-1: Periphery Circuit Parameters1) Timing specification is referenced to fOSC100K = 100 kHz




5 Functional Description

5.1 General Functional DescriptionThe basic function of this device is to periodically trigger an optical smoke sensor, to evaluate the sensor signal, and to indicate a smoke alarm if detected.The optical smoke sensor is a chamber with a light emitting diode LED1 and a photo diode PD. Commonly a reflective detection is used, therefore the inner walls of the detection chamber are virtually non-reflective and the LED1 does not directly illuminate the photo diode PD. Short, high power light pulses from the LED light up the chamber. If smoke is present inside the chamber, a certain amount of light is scattered at the smoke and reaches the photo diode.The device architecture comprises an LED driver (LED DRV), a current to voltage converter (AMP) with a subsequent analog-to-digital converter (ADC) for acquiring the photo current, a micro controller (CPU) for data evaluation and system control, and a physical interface to the 2-wire bus which provides the power supply and links the smoke detector module to a central control instance. Up to 255 detector modules can be attached to the bus.For status indication a driver for a red light emitting diode LED2 is provided. With an appropriate hand held device light pulse sequences can be applied to the red LED2 in order to emulate an alarm for diagnosis purpose in the field. The red LED2 is used as photo diode to convert the light pulses into a current/voltage signal. The signal is decoded and made available for the micro controller.Additionally the device provides a temperature measurement channel to detect and evaluate the temperature as a complementary signal to the optical sensor output. The temperature signal is fed to the ADC and is processed by the micro controller.

Fig. 5.1-1: Block Diagram E520.32



DSUP

Supply/Reference

AMP 10 bit ADC

5 bitDAC

4

RTϑ

D5

DIN

LED

RED

VTSEN

VTDRV

LN24

GPIO / JTAG

LN0

GPIO / JTAG LED Driver 8 bit uC

RED AMP

RED DriverRV

Alarm DriverCommunication

Transceiver

4KB FLASH

128B RAM

28B+4B E²PROM

Oscillator

POR

PDLED1

LED2

C1


5.1.1 Smoke DetectionFor the smoke detection a special measurement sequence is executed. The execution can be initiated periodically in two ways depending on register MECONF.MEMODE:

1. MEMODE=0b : Controlled by the µC based on software and protocol.Periodical measurement requests received via the physical interface protocol are interpreted by the µC to start a measurement, acquire the measurement values, determine the result, and transmit the result to the master unit.

2. MEMODE=1b : Automatically controlled by the configurable measurement timer.After power-up the µC configures the dedicated timer. In operation the µC is periodically interrupted (woken up) to acquire the measurement values, determine the result. In parallel, there might be a protocol request to be processed.

The measurement sequence is generated by the measurement control unit (MEAS_CTRL):1) The receiving current-to-voltage converter/amplifier (AMP) is initialized.2) The analog-to-digital conversion is started with a configurable sampling rate or each conversion

is started by the µC to digitalize the output of the current-to-voltage converter/amplifier, i.e. the photo current from the receiving photo diode PD.

3) The light emitting diode LED1 is driven by the LED driver with a configurable current ILED1 for a configurable time TLED1.

4) During 2) and 3) the µC acquires the noise signal (LED1 off) and the smoke signal (LED1 on).5) LED1 is switched off but µC can continue acquiring the smoke signal (LED1 off)6) Stop ADC conversion, then µC can process the data and determine the results.

For details refer to chapter 5.2.2.2.

5.1.2 Temperature MeasurementFor temperature measurements a half bridge RV - RT can be connected. It is driven via pin VTDRV and measured via pin VTSEN.Enabled by the register MECTRL.TME_EN a temperature measurement can be performed by driving VTDRV and connecting VTSEN to the ADC as a part of the measurement sequence. The time between start of driving VTDRV and start of analog-to-digital conversion is TTEMP,AP (refer to Table 4.1.4-1).For details refer to chapter 5.2.2.2.

5.1.3 Bus Interface via Supply Terminal LN24The physical interface via the supply terminal LN24 is capable to handle a wide range of bit serial communication protocols. The Smoke Detector can receive voltage modulation with configurable polarity and thresholds and it can transmit current modulation with configurable modulation current.The physical interface control unit (LN24_CTRL, refer to chapter 5.2.2.3) builds the interface to the CPU. It can provide interrupts/wake-ups from received RXD events and force answers via TXD with configurable delay and duration.




5.1.4 Red Light InterfaceVia the pin RED the red light emitting diode LED2 can be connected to realize a light interface with two functions:

1. Send periodically pulsed red light driven by the red light driver (RED_DRV) in the measurement pauses as an indicator of the device state. The µC software should periodically set REDCTRL.EN_RED bit to start RED lighting impulse. RED impulse bit REDCTRL.EN_RED is automatically reset. The pulse duration TRED_DUR is fixed to 2ms. To increase the RED pulse duration few following impulses can be used.

2. Receive an alarm request. This interface is intended to receive an emulated alarm for diagnosis purpose via an appropriated hand held device (refer to 5.2.2.4).




5.2 Detailed Functional DescriptionThe Digital part consist of the two global blocks. The universal microprocessor (CPU) and special purpose digital periphery. The periphery part is intended to provide independent processing of the LN24 communication protocol, the measurement cycle and the RED light emitting. Thus microprocessor controls time duration of the periphery modes but timing control, analogue signal forming and priority processing are done by periphery base on the hardware-coded finite state machines.The digital part uses two clock frequencies. The high frequency system clock for Central Processing Unit (CPU) and the low frequency clock for the special purpose periphery. The low frequency clock is continuously generated for timing control of the bus communication, the measurement and the emitting RED light. The high frequency clock is only generated in specific conditions to reduce the CPU's power consumption.The CPU is connected to the memory (FLASH, EEPROM and RAM) and the peripheral modules via the internal system bus. The system bus provides a 16 bit address space and allows 8 bit data transfers.The memory contains the program code and the data. Memory and registers are mapped according to the global Memory Map (refer to 5.2.1.2) and can be accessed through all memory related operation provided by the CPUs instruction set.The Interrupt Controller collects requests from all interrupt sources and provides an interrupt signal to the CPU. Interrupt sources can be masked within the interrupt controller. Interrupts are generated by the modules and hold until they are cleared within the modules.

5.2.1 Central Processing Unit (CPU)5.2.1.1 CPU EL3.5 Core 1. 6805 instruction set compatible including 8 by 8 multiplication2. 15 Interrupt vectors3. 1 Reset vector4. 16 bit address bus width5. 64 KByte data/program address space (0x0000 - 0xFFFF)6. Clock frequency 0-4MHz7. 6 Bit Stack-Pointer8. 16 Bit extended Program counter

CARRY

ACCUMULATOR

7 0

A

INDEX RESIGTER

7 0

X

STACK POINTER

7

SP

PROGRAM COUNTER

0

PC

15

CONDITION CODE REGISTER 1 C CCR1 1 H I N Z

ZERONEGATIVE

INTERRUPT MASKHALF-CARRY (FROM BIT 3)

15 0

0 0 0 0 0 0 1 1

5

00

Fig. 5.2.1.1-1: Programming model




These internal actions occur as result of any CPU reset:1. All registers are set to reset value2. Stack pointer forced to (0x00FF)3. I bit in the CCR set to 1 to inhibit maskable interrupts4. External interrupt latch cleared

As the computer leaves reset, the PC is loaded from the two highest memory location (0xFFFF).The standard interrupt controller accepts up to 15 different interrupts.To accept interrupts the CCR I-Bit has to be cleared with the CLI instruction.

Debug InterfaceTo access the debug structures of the EL3.5 CPU a 4-wire standard JTAG interface is used. The JTAG interface can be accessed via 4 GPIO pins when the TEN pin is set to 3.3V. TEN pin set to zero resets all test and debug structures and the ASIC operates in normal mode.

CPU RegistersThe Accumulator A is used for general calculations. The X Register is used for indirect and indexed addressing.The stack pointer SP is used internally by the CPU. The first 2 Bits of the SP-Register are fixed to one. This is to protect the rest of the RAM in case of a stack overflow.The program counter is 16-Bit long. So the maximum addressable code area is 64KByte.

Name Size DescriptionCCR 5 bit Condition Code RegisterPC 16 bit Program CounterSP 6 bit Stack PointerX 8 bit Index RegisterA 8 bit Accumulator

STACK 64 bytes Stack 64 byte LIFO (last-in-first-out)

Table 5.2.1.1-1: CPU Registers

Bit Name Description4 H Half-Carry (from bit 3)3 I Interrupt mask2 N Negative flag1 Z Zero flag0 C Carry bit

Table 5.2.1.1-2: Condition Code Register




Instruction Set

Table 5.2.1.1-3: Instruction Set Summary (Sheet 1 of 6)
























Table 5.2.1.1-9: Instruction Set Op-Code Map




5.2.1.2 Memory Map - Base Address Table

Base Address Size Modul Name Reference0xF000 0x1000 FLASH 4K X 8 5.2.1.60x0100 0xEFFF unused invalid addresses 1)

0x0080 0x0080 RAM 128 x 8 5.2.1.40x007C 0x0004 reserved invalid addresses 1)

0x0060 0X001C E²PROM 28 X 8 5.2.1.50x0055 0x000B reserved invalid addresses 1)

0x0050 0x0005 E²PROM Control Registers (EE_CTRL) 5.2.1.50x0048 0x0008 reserved invalid addresses 1)

0x0040 0x0008 Universal Timer (TIMER) 5.2.2.70x0039 0x0007 reserved invalid addresses 1)

0x0038 0x0001 Red Light Interface Control Unit (IR_RED_CTRL)

5.2.2.4

0x0034 0x0004 reserved invalid addresses 1)

0x0030 0x0004 Measurement Control Unit (MEAS_CTRL) 5.2.2.20x002A 0x0006 reserved invalid addresses 1)

0x0020 0x000A Physical Interface Control Unit (LN24_CTRL) 5.2.2.30x0018 0x0008 reserved invalid addresses 1)

0x0010 0x0008 Special Function Registers (SFR),locked by SYSCTRL.CONFLOCK

5.2.2.8

0x000C 0x0004 General Purpose IOs (GPIO) 5.2.2.50x0009 0x0003 reserved invalid addresses 1)

0x0008 0x0001 Watchdog (WATCHDOG) 5.2.2.60x0007 0x0001 reserved invalid address 1)

0x0001 0x0006 Main Control Unit (MAIN_CTRL) 5.2.2.10x0000 0x0001 reserved invalid address 1)

Table 5.2.1.2-1: Base Address Table1) Note: An invalid address access will cause a system reset (refer to 5.2.2.1).




Fig. 5.2.1.2-1: Memory map



MAIN_CTRL

0x0001

WATCHDOG

0x0006

0x0008

GPIO0x000C0x000F

SFR

0x0010

0x0017

LN24_CTRL

0x0020

0x0029

MEAS_CTRL0x00300x0033

IR_RED_CTRL0x0038

TIMER

0x0040

0x0047

EE_CTRL0x00500x0054

E²PROM28 x 8

0x0060

0x007B

RAM128 x 8

0x0080

0x00FF

FLASH4K x 8

0xF000

0xFFFF


5.2.1.3 Interrupt vector The following Table 5.2.1.3-1 shows all interrupt vectors in descending priority.

Number Block Vector Address Source0 POR 0xFFFE - 0xFFFF Power drop0 WATCHDOG 0xFFFE - 0xFFFF Watchdog reset0 CPU 0xFFFE - 0xFFFF Invalid address access1 CPU 0xFFFC - 0xFFFD Software interrupt (SWI)2 IR_RED_CTRL 0xFFFA - 0xFFFB RED interface alarm interrupt3 LN24_CTRL 0xFFF8 - 0xFFF9 Physical interface interrupt4 MEAS_CTRL 0xFFF6 - 0xFFF7 Measurement interrupt

(Start)5 GPIO 0xFFF4 - 0xFFF5 GPIO interrupt6 TIMER 0xFFF2 - 0xFFF3 TIMER interrupt7 MAIN_CTRL 0xFFF0 - 0xFFF1 Power monitor interrupt8 EE_CTRL 0xFFEE - 0xFFEF EEPROM interrupt9 MEAS_CTRL 0xFFEC - 0xFFED ADC interrupt

10 - 15 - 0xFFE0 - 0xFFEB 6 Interrupt vectors reservedTable 5.2.1.3-1: Reset and Interrupt vectors list

5.2.1.4 RAM This Random Access Memory (RAM) module is a static volatile memory block.The module contains a 128-word by 8-bit RAM array. RAM address range 0x80 to 0xBF is used to keep CPU variable. RAM address range 0xC0 to 0xFF is fixed by hardware to be used as CPU stack.

5.2.1.5 E²PROM The embedded E²PROM block provides 32 bytes divided into 28 bytes of the USER part and 4 bytes of INFO part. USER part address range is 0x60 to 0x7B. The address range 0x64 to 0x67 is shared between USER and INFO part. To get read access to the INFO part the bit EECFG.INFO (0x50) has to be set.The INFO part of E²PROM is reserved to hold factory trimming data for oscillators and ELMOS ID code as described in Table 5.2.1.5-1.

Address Name Description0x64 OSC_TRIM Oscillator trimming (refer to 5.2.2.1, “Main Control Register”)0x65 UDIN_H ELMOS Device ID, byte 10x66 UDIN_M ELMOS Device ID, byte 20x67 UDIN_L ELMOS Device ID, byte 3

Table 5.2.1.5-1: E²PROM Info Area (EECFG.INFO = 1b)

After power-up one of the first CPU action, after EEPROM wake-up time, has to be the transfer of the oscillator trimming values to the corresponding register OSC_TRIM (refer to chapter 5.2.2.1, Clock and Reset Control Unit).




In the USER part 28 bytes are free to hold for example:• Customer IDs• Smoke detector gain setting: AMP_GAIN[3:0] (4 bit)• LED driver current setting: LED_DAC[4:0] (5 bit)• Supply mode: SUP_MODE[1:0] (2 bit)• Input threshold setting of physical interface: PROT_THR[4:0] (5 bit)• Modulation current setting of physical interface: TXD_CUR[4:0] (5 bit)• ...For reliability it is recommended to periodically refresh the registers with corresponding E²PROM contents.The E²PROM is organized in 12 bit wide words. Data word consists of 8 bit data and 4 bit ECC (one bit error detection and correction).

E²PROM LockingTo prevent unintended E²PROM programming a lock mechanism is implemented. Incorrect handling of the unlocking procedure during attempt to erase or program generates a system reset that can be found by high state of SYSSTAT.EERES.

Erase and Program ProcedureIn the following Table 5.2.1.5-2 and Table 5.2.1.5-3 the procedures for erasing and programming of E²PROM content is described. To change any data on a E²PROM cell it is necessary to first erase this cell.

Step Description1 • If E²PROM is disabled then activate it.2 • Unlock ERASE by:

1) Write 0xA0 to EEPCLK2) Write 0x0A to EEPCLK

3 • Write any data to selected E²PROM address (range 0x60-0x7B).4 • Write a b1 to EECFG.ER to start automatic erasing.5 • After 9 ms erasing cycle bits EECFG.ER and EECFG.LOCK will be cleared, and

EEPROM interrupt EESTAT.IRQ_ER is set.6 • To write now data to the E²PROM go on with step 2 in Programming Procedure (Table

5.2.1.5-3).Table 5.2.1.5-2: Erasing Procedure




If an E²PROM cell is already erased, new data can be programmed directly by the following programming procedure (Table 5.2.1.5-3). If the Erasing Procedure has been just finished the Programming Procedure can be started with step 2.

Step Description1 • If E²PROM is disabled then activate it.2 • Unlock PROGRAM by:

1) Write 0xA0 to EEPCLK2) Write 0x0A to EEPCLK3) Again write 0x0A to EEPCLK

3 • Write data to selected EEPROM address (range 0x60-0x7B).4 • Write a 1b to EECFG.PGM to start automatic programming.5 • After 9 ms programming cycle bits EECFG.PGM and EECFG.LOCK will be cleared, and

EEPROM interrupt EESTAT.IRQ_PGM is set.Table 5.2.1.5-3: Programming Procedure

E²PROM Control and Status Registers

Register Name Address DescriptionEECFG 0x50 EEPROM Configuration RegisterEEPLCK 0x51 EEPROM Programming Lock RegisterEECTRL 0x52 EEPROM Control RegisterEESTAT 0x53 EEPROM Status RegisterEEMIRQ 0x54 EEPROM Masked Interrupt Requests Flags (read only)

Table 5.2.1.5-4: EEPROM Control and Status RegisterLegend: Internal access: from view of HW block. External access: from view of CPU (programmer).

R : read , W : write , S : set , C : clear.




Register EECFG (0x50)MSB LSB

Content [7] PGM ER VHI VLO INFO LOCK ECCERRReset value 0 0 0 0 0 0 0 0Access 0 R/S R/S R/W R/W R/W R RBit Description [7] : reserved

PGM : Selects programming of memory• bit is set by writing a 1b to this location,• bit is cleared automatically after programming has finished.Note: It is not allowed to set both PGM and ER at the same time.ER : Selects erasing of memory• bit is set by writing a 1b to this location,• bit is cleared automatically after erasing has finished.Note: It is not allowed to set both PGM and ER at the same time.VHI : Enable verify mode with high read voltage referenceThe control bits VHI and VLO are used to verify the success of the programmed data or the long term data retention. By setting one of the bits, the internal bias voltage is skewed either up (VHI = 1b) or down (VLO = 1b). The high read reference voltage (VHI = 1b) is used to verify the programmed state '1' (erase state). The low read reference voltage (VLO = 1b) verifies the programmed state '0' (programmed state). If the read out data is unchanged (and no ECCERR is detected) for both read voltages a robust value for normal read out (VHI, VLO = 0b) is verified.Note: Both bits VHI and VLO must not be set at the same time.Note: Changing the read reference voltage by setting VHI or VLO, or after a write cycle the settling of the read reference voltage needs 50 us. This settling time has to be considered by the software.• 0b : normal read voltage• 1b : increased read voltage, VLO have to be 0b !VLO : Enable verify mode with low read voltage referenceFor description refer to bit VHI.• 0b : normal read voltage• 1b : decreased read voltage, VHI have to be 0b !INFO : Enables access to the INFO partThe INFO bit allows access to a portion of the array reserved for factory use, called INFO part. The INFO part shares addresses 0x64 - 0x67 with the USER part.• 0b : USER part is selected,• 1b : INFO part is selected.LOCK : E²PROM Lock Status FlagThis flag indicates that an E²PROM wake-up, a programming or an erasing is in progress (refer to 5.2.1.5, E²PROM Locking).• flag is set if an E²PROM wake-up, a programming or an erasing is initiated,• flag is automatically cleared by hardware, if E²PROM wake-up, programming or

erasing has finished.• ECCERR : Error Correction Code error flag• flag is set if an ECC error has happened in last read access to the E²PROM,• flag is cleared, if last read access was without error.

Table 5.2.1.5-5: EEPROM Configuration Register




Register EEPLCK (0x51)MSB LSB

Content EEPLCK[7:3] LCKST[2:0]Reset value 0 0 0 0 0 1 1 1Access W W W W W R(W) R(W) R(W)Bit Description EEPLCK[7:0] : Lock command

There is no read access to the upper 5 bits EEPLCK[7:3]. Entire 8 bit register EEPLCK[7:0] should be written to change lock state:• 0xA0 - go from any state to state INIT,• 0x0A - go from state INIT to state ERASE or from state ERASE to state

PROGRAM,• 0x55 - go from state PROGRAM to state SHUTDOWN,• any other value leads to state RESET

LCKST[2:0] : Lock State (read only)• b111 : RESET• b000 : INIT, lock initialization• b001 : ERASE, erasing is unlocked• b010 : PROGRAM, programming is unlocked• b100 : SHUTDOWN, shutdown erasing/programming is unlocked

Table 5.2.1.5-6: EEPROM Programming Lock Register

Register EECTRL (0x52)MSB LSB

Content [7] [6] [5] [4] ENIRQ_WU

ENIRQ_SHD

ENIRQ_PGM

ENIRQ_ER

Reset value 0 0 0 0 0 0 0 0Access 0 0 0 0 R/W R/W R/W R/WBit Description [7:4] : reserved

ENIRQ_WU : Enable flag IRQ_WU to generate an interrupt/wakeup.ENIRQ_SHD : Enable flag IRQ_SHD to generate an interrupt/wakeup.ENIRQ_PGM : Enable flag IRQ_PGM to generate an interrupt/wakeup.ENIRQ_ER : Enable flag IRQ_ER to generate an interrupt/wakeup.

Table 5.2.1.5-7: EEPROM Control Register




Register EESTAT (0x53)MSB LSB

Content [7] [6] [5] [4] IRQ_WU IRQ_SHD IRQ_PGM

IRQ_ER

Reset value 0 0 0 0 0 0 0 0Access 0 0 0 0 R/C R/C R/C R/CBit Description [7:4] : reserved

IRQ_WU : Flag for activated EEPROM after wake-up• flag is set when EEPROM timer count 50 us after peripheral wake-up event if

SYSCTRL.EN_EE = 1b, or if CPU write SYSCTRL.EN_EE = 1b,• flag is cleared by writing a 0b to this location.Flag can be enabled to generate an interrupt/wakeup by ENIRQ_WU.IRQ_SHD : Flag for programmed EEPROM in shutdown mode• flag is set when EEPROM timer count 3 ms after EECFG.PGM/ER was set,• flag is cleared by writing a 0b to this location.Flag can be enabled to generate an interrupt/wakeup by IRQ_SHD.IRQ_PGM : Flag for programmed EEPROM in normal mode• flag is set when EEPROM timer count 9 ms after EECFG.PGM was set,• flag is cleared by writing a 0b to this location.Flag can be enabled to generate an interrupt/wakeup by IRQ_PGM.IRQ_ER : Flag for erased EEPROM• flag is set when EEPROM timer count 9 ms after EECFG.ER was set,• flag is cleared by writing a 0b to this location.Flag can be enabled to generate an interrupt/wakeup by IRQ_ER.

Table 5.2.1.5-8: EEPROM Status Register

Register EEMIRQ (0x54)MSB LSB

Content [7] [6] [5] [4] MIRQ_WU

MIRQ_SHD

MIRQ_PGM

MIRQ_ER

Reset value 0 0 0 0 0 0 0 0Access 0 0 0 0 R R R RBit Description [7:4] : reserved

MIRQ_WU : Masked flag for activated EEPROM after wake-up= IRQ_WU and ENIRQ_WUMIRQ_SHD : Masked Flag for programmed EEPROM in shutdown mode= IRQ_SHD and ENIRQ_SHDMIRQ_PGM : Masked flag for programmed EEPROM in normal mode= IRQ_PGM and ENIRQ_PGMMIRQ_ER : Masked flag for erased EEPROM= IRQ_ER and ENIRQ_ER

Table 5.2.1.5-9: EEPROM Masked Interrupt Requests Flags (read only)




5.2.1.6 FLASH The FLASH provides 4 KBytes of non-volatile program code memory. It's equipped with Error Correction Code (ECC) method for enhanced data storage reliability.

Features:• 4 KBytes Flash Memory;• Error Correction Code (ECC);• Programming up to 16 Bytes at once;• Two mode erasing - Page and Mass Erase;• Data verification for erased and programmed states;• Read access time 50 ns.

5.2.2 Periphery5.2.2.1 Main Control Unit

Clock and Reset Control Unit

Clocks:The Smoke Detector operates with two clock sources (refer to Table 4.1.6-1):

1. The slow oscillator OSC100K with a nominal frequency of 100 kHz (CLK100K) is running continuously. All tasks and timings, which have to be done continuously are controlled on the slow clock domain to keep the overall current consumption low.

2. The fast oscillator OSC8M with a nominal frequency of 8 MHz is used only in short time intervals. This oscillator output is internally divided to provide a system clock of 4 MHz (CLK4M). To save power consumption the fast oscillator is stopped most of the time and only woken up for short time, when the CPU is active. To stop the fast oscillator the CPU writes a 1b to register SYSCTRL.CPU_OFF. The CPU keeps its recent state and the FLASH changes into sleep mode. After an interrupt or an enabled wake-up event first the fast oscillator and the FLASH and then the CPU are reactivated (refer to 5.2.2.1)

Both oscillators have trimming inputs determined during production test. The trim-values are stored in the INFO part of the E²PROM (refer to 5.2.1.5) on address 0x64. It is essential to copy this trimming values to the corresponding register OSCTRIM (address 0x10, refer to 5.2.2.1) during system start-up.

Resets :The following sources can reset the system:

1. The power-on reset (POR) during system power-up or insufficient supply.2. An invalid address access caused by unexpected software behavior (refer to 5.2.1.2).3. A watchdog reset (refer to 5.2.2.6) also caused by unexpected software behavior.4. A reset caused by attempt to erase/program in wrong E²PROM lock state (refer to 5.2.1.5).5. A software reset by writing a 1b to register SYSCTRL.CPU_RST.6. A debug reset forced during debug mode.




Interrupt and Wakeup Control UnitThe interrupt and wakeup control unit provides two possibilities to react on events with a wakeup:

Interrupts:An interrupt is generated, if an interrupt request flag is set on register IRQSTAT and the corresponding bit on the interrupt mask register INTM is set to enable the interrupt. An active interrupt forces a jump to the address of the corresponding interrupt vector (refer to chapter 5.2.1.3).If the CPU is in sleep mode (SYSCTRL.CPU_OFF = 1b) an active interrupt also activates (wakes-up) the system clock, the CPU, FLASH and if SYSCTRL.EN_EE = 1b the E²PROM.

Note: There is one exception, the ADC interrupt (IRQ_MSKD.ADC_INT) does not wake-up the CPU, FLASH and E²PROM and the interrupt is not handled immediately in sleep mode.

Wake-ups:An enabled wake-up activates (wakes-up) the system clock, the CPU, the FLASH and if SYSCTRL.EN_EE = 1b the E²PROM, and the program is continued from the recent program location. The advantage is a faster software reaction with the disadvantage of a complexer software development.A wake-up is generated if an interrupt request flag is set on register IRQSTAT and the corresponding bit on the enable wake-up register WUEN is set to enable the wake-up.

Main Control Register DescriptionRegister Name Address Description

IRQSTAT 0x01 Interrupt Request Status RegisterINTM 0x02 Interrupt Unmask Register, locked by SYSCTRL.CONFLOCKWUEN 0x03 Wake-up Enable Register, locked by SYSCTRL.CONFLOCKSYSCTRL 0x04 System Control RegisterIRQ_MSKD 0x05 Masked Interrupt StatusSYSSTAT 0x06 System Status RegisterOSCTRIM 0x10 Oscillators Trimming Register,

located in SFR, locked by SYSCTRL.CONFLOCKPOWCONF 0x11 Power Configuration Register,

located in SFR, locked by SYSCTRL.CONFLOCKTable 5.2.2.1-1: Main Control Registers

Legend:Internal access : from view of HW block . External access : from view of CPU (programmer).R : read , W : write , S : set , C : clear.




Register IRQSTAT (0x01)MSB LSB

Content RED_IRQ PHY_IRQ ME_IRQ GPIO_IRQ

TIM_IRQ PMON_IRQ

EE_IRQ ADC_IRQ

Reset value 0 0 0 0 0 0 0 0Access R R R R R R R RBit Description RED_IRQ : Interrupt request from red light interface control (alarm request),

refer to chapter 5.2.2.4). (read only, this bit is mapped from REDCTRL.RED_IRQ),• bit is cleared by writing a 0b to REDCTRL.RED_IRQ.PHY_IRQ : Combined interrupt request from physical interface,refer to chapter 5.2.2.3. (read only),• bit is reset by clearing all active interrupts on PHYSTAT.ME_IRQ : Interrupt request from measurement control unit,refer to chapter 5.2.2.2. (read only ,this bit is mapped from MECTRL.ME_IRQ),• bit is cleared by reading any of the ADC_VAL registers or by writing a 0b to

MECTRL.ME_IRQGPIO_IRQ : Combined interrupt request from GPIOs,refer to chapter 5.2.2.5. (read only),• bit is reset by clearing all active interrupts on GPIOSTAT.TIM_IRQ : Combined interrupt request from universal timer,refer to chapter 5.2.2.7. (read only),• bit is reset by clearing all active interrupts on TSTAT.PMON_IRQ : Combined interrupt request from voltage monitor for V5D and LN24 (read only , PMON_IRQ = SYSSTAT.MON5LOW or SYSSTAT.LN24LOW),• bit is reset by clearing SYSSTAT.LN24LOW and SYSSTAT.MON5LOW.EE_IRQ : Combined interrupt request from E²PROM control block,refer to chapter 5.2.1.5. (read only),• bit is reset by clearing all active interrupts on EESTAT.ADC_IRQ : Interrupt request from ADC,refer to chapter 5.2.2.2. (read only, this bit is mapped from MECTRL.ADC_IRQ),• bit is cleared by reading any ADC_VAL register.

Table 5.2.2.1-2: Interrupt Request Status Register




Register INTM (0x02)MSB LSB

Content RED_IM PHY_IM ME_IM GPIO_IM TIM_IM PMON_IM

EE_IM ADC_IM

Reset value 0 0 0 0 0 0 0 0Access R/W R/W R/W R/W R/W R/W R/W R/WBit Description RED_IM : Interrupt unmask for RED_IRQ:

• 0b : RED_IRQ is masked (disabled),• 1b : RED_IRQ is unmasked (enabled).PHY_IM : Interrupt unmask for PHY_IRQ:• 0b : PHY_IRQ is masked (disabled),• 1b : PHY_IRQ is unmasked (enabled).ME_IM : Interrupt unmask for ME_IRQ:• 0b : ME_IRQ is masked (disabled),• 1b : ME_IRQ is unmasked (enabled).GPIO_IM : Interrupt unmask for GPIO_IRQ:• 0b : GPIO_IRQ is masked (disabled),• 1b : GPIO_IRQ is unmasked (enabled).TIM_IM : Interrupt unmask for TIM_IRQ:• 0b : TIM_IRQ is masked (disabled),• 1b : TIM_IRQ is unmasked (enabled).PMON_IM : Interrupt unmask for PMON_IRQ:• 0b : PMON_IRQ is masked (disabled),• 1b : PMON_IRQ is unmasked (enabled).EE_IM : Interrupt unmask for EE_IRQ:• 0b : EE_IRQ is masked (disabled),• 1b : EE_IRQ is unmasked (enabled).ADC_IM : Interrupt unmask for ADC_IRQ:• 0b : ADC_IRQ is masked (disabled),• 1b : ADC_IRQ is unmasked (enabled).

Table 5.2.2.1-3: Interrupt Unmask Register, locked by SYSCTRL.CONFLOCK

Register WUEN (0x03)MSB LSB

Content RED_WE PHY_WE ME_WE GPIO_WE

TIM_WE PMON_WE

EE_WE [0]

Reset value 0 0 0 0 0 0 0 0Access R/W R/W R/W R/W R/W R/W R/W 0Bit Description RED_WE : Wake-up enable for RED_IRQ

PHY_WE : Wake-up enable for PHY_IRQME_WE : Wake-up enable for ME_IRQGPIO_WE : Wake-up enable for GPIO_IRQTIM_WE : Wake-up enable for TIM_IRQPMON_WE : Wake-up enable for PMON_IRQEE_WE : Wake-up enable for EE_IRQ[0] : reserved

Table 5.2.2.1-4: Wake-up Enable Register, locked by SYSCTRL.CONFLOCK




Register SYSCTRL (0x04)MSB LSB

Content [7:6] CPU_RST

CONFLOCK

EN_GPIO EN_EE [1] CPU_OFF

Reset value 0 0 0 0 0 1 0 0Access 0 0 S R/W R/W R/W R/W SBit Description [7:6] : unused

CPU_RST : Reset command• write a b1 to CPU_RST to reset system,• bit is automatically cleared after reset.CONFLOCK : Lock configuration registers (SFR, refer to 5.2.2.8)• 0b : unlocked, CPU write access to configuration registers is enabled,• 1b : locked, CPU write access to configuration registers is disabled.EN_GPIO : Enable for General Purpose IO Unit• 0b : GPIO unit disabled,• 1b : GPIO unit enabled.EN_EE : Enable for EEPROM• 0b : EEPROM is constantly switched to sleep mode,• 1b : EEPROM is activated synchronous with CPU wake-up.[1] : reserved : • Always write 0b !CPU_OFF : Switch CPU, FLASH & E²PROM to sleep mode• write a 1b to CPU_OFF to stop CPU in sleep mode,• bit is cleared automatically by a wake-up.

Table 5.2.2.1-5: System Control RegisterRegister IRQ_MSKD (0x05)

MSB LSBContent RED_INT PHY_INT ME_INT GPIO_IN

TTIM_INT PMON_I

NTEE_INT ADC_INT

Reset value 0 0 0 0 0 0 0 0Access R R R R R R R RBit Description RED_INT : Interrupt from red light interface control

= RED_IRQ and RED_IM (read only)PHY_INT : Interrupt from physical interface control= PHY_IRQ and PHY_IM (read only)ME_INT : Interrupt from measurement control= ME_IRQ and ME_IM (read only)GPIO_INT : Interrupt from GPIOs= GPIO_IRQ and GPIO_IM (read only)TIM_INT : Interrupt from universal timer= TIM_IRQ and TIM_IM (read only)PMON_INT : Interrupt from voltage monitoring= PMON_IRQ and PMON_IM (read only)EE_INT : Interrupt from EEPROM control= EE_IRQ and EE_IM (read only)ADC_INT : Interrupt from ADC= ADC_IRQ and ADC_IM (read only)

Table 5.2.2.1-6: Masked Interrupt Status




Register SYSSTAT (0x06)MSB LSB

Content [7:6] EERES INVARES WDRES PUP MON5LOW

LN24LOW

Reset value 0 0 0 0 0 1 0 0Access 0 0 R/C R/C R/C R/C R/C R/CBit Description EERES : Invalid attempt to erase or program E²PROM (refer to 5.2.1.5)

• bit is set by invalid attempt (wrong E²PROM lock state) to set EECFG.ER/PGM, system reset was generated,

• bit is cleared by writing a 0b to this bit location.INVARES : Invalid address reset status bit• bit is set if invalid address has been detected, system reset has been generated,• bit is cleared by writing a 0b to this bit location.WDRES : Watchdog reset status bit• bit is set if watchdog reset has happened ,system reset has been generated,• cleared by writing a 0b to this bit location.PUP : Power-up reset status bit• bit is set by power-on reset,• cleared by writing a 0b to this bit location.MON5LOW : Status bit for analog monitor of the V5D voltage• bit is set if voltage is below monitor threshold,• cleared by writing a 0b to this bit location.LN24LOW : Status bit for analog monitor of the LN24• bit is set if voltage is below monitor threshold,• bit is cleared by writing a 0b to this bit location.

Table 5.2.2.1-7: System Status RegisterRegister OSCTRIM (0x10)

MSB LSBContent [7:6] OSC8M_

TRIM[1:0]OSC100K_TRIM[3:0]

Reset value 0 0 0 0 1 1 1 1Access 0 0 R/W R/W R/W R/W R/W R/WBit Description [7:6] : reserved

OSC8M_TRIM[1:0] : 2 bit trimming of 8 MHz oscillator• to be copied after power-up from E²PROM INFO address 0x64 to this location.OSC100K_TRIM[3:0] : 4 bit trimming of 100 kHz oscillator• to be copied after power-up from E²PROM INFO address 0x64 to this location.

Table 5.2.2.1-8: Oscillators Trimming Register, located in SFR, locked by SYSCTRL.CONFLOCKRegister POWCONF (0x11)

MSB LSBContent [7:2] SUP_MO

DE[1:0]Reset value 0 0 0 0 0 0 0 0Access 0 0 0 0 0 0 R/W R/WBit Description [7:2] : reserved

SUP_MODE[1:0] : Supply current mode• Setting is according to Table 4.1.1-1.

Table 5.2.2.1-9: Power Configuration Register, located in SFR, locked by SYSCTRL.CONFLOCK




5.2.2.2 Measurement Control Unit The Measurement Control Unit (MEAS_CTRL) is intended to control smoke and temperature measurements. There are two possibilities to wake-up and start a smoke measurement:

1. MEMODE = 0b: CPU controlled measurement cycle.2. MEMODE = 1b: Periodical measurement cycle with defined time period controlled by the

measurement timer.

In both cases temperature measurements can be started automatically by setting the enable bit MECTRL.TME_EN. The measured temperature value is then saved in the ADC register and should be read by CPU before starting the smoke measurement otherwise this value will be lost.A 10 bit ADC is used to sample amplified chamber photo diode current as well as temperature sensor voltage. There are two ADC sampling modes for smoke measurement depending on MECONF.AAC_EN:

1. AAC_EN = 0b: Sampling mode is irregular controlled by CPU.2. AAC_EN = 1b: Regular ADC sampling with 2 possible configuration (10 or 20 us time per

sample).

To use interrupts/wake-ups from the measurement control unit first the global interrupt mask (INTM.ME_IM) or the global wake-up enable (WUEN.ME_WE) have to be set (refer to 5.2.2.1).To automate the control of the measurement cycles a finite state machine is used.

This state machine has three states:1. IDLE• After a reset the measurement FSM starts in IDLE state.• During this state analog part is switched off.• Depending on MECONF.MEMODE there are two different events to switch to INIT state:• MEMODE = 0b: Writing 1b to MECTRL.SSME starts initialization,• MEMODE = 1b: Measurement timer starts initialization, period is configurable with

MECONF.ME_PR[1:0].2. INIT• In this state the amplifiers are initialized.• If the temperature measurement is enabled with MECTRL.TME_EN = 1b a temperature

measurement is automatically performed during this state.• After initialization time tINIT the state changes to ACTIVE and the interrupt flag MECTRL.ME_IRQ

should be used to wake-up the CPU.3. ACTIVE• After wake-up the CPU can first read the temperature value from the ADC register, if the

temperature measurement was enabled.• Depending on MECONF.AAC_EN the ADC conversion is started by writing a 1b to

MECTRL.SOC.• AAC_EN = 0b : A single ADC conversion is started.• AAC_EN = 1b : An automatically, regular ADC conversion is started.

• With writing a 1b to MECTRL.LED_EN the smoke chamber LED1 is switched on with a current pulse of length tLED.

• After the measurement, i.e. stopping ADC conversion with subsequent post-processing state changes back to IDLE by going into sleep mode (SYSCTRL.CPU_OFF = 1b).

At any time and any state a measurement cycle is stopped and the measurement timer is restart in IDLE state by first writing MECTRL.SSME = 0b and then writing SYSCTRL.CPU_OFF = 1b.




The following chapters show examples of different configured measurements.

Measurement Cycle controlled by TimerFig. 5.2.2.2-1 depicts an example of a measurement cycle controlled by timer.

Fig. 5.2.2.2-1: Example : Measurement Cycle controlled by timer (MECONF.MEMODE = 1b)

Settings:• MECONF.MEMODE = 1b, timer controlled measurements,• INTM.ME_IM = 1b or WUEN.ME_WE = 1b to enable wake-up/interrupt by measurement timer.

1. The measurement timer changes the state from IDLE to INIT and sets the bit MECTRL.SSME.2. During state INIT the amplifiers are initialized and a temperature measurement can be enabled (for

details refer to Fig. 5.2.2.2-3 in chapter 5.2.2.2).3. The measurement timer set the interrupt request flag MECTRL.ME_IRQ and generates a wake-

up/interrupt. The state changes to ACTIVE.4. The wake-up activates the CPU (SYSCTRL.CPU_OFF = 0b).5. The CPU has to clear the interrupt request, writing a 0b to MECTRL.ME_IRQ.6. The CPU starts to control the ADC (MECTRL.SOC, for details refer to chapter 5.2.2.2). First the

noise level is measured (before the LED pulse).7. The CPU set the bit MECTRL.LED_EN. After synchronization a current pulse of length tLED is forced

to pin LED.8. The measurement is stopped by clearing the bit MECTRL.SSME.9. After post processing the CPU switches to sleep mode (SYSCTRL.CPU_OFF = 1b) and the state

changes to IDLE.10.The measurement timer starts the next measurement cycle.



MECTRL.LED_EN

MEAS_TIMER

MECTRL.ME_IRQ

State

MECTRL.SSME

IDLE INIT ACTIVE

wake-up

tINIT

Set by timer Cleared by CPU

SYSCTRL.CPU_OFF

IDLE


Cleared by wake-up Set by CPU

Pin LED

Amplifier output

registers

Post processing

1

ADC conversion

tLED

MECTRL.SOC

2 3 45 67

Set by CPU Cleared automatically

8 9 10

INIT

tCYCLE


Measurement Cycle controlled by CPUFig. 5.2.2.2-2 is an example of a measurement cycle controlled by CPU.

Fig. 5.2.2.2-2: Example : Measurement Cycle controlled by CPU (MECONF.MEMODE = 0b)

Settings:• MECONF.MEMODE = 0b, CPU controlled measurements• INTM.ME_IM = 1b or WUEN.ME_WE = 1b to enable wake-up/interrupt by measurement timer

1. The CPU wakes-up by protocol for a measurement request.2. The CPU changes the state from IDLE to INIT by setting the bit MECTRL.SSME.3. The CPU switches to sleep mode (SYSCTRL.CPU_OFF = 1b).4. During state INIT the amplifiers are initialized and a temperature measurement can be enabled (for

details refer to Fig. 5.2.2.2-4 in chapter 5.2.2.2).5. After tINIT the measurement timer set the interrupt request flag MECTRL.ME_IRQ and generates a

wake-up/interrupt. The state changes to ACTIVE.6. The wake-up activates the CPU (SYSCTRL.CPU_OFF = 0b).7. The CPU has to clear the interrupt request flag, writing a 0b to MECTRL.ME_IRQ.8. The CPU starts to control the ADC (MECTRL.SOC, for details refer to chapter 5.2.2.2). First the

noise level is measured (before the LED pulse).9. The CPU set the bit MECTRL.LED_EN. After synchronization a current pulse of length tLED is forced

to pin LED.10.The measurement is stopped by clearing the bit MECTRL.SSME.11.After post processing the CPU switches to sleep mode (SYSCTRL.CPU_OFF = 1b) and the state

changes to IDLE.12.The next measurement cycle starts after a measurement request via protocol.



MECTRL.LED_EN

MECTRL.ME_IRQ

State

MECTRL.SSME

IDLE INIT ACTIVE

wake-up

tINIT


SYSCTRL.CPU_OFF

IDLE

Set by CPU Cleared by CPU

Cleared by wake-up

Set by CPU

Pin LED

Amplifier output

registers

Post processing

2

ADC conversion

tLED

MECTRL.SOC

4 5 67 89


10 11 12

INIT

1 3

Set by CPU Cleared by wake-up

tCYCLE


Temperature MeasurementAn example of a temperature measurement in the timer controlled mode is illustrated in Fig. 5.2.2.2-3.

Fig. 5.2.2.2-3: Example : Cycle incl. Temperature controlled by timer (MECONF.MEMODE = 1b)

Settings:• MECONF.MEMODE = 1b, timer controlled measurements• INTM.ME_IM = 1b or WUEN.ME_WE = 1b to enable wake-up/interrupt by measurement timer

1. At the end of last measurement cycle the CPU sets MECTRL.TME_EN to enable a temperature measurement for the next measurement cycle.

2. End of last measurement by going to sleep mode (SYSCTRL.CPU_OFF = 1b).3. The measurement timer changes the state from IDLE to INIT and sets the bit MECTRL.SSME.4. After tTEMP_DELAY an automized temperature measurement is started.5. After tTEMP the temperature measurement is finished and the ADC converted temperature value is

available on register ADCVAL.6. After amplifier initialization the measurement timer set the interrupt request flag MECTRL.ME_IRQ

and generates a wake-up. The state changes to ACTIVE.7. The wake-up activates the CPU (SYSCTRL.CPU_OFF = 0b).8. The CPU read the temperature value from register ADCVAL. With this read access the interrupt

request flag is reset (MECTRL.ME_IRQ = 0b).



MECTRL.LED_EN

MECTRL.ME_IRQ

State

MECTRL.SSME

IDLE INIT ACTIVE

wake-up

tINIT


SYSCTRL.CPU_OFF

IDLE


Set by CPU

Pin LED

Amplifier output

registers

3

ADC conversionof temperature value

tLED

MECTRL.SOC

4 6 7 8


2

ACTIVE

Cleared by wake-up

MECTRL.TME_EN Set by CPU

Pin VTDRV

tTEMP

tTEMP_DELAY

5

Cleared automatically

MEAS_TIMER

Set by CPU

1

tINACTIVEt

ACTIVE


An example of a temperature measurement in the CPU controlled mode is shown in Fig. 5.2.2.2-4.

Fig. 5.2.2.2-4: Example : Cycle incl. Temperature controlled by CPU (MECONF.MEMODE = 0b)

Settings:• MECONF.MEMODE = 0b, CPU controlled measurements• INTM.ME_IM = 1b or WUEN.ME_WE = 1b to enable wake-up/interrupt by measurement timer

1. The end of the last measurement by going to sleep mode (SYSCTRL.CPU_OFF = 1b).2. The CPU wakes-up by protocol for a measurement request.3. The CPU changes the state from IDLE to INIT by setting the bits MECTRL.SSME and

MECTRL.TME_EN to enable the temperature measurement.4. The CPU switches to sleep mode (SYSCTRL.CPU_OFF = 1b).5. After tTEMP_DELAY an automatized temperature measurement is started.6. After tTEMP the temperature measurement is finished and the ADC converted temperature value is

available on register ADCVAL.7. After amplifier initialization the measurement timer set the interrupt request flag MECTRL.ME_IRQ

and generates a wake-up. The state changes to ACTIVE.8. The wake-up activates the CPU (SYSCTRL.CPU_OFF = 0b).9. The CPU read the temperature value from register ADCVAL. With this read access the interrupt

request flag is reset (MECTRL.ME_IRQ = 0b).



MECTRL.LED_EN

MECTRL.ME_IRQ

State

MECTRL.SSME

IDLE INIT ACTIVE

wake-up

tINIT


SYSCTRL.CPU_OFF

IDLE

Set by CPU Cleared by CPU

Cleared by wake-up

Set by CPU

Pin LED

Amplifier output

registers

3

ADC conversionof temperature value

tLED

MECTRL.SOC

5 7 8 9


1

ACTIVE

2 4

Set by CPU Cleared by wake-up

MECTRL.TME_EN Set by CPU

Pin VTDRV

tTEMP

tTEMP_DELAY

6

Cleared automatically

tINACTIVE

tACTIVE


Smoke Measurement Phase Fig. 5.2.2.2-5 shows an example of the smoke measurement phase with regular ADC conversion.

Fig. 5.2.2.2-5: Example : Automatic ADC conversation (MECONF.AAC_EN = 1b)

Settings:• MECONF.MEMODE = 0b or 1b• MECONF.AAC_EN = 1b• INTM.ME_IM = 1b or WUEN.ME_WE = 1b to enable wake-up/interrupt by measurement timer

1. The measurement timer set the interrupt request flag MECTRL.ME_IRQ and generates a wake-up/interrupt. The state changes to ACTIVE.

2. The wake-up activates the CPU (SYSCTRL.CPU_OFF = 0b).3. The CPU has to clear the interrupt request by writing a 0b to MECTRL.ME_IRQ or reading ADCVAL.4. The CPU sets MECTRL.SOC to start an automatized ADC sampling. MECTRL.EOC is reset by

hardware when an ADC conversion starts.5. MECTRL.EOC and MECTRL.ADC_IRQ are set when the an ADC conversion has finished. The

converted value is available on register ADCVAL.6. When MECTRL.EOC becomes 0b the next ADC conversion is started.7. The CPU reads register ADCVAL. With this read access MECTRL.ADC_IRQ is reset.8. The CPU set the bit MECTRL.LED_EN. After synchronization a current pulse is forced to pin LED.9. After tLED the current pulse is finished and MECTRL.LED_EN is automatically reset.10.The measurement and the automatic ADC conversion are stopped by clearing the two bits

MECTRL.SSME and MECTRL.SOC.11.After post processing the CPU switches to sleep mode (SYSCTRL.CPU_OFF = 1b) and state

changes to IDLE.



MECTRL.LED_EN

MECTRL.ME_IRQ

State

MECTRL.SSME

INIT ACTIVE

wake-upCleared by CPU

SYSCTRL.CPU_OFF

IDLE

Cleared by CPU

Set by CPU

Pin LED

Amplifier output

registers

Post processing

ADC conversion

tLED

MECTRL.SOC

4


1 2

Cleared by wake-up

3

MECTRL.EOC

MECTRL.ADC_IRQ

ADCVAL

5 6 78 ... 9 10 11

tSAMP


Fig. 5.2.2.2-6 depicts an example of a smoke measurement phase with single ADC conversion, i.e. the CPU starts each single ADC conversion.

Fig. 5.2.2.2-6: Example : CPU controlled ADC conversation (MECONF.AAC_EN = 0b)

Settings:• MECONF.MEMODE = 0b or 1b• MECONF.AAC_EN = 0b• INTM.ME_IM = 1b or WUEN.ME_WE = 1b to enable wake-up/interrupt by measurement timer

1. The measurement timer set the interrupt request flag MECTRL.ME_IRQ and generates a wake-up/interrupt. The state changes to ACTIVE.

2. The wake-up activates the CPU (SYSCTRL.CPU_OFF = 0b).3. The CPU has to clear the interrupt request, writing a 0b to MECTRL.ME_IRQ or reading ADCVAL.4. The CPU sets MECTRL.SOC to start a single ADC sampling.5. MECTRL.SOC and MECTRL.EOC are reset by hardware when the ADC conversion starts.6. MECTRL.EOC and MECTRL.ADC_IRQ are set when the ADC conversion has finished. The

converted value is available on register ADCVAL.7. The CPU reads ADCVAL and MECTRL.ADC_IRQ is reset.8. The CPU set the bit MECTRL.LED_EN. After synchronization a current pulse is forced to pin LED.9. After tLED the current pulse is finished and MECTRL.LED_EN is automatically reset.10.The CPU reads the last ADC value.11.The resets MECTRL.SSME to stop the measurement.12.After post processing the CPU switches to sleep mode (SYSCTRL.CPU_OFF = 1b) and state

changes to IDLE.



MECTRL.LED_EN

MECTRL.ME_IRQ

State

MECTRL.SSME

INIT ACTIVE

wake-upCleared by CPU

SYSCTRL.CPU_OFF

IDLE

Cleared by CPU

Set by CPU

Pin LED

Amplifier output

registers

Post processing

ADC conversion

tLED

MECTRL.SOC

4


1 2

Cleared by wake-up

3

MECTRL.EOC

MECTRL.ADC_IRQ

ADCVAL

67 8...

9 10 125 11


Timing DefinitionsName Time Description

tINIT 7.8 ms Time for initialization of amplifier from setting MECTRL.SSME to setting of interrupt flag ME_IRQ

tTEMP_DELAY 1000 us Time for initialization of amplifier from setting MECTRL.SSME until start of temperature measurement

tTEMP 20 us Duration of temperature measurementTable 5.2.2.2-1: Measurement Timing Table

Measurement Control Register DescriptionRegister Name Address Description

LEDCONF 0x14 LED1 configuration register,locked by SYSCTRL.CONFLOCK

AMPCONF 0x15 Current-to-voltage converter/amplifier configuration register,locked by SYSCTRL.CONFLOCK.

MECONF 0x16 Measurement configuration register,locked by SYSCTRL.CONFLOCK.

ADCVAL10_H 0x30 High byte 10 bit ADC valueADCVAL10_L 0x31 Low byte 10 bit ADC valueADCVAL8 0x32 8 bit ADC valueMECTRL 0x33 Measurement Control Register

Table 5.2.2.2-2: Measurement Control RegistersLegend: Internal access: from view of HW block. External access: from view of CPU (programmer).


Register LEDCONF (0x14)MSB LSB

Content [7:5] LED_DAC[4:0]

Reset value 0 0 0 0 0 1 0 0Access 0 0 0 R/W R/W R/W R/W R/WBit Description [7:5] : reserved

LED_DAC[4:0] : LED DAC (current) setting :• 00000b : ILED = 0 mA• 00001b : ILED = 6.45 mA• ... (+ 6.45 mA steps)• 11111b : ILED = 200.0 mADefault : 25.8 mA

Table 5.2.2.2-3: LED1 configuration register, locked by SYSCTRL.CONFLOCK




Register AMPCONF (0x15)MSB LSB

Content [7:6] ON_MUX AMP_TSW

AMP_GAIN[3:0]

Reset value 0 0 0 0 0 0 0 0Access 0 0 R/W R/W R/W R/W R/W R/WBit Description [7:6] : reserved

ON_MUX : Connect ADC input• 0b : unconnected, ADC input is open,• 1b : connected, multiplexer is connected to ADC.AMP_TSW : Test switch control• 0b : unconnected,• 1b : connect amplifier output to VTSEN.AMP_GAIN[3:0] : Current-to-voltage conversion factor setting• 1111b : FCONV = 0.022 V/nA• 1110b : FCONV = 0.022 V/nA• 1101b : FCONV = 0.022 V/nA• 1100b : FCONV = 0.045 V/nA• 1011b : FCONV = 0.065 V/nA• 1010b : FCONV = 0.085 V/nA• 1001b : FCONV = 0.105 V/nA• 1000b : FCONV = 0.135 V/nA• 0111b : FCONV = 0.165 V/nA• 0110b : FCONV = 0.21 V/nA• 0101b : FCONV = 0.27 V/nA• 0100b : FCONV = 0.34 V/nA• 0011b : FCONV = 0.43 V/nA• 0010b : FCONV = 0.53 V/nA• 0001b : FCONV = 0.61 V/nA• 0000b : FCONV = 0.67 V/nA (default)

Table 5.2.2.2-4: Current-to-voltage converter/amplifier configuration register, locked by SYSCTRL.CONFLOCK.




Register MECONF (0x16)MSB LSB

Content [7:5] ADCRA ME_PR[1:0]

AAC_EN MEMODE

Reset value 0 0 0 0 0 0 0 0Access 0 0 0 R/W R/W R/W R/W R/WBit Description [7:5] : reserved

ADCRA : ADC sampling rateValid if AAC_EN = 1b• 0b : 10 µs• 1b : 20 µsWhen AAC_EN = 0b this bit is unused.

ME_PR[1:0] : Measurement cycle periodThe measurement cycle period consists of:tCYCLE = tINACTIVE + tACTIVE, wheretINACTIVE is the sum of IDLE time and INIT time. tINACTIVE is configurable with:• 00b : tINACTIVE = 0.8s• 01b : tINACTIVE = 1.0s• 10b : tINACTIVE = 2.0s• 11b : tINACTIVE = 4.0stACTIVE is software depending in the range of 0.2 - 4 ms.

AAC_EN : Enable automatic ADC conversion• 0b : each individual SOC pulse is generated by the CPU,• 1b : SOC pulses are generated automatically with sampling rate

MECONF.ADCRA.MEMODE : Measurement mode• 0b : measurement period is controlled by CPU,• 1b : measurement period controlled by measurement timer.

Table 5.2.2.2-5: Measurement configuration register, locked by SYSCTRL.CONFLOCK.

Register ADCVAL10_H (0x30)MSB LSB

Content [7:2] ADCVAL[9:8]

Reset value 0 0 0 0 0 0 0 0Access 0 0 0 0 0 0 R RBit Description [7:2] : unused ; filled with 0´s, if read.

ADCVAL[9:8] : High byte (2 MSBs) of 10 bit ADC value (unsigned)Table 5.2.2.2-6: High byte 10 bit ADC value

Register ADCVAL10_L (0x31)MSB LSB

Content ADCVAL[7:0]Reset value 0 0 0 0 0 0 0 0Access R R R R R R R RBit Description ADCVAL[7:0] : Low byte (8 LSBs) of 10 bit ADC value

Table 5.2.2.2-7: Low byte 10 bit ADC value




Register ADCVAL8 (0x32)MSB LSB

Content ADCVAL[9:2]Reset value 0 0 0 0 0 0 0 0Access R R R R R R R RBit Description ADCVAL[9:2] : 8 bit ADC value (unsigned)

Table 5.2.2.2-8: 8 bit ADC value

Register MECTRL (0x33)MSB LSB

Content ME_IRQ EOC ADC_IRQ DLOST LED_EN SOC TME_EN SSMEReset value 0 1 0 0 0 0 0 0Access R/C R R/C R/C R/S R/W R/S SBit Description ME_IRQ : Measurement interrupt flag

• flag is set by hardware after amplifier initialization phase,• flag is cleared by reading any of the ADC_VAL registers or by writing a 0b to this

bit position.EOC : End of analog-to-digital conversion• bit is set, if conversion is ready,• bit is cleared with next SOC pulse.ADC_IRQ : ADC interrupt request flag (Data valid flag)• flag is set with rising edge of EOC, new ADC data is valid,• flag is cleared by reading any of the ADC_VAL registers.DLOST : Data lost flag• flag is set with rising edge of EOC, when ADC_IRQ is already set, i.e. previous

data were not read by CPU,• flag is cleared by reading any of the ADC_VAL registers.LED_EN : LED enable • with writing a 1b to this location the LED1 is switched on, synchronized by

CLK100K.• LED1 is switched off by internal timer after 100 µs and LED_EN is automatically

cleared.SOC : Start of analog-to-digital conversionCase 1 : ME_CONF.AAC_EN = 0b • writing a 1b to this location starts a single analog-to-digital conversion.• bit is automatically cleared, after starting conversion cycleCase 2 : ME_CONF.AAC_EN = 1b • writing a 1b to this location starts automated analog-to-digital conversion with

constant sampling rate according to ME_CONF.ADCRA.TME_EN : Temperature measurement enable• if this bit is set a temperature measurement is performed during initialization of a

measurement sequence,• after temperature measurement this bit is cleared automatically.SSME : Start smoke measurement sequence• writing a 1b to this location starts a measurement sequence,• writing a 0b to this bit together with SOC = 0b stops the ADC conversion and

switch off analog partto conserve energy.

Note : If Automatic ADC conversion is used (AAC_EN='1') measurement should be stopped before going in sleep mode.

Table 5.2.2.2-9: Measurement Control Register




5.2.2.3 Physical Interface Control Unit The Physical Interface Control Unit (LN24_CTRL) is intended to support the CPU in processing a wide range of different one wire protocols. In most cases only one interrupt/wakeup per bit is needed to interpret the received data and to force the answer. The CPU is kept in sleep mode as long as possible to decrease its current consumption.

ReceivingVoltage modulation on pin LN24 are converted to a digital level in the analog part of the physical interface (refer to chapter MISSING REFERENCE) by comparison with a configurable threshold. This threshold VTH is derived from register PHYCONF1.PROT_THR[4:0] according to Table 4.1.2-1.Two different receiving modes according to Table 5.2.2.3-1 and Fig. 5.2.2.3-1 are configurable to handle different protocols depending on register PHYCONF1.RXDMODE. The two modes differ in the definition of the leading edge (bit-start) and the captured time (RXDCAP), or in other words, if the protocol uses up or down modulation. The leading edge resets and starts two 8 bit timers, the receiving capture/compare timer (RXD_TIMER) and the transmitting delay/duration timer (TXD_TIMER). Both timers run with the slow clock CLK100K. Additionally the interrupt flag PHYSTAT.IRQ_LE is set by the leading edge, it can be configured to generate an interrupt/wakeup with PHYCTRL.ENIRQ_LE.The timer capture function provides the measured time between two RXD edges (from leading edge to trailing edge). The captured time can be read on register RXDCAP. After capturing the interrupt flag PHYSTAT.IRQ_CAP is set. It can be enabled with PHYCTRL.ENIRQ_CAP to generate an interrupt/wakeup.If the RXD_TIMER reaches its maximum value 0xFF the overflow flag PHYSTAT.RXD_TOF is set and the RXD_TIMER is stopped. This flag can also be configured to generate an interrupt/wakeup with PHYCTRL.ENIRQ_TOF.

RXDMODE Leading edge Trailing edge Captured time (RXDCAP)0b Falling edge of RXD Rising edge of RXD Falling to rising edge of RXD1b Rising edge of RXD Falling edge of RXD Rising to falling edge of RXD

Table 5.2.2.3-1: Receiving modes

Fig. 5.2.2.3-1: Timing Diagram for Receiving Modes



RXD

RXD

RXDMODE = 1b

leading edge (bit start) trailing edge

RXDMODE = 0b

RXD_TIMER

next leading edge (next bit)

0 1 2 ...

timer reset

... 0 1 2 ...

timer reset

.........

RXDCAPcaptured time


The CPU can write two compare values to registers RXDCMP1 and RXDCMP2. With this functions it is possible to observe both, a low phase as well as a high phase on RXD.

1. The first compare function is started with the leading edge and if the recent timer value RXD_TIMER = RXDCMP1 before the trailing edge the flag IRQ_CMP1 is set.

2. The second compare function is started with the trailing edge, so the captured time RXDCAP between leading and trailing edge is already available. If (RXD_TIMER - RXDCAP) = RXDCMP2 the flag IRQ_CMP2 is set.

If RXDCMP1/2 compares an RXD low or high phase is determined by PHYCTRL.RXDMODE. Both flags PHYSTAT.IRQ_CMP1 and PHYSTAT.IRQ_CMP2 can be used to generate an interrupt/wakeup. This is enabled by PHYCTRL.ENIRQ_CMP1 and PHYCTRL.ENIRQ_CMP2

RXDMODE RXDCMP1 RXDCMP20b Compare low phase between leading and

trailing edgeCompare high phase between trailing and next leading edge

1b Compare high phase between leading and trailing edge

Compare low phase between trailing and next leading edge

Table 5.2.2.3-2: Compare Functions

Fig. 5.2.2.3-2: Timing Diagram for Compare Functions

Besides the capture function the physical interface provides an additional possibility to automatically read a received bit.The CPU can write a defined time to register RXDREAD. If the timer value RXD_TIMER reaches the strobe time RXDREAD the recent level of RXD is stored to PHYSTAT.RXD_RD and the flag PHYSTAT.IRQ_READ is set (refer to Fig. 5.2.2.3-3). This flag can be used to generate an interrupt/wakeup enabled by PHYCTRL.ENIRQ_READ.



RXD

RXD

RXDMODE = 1b


RXDMODE = 0b

RXD_TIMER


0 1 2 ...... 0 1 2 .........

RXDCMP1 RXDCMP2

...

Flag IRQ_CMP1 is set, if RXD_TIMER = RXDCMP1before trailing edge

IRQ_CMP1 is not set IRQ_CMP2 is not set

Flag IRQ_CMP2 is set, if RXD_TIMER - RXDCAP = RXDCMP2before next leading edge

RXDCAP


RXD

RXD

RXDMODE = 1b


RXDMODE = 0b

RXD_TIMER


0 1 2 ...... 0 1 2 .........

RXDREAD

If RXD_TIMER = RXDREADFlag IRQ_READ is set, and recentlevel of RXD is stored to PHYSTAT.RXD_RD

RXD_RD = 0

RXD_RD = 1

RXD_RD = 0RXD_RD = 1

Fig. 5.2.2.3-3: Timing Diagram for RXD Read Function (RXDSAMP = 0b)

The delay time between different slaves caused by long wires can vary. For a robust reading two methods of sampling the RXD_RD signal are implemented. PHYCONF1.RXDSAMP selects if just one or two subsequent samples are used for RXD_RD and PHYCONF1.RXDGATE selects how the two samples are combined to the final RXD_RD (refer to Table 5.2.2.3-3).

RXDSAMP RXDGATE Description0b Xb Just one sample is generating the RXD_RD bit.1b 0b Two subsequent samples (sampling rate 10 us) are used to generate

the RXD_RD bit, where this samples are combined by an AND-gate.IRQ_READ is set with taking the 2. sample.

1b 1b Two subsequent samples (sampling rate 10 us) are used to generate the RXD_RD bit, where this samples are combined by an OR-gate.IRQ_READ is set with taking the 2. sample.

Table 5.2.2.3-3: RXD read sampling configuration

To prevent unintended or self-induced timer resets and interrupts by forcing current on LN24 (via TXD) or disturbances on LN24, the interface control unit provides a blockage function:

1. After the 1. trailing edge any possible leading edge is blocked to reset RXD_TIMER and the interrupt flag PHYSTAT.IRQ_LE is suppressed until RXD_TIMER reaches the value on register RXDBLK.

2. After the 1. trailing edge any possible 2. trailing edge is blocked to capture the recent timer value and the interrupt flag PHYSTAT.IRQ_CAP is suppressed until RXD_TIMER reaches the value on register RXDBLK.

Depending on PHYCONF1.RXDMODE there are two cases for blockage function, refer to Fig. 5.2.2.3-4 and Fig. 5.2.2.3-5.




Fig. 5.2.2.3-4: Timing Diagram for Blockage Function : RXDMODE = 0b

RXD


RXDMODE = 1b

RXD_TIMER


0 1 2 ...

timer reset

... 0 1 2 ...

timer reset

...

RXDBLK

1. Trailing is valid:→ capture function active→ interrupt flag is set→ blocking is activated

Leading edgeis blocked:→ no timer reset→ no interrupt from edge

2. Trailing edgeis blocked:→ no 2. capture→ no interrupt from edge

TXD

LN24 is pulled down by current modulation→ RXD is influenced by TXD

Fig. 5.2.2.3-5: Timing Diagram for Blockage Function : RXDMODE = 1b

TransmittingFor transmitting data, i.e. force a modulation current to pin LN24, the bit to transmit have to be written to register PHYCTRL.TXD. This bit is internally buffered and has to be written before the leading edge to be transmitted after the leading edge. The bit for the next leading edge can be written during or even before actual transmission (current forcing). With the leading edge PHYCTRL.TXD is internally buffered and automatically cleared. Also with leading edge PHYCTRL.TXD is latched to PHYCTRL.TXD_LAT, to be able to read what will be or is transmitted in recent bit time.For timing the transmitting delay/duration timer (TXD_TIMER) is used. If PHYCTRL.TXD is high the transmitting timer generates a current modulation pulse IMOD with current setting determined by PHYCONF2.TXD_CUR[4:0] according to Table 4.1.2-1. The current pulse is generated with two configurable timings, a delay from leading edge (bit-start) to TXD-pulse and the duration of the pulse (refer to Fig. 5.2.2.3-1). If PHYCTRL.TXD is low no pulse is generated.



RXD


RXDMODE = 0b

RXD_TIMER


0 1 2 ...

timer reset

... 0 1 2 ...

timer reset

...

RXDBLK

1. Trailing is valid:→ capture function active→ interrupt flag is set→ blocking is activated

Leading edgeis blocked:→ no timer reset→ no interrupt from edge

2. Trailing edgeis blocked:→ no 2. capture→ no interrupt from edge

TXD

LN24 is pulled down by current modulation→ RXD is influenced by TXD


The delay is determined by register TXDDEL and the pulse duration is according to register TXDDUR. The PHYCTRL.TXD has to be written before the leading edge. In the special case that the delay is 0 (TXDDEL = 0x00), the current force is immediately and the TXD_TIMER is directly loaded with duration value TXDDUR (refer to Fig. 5.2.2.3-9).

RXD

RXD

RXDMODE = 1b

leading edge (bit start)

RXDMODE = 0b

TXD_TIMER


...

load timer with delay,after synchronization

... 0 1 2 ...

timer reset

...

TXDDEL

TXD

TXDDUR

...0

TXD

_DEL

load timer with duration

force currentif PHYCTRL.TXD=1

TXD

_DU

R

0

PHYCTRL.TXD has to be written before the leading edge,

otherwise it is transmitted after the next leading edge

Fig. 5.2.2.3-6: Timing Diagram for Transmitting

InterruptsTo use interrupts/wake-ups from the physical interface first the global interrupt mask (INTM.PHY_IM) or the global wake-up enable (WUEN.PHY_WE) have to be set (refer to 5.2.2.1). After this six different flags can be locally enabled to generate an interrupt/wakeup (refer to Table 5.2.2.3-4 and registers PHYSTAT and PHYCTRL):

Flag on PHYSTAT

Enable interrupt on PHYCTRL

Description

IRQ_LE ENIRQ_LE Interrupt request generated from leading edge on RXDIRQ_CAP ENIRQ_CAP Interrupt request generated from trailing edge on RXD,

when RXDCAP is capturedIRQ_CMP1 ENIRQ_CMP1 Interrupt request generated from RXD_TIMER, if recent

timer RXD_TIMER = RXDCMP1 before the trailing edge. Refer to Fig. 5.2.2.3-2.

IRQ_CMP2 ENIRQ_CMP2 Interrupt request generated from RXD_TIMER, if RXD_TIMER - RXDCAP = RXDCMP2 before the next trailing edge. Refer to Fig. 5.2.2.3-2.

IRQ_READ ENIRQ_READ Interrupt request generated from RXD_TIMER, if recent timer RXD_TIMER = RXDREAD independent of the trailing edge. Refer to Fig. 5.2.2.3-3.

IRQ_TOF ENIRQ_TOF Interrupt request generated from RXD_TIMER, if timer has an overflow, i.e. the timer stops at 0xFF.

Table 5.2.2.3-4: Physical Interface Interrupts




Fig. 5.2.2.3-7 depicts all details about generation of physical interface interrupt/wakeup generation (refer also to chapter 5.2.2.1), incl. the global interrupt mask and wake-up enable registers.

IRQ_LE

ENIRQ_LE AND

IRQ_CAP

ENIRQ_CAP

IRQ_CMP1

ENIRQ_CMP1

IRQ_CMP2

ENIRQ_CMP2

PHYCTRL012346 57

addr 0x27

IRQ_READ

ENIRQ_READ

AND

AND

AND

WUEN012346 57

addr 0x03

INTM012346 57

addr 0x02

PHY_IRQ

PHY_WE

PHY_IM

AND

IRQ

STAT

7

4

5

2

3

0

1

6

addr

0x0

1 AND

PHY_INT

WAKEUPOR

PHY_IRQ

IRQ_TOF

ENIRQ_TOF AND

ANDOR

PHYSTAT012346 57

addr 0x28

Interrupt and Wake-up Control UnitPhysical Interface Interrupt Control

Fig. 5.2.2.3-7: Physical Interface Interrupts/Wakeups

SynchronizationThe received signal RXD is synchronized to CLK100K. For this reason any timing derived from RXD have a sampling jitter of TRXD,JIT = 10 µs and a synchronization time of TRXD,SYNCH = 5 µs.Fig. 5.2.2.3-8 depicts the RXD synchronization.

CLK100K

Sampling jitterT

RXD,JIT= 0 – 10 us

RXD_RE ↑:

RXD

RXD_FE ↓:

RXD_TIMER 0 1

TXDDEL= 3

X

0

RXD_RE2 ↑:

TXD_TIMER

LOAD1_TIMER =not RXD_FE and RXD_RE2

2 1

PHY_TXD

LOAD_TXDDUR

TXDDUR TXDDUR- 1

2 3 4

Synchronization timeT

RXD,SYNCH = 10 us

Fig. 5.2.2.3-8: RXD Synchronization , TXDDEL > 0




Fig. 5.2.2.3-9 shows the special case for TXDDEL = 0x00.

Fig. 5.2.2.3-9: RXD synchronization , TXDDEL = 0

Description of Interface Control RegistersRegister Name Address Description

PHYCONF1 0x12 Physical Interface Configuration Register 1,locked by SYSCTRL.CONFLOCK

PHYCONF2 0x13 Physical Interface Configuration Register 2,locked by SYSCTRL.CONFLOCK

TXDDEL 0x20 Transmitter Configuration : Transmitting delayTXDDUR 0x21 Transmitter Configuration : Transmitting durationRXDCMP1 0x22 Receiving Timer Compare Value 1RXDCMP2 0x23 Receiving Timer Compare Value 2RXDBLK 0x24 Receiving Timer Blockage TimeRXDREAD 0x25 Receiving Timer Read TimeRXDCAP 0x26 Receiving Timer Captured ValuePHYCTRL 0x27 Physical Interface Control RegisterPHYSTAT 0x28 Physical Interface Status RegisterPHYMIRQ 0x29 Physical Interface Masked Interrupt Requests Flags (read only)

Table 5.2.2.3-5: Physical Interface Control RegistersLegend: Internal access: from view of HW block. External access: from view of CPU (programmer).




CLK100K

RXD

RXD_TIMER 0 1

RESET_RXD_TIMER =not RXD_RE and RXD_FE

X

0TXD_TIMER

LOAD_TXDDEL =not RXD_FE and RXD_RE2

PHY_TXD

LOAD_TXDDUR

2 3 4 5

TXDDUR= 4 3 2 1 0

Sampling jitterT

RXD,JIT= 0 – 10 us

Synchronization timeT

RXD,SYNCH = 10 us


Register PHYCONF1 (0x12)MSB LSB

Content RXDGATE

RXDSAMP

RXDMODE

PROT_THR[4:0]

Reset value 0 0 0 1 1 1 0 0Access R/W R/W R/W R/W R/W R/W R/W R/WBit Description RXDGATE : Select gate for RXD read function with two samples

This bit is unused if PHYCONF1.RXDSAMP = 0b.• 0b : RXD_RD = sample(n) AND sample(n+1),• 1b : RXD_RD = sample(n) OR sample(n+1).where n is the read time RXDREAD.RXDSAMP : Select number of samples in RXD read function• 0b : 1 sample,• 1b : 2 samples, combination is selected by PHYCONF1.RXDGATE.RXDMODE : Receiving mode (refer to chapter 5.2.2.3)• 0b : falling edge is leading edge,• 1b : rising edge is leading edge.PROT_THR[4:0] : Protocol receiver thresholds• 00000b : VTH,MOD1 = 8 V, modulation type 1• 00001b : VTH,MOD1 = 9 V, modulation type 1• ... (+ 1 V steps)• 11001b : VTH,MOD1 = 33 V, modulation type 1• 11010b : VTH,MOD1 = 34 V, modulation type 1• 11011b : VTH,MOD2 = 4.4 V, modulation type 2• 11100b : VTH,MOD2 = 9.5 V, modulation type 2 (default)• 11101b : VTH,MOD2 = 11.5 V, modulation type 2• 11110b : VTH,MOD2 = 14.5 V, modulation type 2• 11111b : VTH,MOD2 = 20 V, modulation type 2

Table 5.2.2.3-6: Physical Interface Configuration Register 1, locked by SYSCTRL.CONFLOCK

Register PHYCONF2 (0x13)MSB LSB

Content [7:5] TXD_CUR[4:0]

Reset value 0 0 0 0 0 0 0 0Access 0 0 0 R R R R RBit Description [7:5] : reserved

TXD_CUR[4:0] : Transmitter current setting• 00000b : IMOD = 0 mA (default)• 00001b : IMOD = 7.6 mA• ... (+ 7.6 mA steps)• 11111b : IMOD = 240 mA

Table 5.2.2.3-7: Physical Interface Configuration Register 2, locked by SYSCTRL.CONFLOCK




Register TXDDEL (0x20)MSB LSB

Content TXDDEL[7:0]

Reset value 0 0 0 1 0 0 1 1Access R/W R/W R/W R/W R/W R/W R/W R/WBit Description TXDDEL[7:0] : Transmitter delay (TTXD,DEL)

• 00000000b : 0 us (TXD forced directly)• 00000001b : 20 us• 00000010b : 30 us• ... (+ 10 us steps)• 11111111b : 2560 usPlease Note : 1. All timings are referenced to nominal clock frequency 100kHz.2. The total delay from RXD edge to TXD edge for TXDDEL > 0 is:

TTXD,DEL,TOTAL = TTXD,DEL + TRXD,JIT (refer to Fig. 5.2.2.3-8 and Fig. 5.2.2.3-9).3. Reset value = 200 usTable 5.2.2.3-8: Transmitter Configuration : Transmitting delay

Register TXDDUR (0x21)MSB LSB

Content TXDDUR[7:0]

Reset value 0 0 1 0 1 0 0 0Access R/W R/W R/W R/W R/W R/W R/W R/WBit Description TXDDUR[7:0] : TXD pulse duration (TTXD,DUR)

• 00000000b : 0 us• 00000001b : 10 us• ... (+ 10 us steps)• 11111111b : 2550 usPlease Note : 1. All timing are referenced to nominal clock frequency 100kHz.2. For the case TXDDEL = 0x00 the duration is increased by 10 us synchronization

time and TRXD,JIT (refer to Fig. 5.2.2.3-9)3. Reset value = 400 us

Table 5.2.2.3-9: Transmitter Configuration : Transmitting duration




Register RXDCMP1 (0x22)MSB LSB

Content RXDCMP1[7:0]

Reset value 0 0 0 0 0 0 0 0Access R/W R/W R/W R/W R/W R/W R/W R/WBit Description RXDCMP1[7:0] : Receiving timer compare value 1

Started from leading edge, sets flag PHYSTAT.IRQ_CMP1 if RXD_TIMER = RXDCMP1 before trailing edge (refer to Fig. 5.2.2.3-2).• 00000000b : compare function disabled (default)• 00000001b : 20 us• 00000010b : 30 us• ... (+ 10 us steps)• 11111111b : 2560 us

Table 5.2.2.3-10: Receiving Timer Compare Value 1

Register RXDCMP2 (0x23)MSB LSB

Content RXDCMP2[7:0]

Reset value 0 0 0 0 0 0 0 0Access R/W R/W R/W R/W R/W R/W R/W R/WBit Description RXDCMP2[7:0] : Receiving timer compare value 2

Started from trailing edge, sets flag PHYSTAT.IRQ_CMP2 if RXD_TIMER - RXDCAP = RXDCMP2 before next leading edge (refer to Fig. 5.2.2.3-2).• 00000000b : compare function disabled (default)• 00000001b : 20 us• 00000010b : 30 us• ... (+ 10 us steps)• 11111111b : 2560 us

Table 5.2.2.3-11: Receiving Timer Compare Value 2

Register RXDBLK (0x24)MSB LSB

Content RXDBLK[7:0]

Reset value 0 0 0 0 0 0 0 0Access R/W R/W R/W R/W R/W R/W R/W R/WBit Description RXDBLK[7:0] : RXD_TIMER blockage time (refer to Fig. 5.2.2.3-4)

• 00000000b : blockage function disabled (default)• 00000001b : 20 us• 00000010b : 30 us• ... (+ 10 us steps)• 11111111b : 2560 us

Table 5.2.2.3-12: Receiving Timer Blockage Time




Register RXDREAD (0x25)MSB LSB

Content RXDREAD[7:0]

Reset value 0 0 0 0 0 0 0 0Access R/W R/W R/W R/W R/W R/W R/W R/WBit Description RXDREAD[7:0] : RXD_TIMER read time

If RXD_TIMER reaches RXDREAD recent RXD level is stored in PHYSTAT.RXD_RD and flag PHYSTAT.IRQ_READ is set.• 00000000b : read function disabled (default)• 00000001b : 20 us• 00000010b : 30 us• ... (+ 10 us steps)• 11111111b : 2560 us

Table 5.2.2.3-13: Receiving Timer Read TimeRegister RXDCAP (0x26)

MSB LSBContent RXDCAP[

7:0]Reset value 0 0 0 0 0 0 0 0Access R R R R R R R RBit Description RXDCAP[7:0] : RXD timer captured value (read only)

(refer to chapter 5.2.2.3).RXDCAP is captured with the trailing edge, with this event flag PHYSTAT.IRQ_CAP is set.

Table 5.2.2.3-14: Receiving Timer Captured ValueRegister PHYCTRL (0x27)

MSB LSBContent TXD TXD_LAT ENIRQ_T

OFENIRQ_READ

ENIRQ_CMP2

ENIRQ_CMP1

ENIRQ_CAP

ENIRQ_LE

Reset value 0 0 0 0 0 0 0 0Access R/S R R/W R/W R/W R/W R/W R/WBit Description TXD : Bit to be transmitted

This bit is internally buffered and has to be written before the leading edge to be transmitted after the leading edge. The bit for the next leading edge can be written during or even before actual transmission (current forcing). With the leading edge PHYCTRL.TXD is first internally buffered and then automatically cleared.• 0b : no current• 1b : force modulation current IMOD .TXD_LAT : Latched TXDThis bit is TXD latched with leading edge.ENIRQ_TOF : Enable RXD_TOF to generate an interrupt/wakeup.ENIRQ_READ : Enable IRQ_READ to generate an interrupt/wakeup.ENIRQ_CMP2 : Enable IRQ_CMP2 to generate an interrupt/wakeup.ENIRQ_CMP1 : Enable IRQ_CMP1 to generate an interrupt/wakeup.ENIRQ_CAP : Enable IRQ_CAP to generate an interrupt/wakeup.ENIRQ_LE : Enable IRQ_LE to generate an interrupt/wakeup.

Table 5.2.2.3-15: Physical Interface Control Register




Register PHYSTAT (0x28)MSB LSB

Content RXD RXD_RD IRQ_TOF IRQ_READ

IRQ_CMP2

IRQ_CMP1

IRQ_CAP IRQ_LE

Reset value 0 0 0 0 0 0 0 0Access R R R/C R/C R/C R/C R/C R/CBit Description RXD : Recent level of receiving comparator RXD

Synchronized to CLK4M.• 0b : VLN24 < VTH

• 1b : VLN24 > VTH

RXD_RD : Stored level of RXD at reading timeRefer to Fig. 5.2.2.3-3).• 0b : At time RXDREAD after leading edge RXD was 0b,• 1b : at time RXDREAD after leading edge RXD was 1b.IRQ_TOF : Overflow flag of RXD_TIMERTimer is stopped at 0xFF.• bit is set by timer overflow,• bit is cleared by writing a 0b to this location.Flag can be enabled to generate an interrupt/wakeup by PHYCTRL.ENIRQ_TOF.IRQ_READ : Flag for reading functionRefer to Fig. 5.2.2.3-3).• bit is set if RXD_TIMER = RXDREAD,• bit is cleared by writing a 0b to this location.Flag can be enabled to generate an interrupt/wakeup by PHYCTRL.ENIRQ_READ.IRQ_CMP2 : Flag for compare function 2Refer to Fig. 5.2.2.3-2).• bit is set if (RXD_TIMER - RXDCAP) = RXDCMP2 before next leading edge,• bit is cleared by writing a 0b to this location.Flag can be enabled to generate an interrupt/wakeup by PHYCTRL.ENIRQ_CMP2.IRQ_CMP1 : Flag for compare function 1Refer to Fig. 5.2.2.3-2).• bit is set if RXD_TIMER = RXDCMP1 before trailing edge,• bit is cleared by writing a 0b to this location.Flag can be enabled to generate an interrupt/wakeup by PHYCTRL.ENIRQ_CMP1.IRQ_CAP : Flag for timer capture• bit is set by trailing edge on RXD,• bit is cleared by reading register RXDCAP or by writing a 0b to this location.Flag can be enabled to generate an interrupt/wakeup by PHYCTRL.ENIRQ_CAP.IRQ_LE : Flag for leading edge on RXD• bit is set by leading edge (determined by RXDMODE),• bit is cleared by writing a 0b to this location.Flag can be enabled to generate an interrupt/wakeup by PHYCTRL.ENIRQ_LE.

Table 5.2.2.3-16: Physical Interface Status Register




Register PHYMIRQ (0x29)MSB LSB

Content [7:6] MIRQ_TOF

MIRQ_READ

MIRQ_CMP2

MIRQ_CMP1

MIRQ_CAP

MIRQ_LE

Reset value 0 0 0 0 0 0 0 0Access 0 0 R R R R R RBit Description [7:6] : reserved

MIRQ_TOF : Masked overflow flag of RXD_TIMER= IRQ_TOF and ENIRQ_TOFMIRQ_READ : Masked flag for reading function= IRQ_READ and ENIRQ_READMIRQ_CMP2 : Masked flag for compare function 2= IRQ_CMP2 and ENIRQ_CMP2MIRQ_CMP1 : Masked flag for compare function 1= IRQ_CMP1 and ENIRQ_CMP1MIRQ_CAP : Masked flag for timer capture= IRQ_CAP and ENIRQ_CAPMIRQ_LE : Masked flag for leading edge on RXD= IRQ_LE and ENIRQ_LE

Table 5.2.2.3-17: Physical Interface Masked Interrupt Requests Flags (read only)

5.2.2.4 Red Light Interface Control Unit The Red Light Interface Control Unit (IR_RED_CTRL) provides two functions:

1) Transmit current pulses to the external red LED2 via pin RED.2) Receive an interrupt condition via red LED2, to initiate an alarm request.

Red Light TransmittingTo start a pulse on red LED2 the CPU has to write a 1b to register REDCTRL.EN_RED. After TRED,DUR

(refer to Fehler: Referenz nicht gefunden) this bit is automatically cleared.

Red Light ReceivingVia the red LED2 an interrupt request (alarm request) can be forced by illuminating LED2 with a high energy red laser pointer. The red light control unit monitors falling edges on pin LED to detect a configurable period TALARM (refer to Fehler: Referenz nicht gefunden).The detectable period can be configured with REDCONF.ALPER[1:0]. If 8 subsequent falling edges with a period of TALARM are detected, the interrupt request RED_IRQ is set.The final interrupt or wake-up have to be enabled with INTM.RED_IM or WUEN.RED_WE (refer to chapter 5.2.2.1 ,Table 5.2.2.1-1).

Note: To get write access to register REDCONF the configuration lock bit SYSCTRL.CONFLOCK have to be cleared before.




Red Light Control Register DescriptionRegister Name Address Description

REDCONF 0x17 Light Interface Configuration Register,locked by SYSCTRL.CONFLOCK

REDCTRL 0x38 Light Interface Control RegisterTable 5.2.2.4-1: Light Interface Registers

Legend: Internal access: from view of HW block. External access: from view of CPU (programmer).R : read , W : write , S : set , C : clear.

Register REDCONF (0x17)MSB LSB

Content [7:2] ALPER[1:0]

Reset value 0 0 0 0 0 0 1 0Access 0 0 0 0 0 0 R/W R/WBit Description [7:2] : reserved

ALPER[1:0] : Alarm period (refer to Fehler: Referenz nicht gefunden)• 00b : 750 µs (1.3 kHz)• 01b : 500 µs (2 kHz)• 10b : 330 µs (3 kHz, default)• 11b : 250 µs (4 kHz)Note: Nominal timing is referenced to clock frequency 100kHz.

Table 5.2.2.4-2: Light Interface Configuration Register, locked by SYSCTRL.CONFLOCK

Register REDCTRL (0x38)MSB LSB

Content [7:3] RED_IRQ RED EN_REDReset value 0 0 0 0 0 0 0 0Access 0 0 0 0 0 R/C R R/SBit Description [7:3] : reserved

RED_IRQ : Red light interrupt request• bit is set if pulsed light with configured period (ALPER) is detected, i.e. 8

subsequent falling edges,• bit is cleared by writing a 0b to this location.RED : Red light status (read only)• 0b: receiving no light,• 1b: receiving light.EN_RED : Enable red light emitting• bit is set by CPU to start light pulse,• bit is cleared automatically when pulse duration (refer to tRED,DUR in Table 4.1.5-1)

has elapsed.Table 5.2.2.4-3: Light Interface Control Register




5.2.2.5 General Purpose IOs The Smoke Detector provides a free programmable digital interface via pins IO[3:0].

The GPIO unit is activated by setting control bit SYSCTRL.EN_GPIO = 1b.

The register GPIODIR.DIR[3:0] determines the signal direction. A 0b configures the corresponding pad to an input and a 1b to an output pin.

On register GPIOSTAT.GPIO[3:0] the recent status of the pins IO[3:0] can be read (input) or forced (output) depending on its direction GPIODIR.DIR[3:0].

A rising edge or a falling edge on an input pin sets an interrupt request flag on register GPIOSTAT.IRQ_IO[3:0]. GPIOCTRL.IOEDGE[3:0] selects if the flag is set by an rising edge (1b) or an falling edge (0b).

With the local mask GPIOCTRL.ENIRQ_IO[3:0] the flags GPIOSTAT.IRQ_IO[3:0] are masked to determine the interrupt request GPIO_IRQ, which can be read on IRQSTAT.GPIO_IRQ.

The final interrupt or wake-up have to be enabled with INTM.GPIO_IM or WUEN.GPIO_WE (refer to 5.2.2.1).

Fig. 5.2.2.5-1: Block Diagram of GPIO Unit



IRQ_IO[0]

ENIRQ_IO[0]

AND

AND

AND

WUEN012346 57

addr 0x03

INTM012346 57

addr 0x02

GPIO_IRQ

GPIO_WE

GPIO_IMAND

IRQ

STA

T

7

4

5

2

3

0

1

6

addr

0x0

1

AND

GPIO_INT

WAKEUPOR

GPIO_IRQ

ANDOR

IRQ_IO[1]

ENIRQ_IO[1]

IRQ_IO[2]

ENIRQ_IO[2]

IRQ_IO[3]

ENIRQ_IO[3]

GPIOCTRL012346 57

addr 0x0D

'0'

GP

IOD

IR

2

3

0

1

addr

0x0

C

0 1

01

01

01

01

IOEDGE[3]IOEDGE[2]

IOEDGE[1]IOEDGE[0]

edge detectionGPIO Unit

Interrupt and Wake-up Control Unit'0'

0 1'0'

0 1'0'

0 1

GPIOSTAT012346 57

set set set set addr 0x0E

IO0IO1IO2IO3


GPIO Register DescriptionRegister Name Address Description

GPIODIR 0x0C General Purpose IO Direction RegisterGPIOCTRL 0x0D General Purpose IO Control RegisterGPIOSTAT 0x0E General Purpose IO Status RegisterGPIOMIRQ 0x0F Masked Interrupt Request Flags (read only)

Table 5.2.2.5-1: General Purpose IO RegistersLegend: Internal access: from view of HW block. External access: from view of CPU (programmer).


Register GPIODIR (0x0C)MSB LSB

Content [7:4] DIR3 DIR2 DIR1 DIR0Reset value 0 0 0 0 0 0 0 0Access 0 0 0 0 R/W R/W R/W R/WBit Description [7:4] : reserved

DIR3 : Direction of pin IO3• 0b : IO3 is input• 1b : IO3 is outputDIR2 : Direction of pin IO2• 0b : IO2 is input• 1b : IO2 is outputDIR1 : Direction of pin IO1• 0b : IO1 is input• 1b : IO1 is outputDIR0 : Direction of pin IO0• 0b : IO0 is input• 1b : IO0 is output

Table 5.2.2.5-2: General Purpose IO Direction Register




Register GPIOCTRL (0x0D)MSB LSB

Content ENIRQ_IO3

ENIRQ_IO2

ENIRQ_IO1

ENIRQ_IO0

IOEDGE3 IOEDGE2 IOEDGE1 IOEDGE0

Reset value 0 0 0 0 0 0 0 0Access R/W R/W R/W R/W R/W R/W R/W R/WBit Description ENIRQ_IO3 : Local interrupt enable for pin IO3

• 0b : disabled,• 1b : enabled.ENIRQ_IO2 : Local interrupt enable for pin IO2• 0b : disabled,• 1b : enabled.ENIRQ_IO1 : Local interrupt enable for pin IO1• 0b : disabled,• 1b : enabled.ENIRQ_IO0 : Local interrupt enable for pin IO0• 0b : disabled,• 1b : enabled.IOEDGE3 : Select edge for interrupt flag on pin IO3• 0b : falling edge on IO3 sets the interrupt request flag GPIOSTAT.IRQ_IO3 if

GPIODIR.DIR3 = 0b.• 1b : rising edge on IO3 sets the interrupt request flag GPIOSTAT.IRQ_IO3 if

GPIODIR.DIR3 = 0b.IOEDGE2 : Select edge for interrupt flag on pin IO2• 0b : falling edge on IO2 sets the interrupt request flag GPIOSTAT.IRQ_IO2 if






GPIODIR.DIR0 = 0b.Table 5.2.2.5-3: General Purpose IO Control Register




Register GPIOSTAT (0x0E)MSB LSB

Content IRQ_IO3 IRQ_IO2 IRQ_IO1 IRQ_IO0 GPIO3 GPIO2 GPIO1 GPIO0Reset value 0 0 0 0 0 0 0 0Access R/C R/C R/C R/C R/W R/W R/W R/WBit Description IRQ_IO3 : Interrupt request flag for IO3

• bit is set by an edge on IO3, if GPIODIR.DIR3 = 0b (input), GPIOCTRL.IOEDGE3 selects if this bit is set by a rising edge (1b) or a falling edge (ob),

• bit is cleared by writing a 0b to GPIO3.IRQ_IO2 : Interrupt request flag for IO2• bit is set by an edge on IO2, if GPIODIR.DIR2 = 0b (input), GPIOCTRL.IOEDGE2

selects if this bit is set by a rising edge (1b) or a falling edge (ob),• bit is cleared by writing a 0b to GPIO2.IRQ_IO1 : Interrupt request flag for IO1• bit is set by an edge on IO1, if GPIODIR.DIR1 = 0b (input), GPIOCTRL.IOEDGE1

selects if this bit is set by a rising edge (1b) or a falling edge (ob),• bit is cleared by writing a 0b to GPIO1.IRQ_IO0 : Interrupt request flag for IO0• bit is set by an edge on IO0, if GPIODIR.DIR0 = 0b (input), GPIOCTRL.IOEDGE0

selects if this bit is set by a rising edge (1b) or a falling edge (ob),• bit is cleared by writing a 0b to GPIO0.GPIO3 : Status bit on pin IO3Depending on GPIODIR.DIR3, CPU can read recent input or force the output.GPIO2 : Status bit on pin IO2Depending on GPIODIR.DIR2, CPU can read recent input or force the output.GPIO1 : Status bit on pin IO1Depending on GPIODIR.DIR1, CPU can read recent input or force the output.GPIO0 : Status bit on pin IO0Depending on GPIODIR.DIR0, CPU can read recent input or force the output.

Table 5.2.2.5-4: General Purpose IO Status Register

Register GPIOMIRQ (0x0F)MSB LSB

Content MIRQ_IO3

MIRQ_IO2

MIRQ_IO1

MIRQ_IO0

[3:0]

Reset value 0 0 0 0 0 0 0 0Access R R R R R R R RBit Description MIRQ_IO3 : Masked interrupt request flag for IO3

= IRQ_IO3 and ENIRQ_IO3MIRQ_IO2 : Masked interrupt request flag for IO2= IRQ_IO2 and ENIRQ_IO2MIRQ_IO1 : Masked interrupt request flag for IO1= IRQ_IO1 and ENIRQ_IO1MIRQ_IO0 : Masked interrupt request flag for IO0= IRQ_IO0 and ENIRQ_IO0[3:0] : reserved

Table 5.2.2.5-5: Masked Interrupt Request Flags (read only)




5.2.2.6 Watchdog To provide reliability of software the watchdog unit covers two functions:

1. Configurable timeout for CPU active time2. Configurable slow watchdog trigger

After power-up both watchdog functions are immediately enabled with default setting (TACT = 8 ms , TWD = 2 s , i.e. WDCONF = 0x0D).The first write access to register WDCONF should write watchdog configuration to lock configuration until next reset (all reset source, refer to 5.2.2.1). For this the CPU should write value unequal to 0x5 to the high nibble of WDCONF.If first written value is watchdog trigger 0x55, then watchdog configuration is locked with default values.

Timeout for CPU Active TimeWith WDCONF.ACTTIME[1:0] the maximum allowed active time TACT can be selected between 1 ms and 8 ms.If TACT has elapsed the watchdog generates a system reset. This prevents to run out of power by a too long active time of CPU. This function runs with the slow clock CLK100K. Its timer is reseted with a sleep command SYSCTRL.CPU_OFF = 1b and enabled with a CPU wake-up.

Slow WatchdogThe slow timer observes if the CPU is hooked unintentionally in sleep mode.To trigger the watchdog a 0x55 has to be written to address 0x08 before the watchdog time TWD has elapsed. With a valid trigger the watchdog timer is restarted. A missing trigger after watchdog time leads to a system reset. This function also runs with the slow clock CLK100K.

Watchdog Register DescriptionRegister Name Address Description

WDCONF 0x08 Watchdog Configuration Register,automatically locked after first write access.Table 5.2.2.6-1: Watchdog Registers

Legend: Internal access: from view of HW block. External access: from view of CPU (programmer).R : read , W : write , S : set , C : clear.




Register WDCONF (0x08)MSB LSB

Content WDCONF[7:0]

ACTTIME[1:0]

WDTIME[1:0]

Reset value - - - - 1 1 0 1Access W W W W R/W R/W R/W R/WBit Description WDCONF[7:0] : Note:

The first write access to this register serves as first watchdog trigger and locks the configuration (ACTTIME[1:0] and WDTIME[1:0]) for any further write access.First write access:• WDCONF[7:4] = 0x5 : default watchdog setting is locked,• WDCONF[7:4] 0x5 : WDCONF[3:0] is configured and locked.Any next trigger is generated by writing 0x55 to this register addressACTTIME[1:0] : CPU active time• 00b : TACT = 0.96 ms• 01b : TACT = 2.24 ms• 10b : TACT = 4.16 ms• 11b : TACT = 8.00 msWDTIME[1:0] : Watchdog trigger time• 00b : TWD = 1.024 s• 01b : TWD = 2.048 s• 10b : TWD = 3.072 s• 11b : TWD = 4.096 s

Table 5.2.2.6-2: Watchdog Configuration Register, automatically locked after first write access.




5.2.2.7 Universal Timer The timer is implemented as a 16 bit up counter. The timer uses low frequency clock.To ensure the readout of consistent timer values the timer low byte is latched if the timer high byte is read. The capture register can be used to generated defined timer capture interrupts.The special multiplexer can be used to capture one of the input channels such as the four GPIO inputs, physical RXD or red RXD.

Description of Universal Timer RegistersRegister Name Address Description

TSTAT 0x40 Timer Status RegisterTCTRL 0x41 Timer Control RegisterTIMH 0x42 Recent Timer Value (high byte)TIML 0x43 Recent Timer Value (low byte)TCMPH 0x44 Timer Compare Register (high byte)TCMPL 0x45 Timer Compare Value (low byte)TCAPH 0x46 Timer Captured Value (high byte)TCAPL 0x47 Timer Captured Value (low byte)

Table 5.2.2.7-1: Universal Timer RegistersLegend: Internal access: from view of HW block. External access: from view of CPU (programmer).


Register TSTAT (0x40)MSB LSB

Content ICF OCF TOF [4:2] CMPR RSTReset value 0 0 0 0 0 0 0 0Access R/C R/C R/C 0 0 0 R/W WBit Description ICF : Flag for input capture

• flag is set by timer hardware when timer value is captured,• flag is cleared by reading low byte of captured value (TCAPL) or writing a 0b to this

location.OCF : Flag for output compare• flag is set by timer hardware when values of TIMH/TIML and of TCMPH/TCMPL

register matches. No further comparison is made until the OCF bit is cleared,• flag is cleared by reading of the TCMPL register or writing a 0b to this location.TOF : Flag for timer overflow • flag is set by timer hardware in case of overflow,• flag is cleared by writing a 0b to this location.[4:2] : reservedCMPR : Enable compare timer reset • 0b : disabled,• 1b : enabled, timer is reset if it reaches compare value TCMPH/TCMPL.RST : Reset command for timer • write 1b to reset timer value,• bit is automatically cleared.

Table 5.2.2.7-2: Timer Status Register




Register TCTRL (0x41)MSB LSB

Content ICIE OCIE TOFIE INTD CSEL[2:0]

EDGE

Reset value 0 0 0 1 0 0 0 0Access R/W R/W R/W R/W R/W R/W R/W R/WBit Description ICIE : Interrupt enable for input capture

• 0b : disabled,• 1b : enabled.OCIE : Interrupt enable for output compare• 0b : disabled,• 1b : enabled.TOFIE : Interrupt enable for timer overflow• 0b : disabled,• 1b : enabled.INTD : Interrupt disable for all timer interrupts• 0b : not disabled,• 1b : all interrupts are disabled.CSEL[2:0] : Select capture signal• 000b : capture function is disabled (default)• 001b : IO[0]• 010b : IO[1]• 011b : IO[2]• 100b : IO[3]• 101b : PHY RXD• 110b : RED RXD• 111b : capture function is disabledEDGE : Select capture edge• 0b : falling edge,• 1b : rising edge.

Table 5.2.2.7-3: Timer Control Register

Register TIMH (0x42)MSB LSB

Content TIM[15:8]Reset value 0 0 0 0 0 0 0 0Access R R R R R R R RBit Description TIM[15:8] : High byte of timer register (read only)

Table 5.2.2.7-4: Recent Timer Value (high byte)

Register TIML (0x43)MSB LSB

Content TIM[7:0]Reset value 0 0 0 0 0 0 0 0Access R R R R R R R RBit Description TIM[7:0] : Low byte of timer register (read only)

Table 5.2.2.7-5: Recent Timer Value (low byte)




Register TCMPH (0x44)MSB LSB

Content TCMP[15:8]

Reset value 0 0 0 0 0 0 0 0Access R/W R/W R/W R/W R/W R/W R/W R/WBit Description TCMP[15:8] : High byte of timer compare register

Table 5.2.2.7-6: Timer Compare Register (high byte)Register TCMPL (0x45)

MSB LSBContent TCMP[7:

0]Reset value 0 0 0 0 0 0 0 0Access R/W R/W R/W R/W R/W R/W R/W R/WBit Description TCMP[7:0] : Low byte of timer compare register

Table 5.2.2.7-7: Timer Compare Value (low byte)Register TCAPH (0x46)

MSB LSBContent TCAP[15:

8]Reset value 0 0 0 0 0 0 0 0Access R R R R R R R RBit Description TCAP[15:8] : Low byte of timer capture register (read only)

Table 5.2.2.7-8: Timer Captured Value (high byte)Register TCAPL (0x47)

MSB LSBContent TCAP[7:0

]Reset value 0 0 0 0 0 0 0 0Access R R R R R R R RBit Description TCAP[7:0] : Low byte of timer capture register (read only)

Table 5.2.2.7-9: Timer Captured Value (low byte)

5.2.2.8 Special Function Registers (SFR) The following registers Table 5.2.2.8-1 are implemented in the special function register block, but described in other chapters. All SFR registers are locked (not writable), if SYSCTRL.CONFLOCK = 1b.

Register Description Address ChapterOSCTRIM Oscillator trimming register 0x10 5.2.2.1POWCONF Power configuration regfister 0x11 5.2.2.1PHYCONF1 Physical interface configuration register 1 0x12 5.2.2.3PHYCONF2 Physical interface configuration register 2 0x13 5.2.2.3LEDCONF LED configuration register 0x14 5.2.2.2




Register Description Address ChapterAMPCONF Amplifier configuration register 0x15 5.2.2.2MECONF Measurement configuration register 0x16 5.2.2.2REDCONF Red light interface configuration register 0x17 5.2.2.4

Table 5.2.2.8-1: Special Function Registers

5.2.3 Power ManagementThe IC is basically supplied from the tank capacitor C1 connected to pin D5. The constant current drawn from the loop line (pin LN24) is set by SUP_MODE (Table 5.2.3-1). While the IC is in sleep mode the charge current out of pin D5 into C1 is limited by current drawn from the loop line except current fraction that is consumed by always active IC blocks. Once the IC is woken up for taking a measurement the current at pin D5 reverses and discharges C1, while the current drawn from the loop line remains constant. Overall the average current into D5 must be less than the current limit set by SUP_MODE in order to avoid the charge in C1 fading away. The following table shows the IC's current consumption at pin D5 for all active operating modes. From these you can calculate the average current for a measurement cycle considering your individual configurations.

Mode Symbol Register State Current into pin D5

Duration Time in measuring cycle

Sleep mode - 23uA 0.8s .. 4sprogram depended

Start-up after power on

tCPU_POR SYSCTRL.EEWU_EN=1 1.7mA 2ms(*)only after power on

LN24 RXD processing

tCPU_RXD SYSCTRL.EEWU_EN=0 1.0mA 5us/bit(*)

RED RXD processing

tCPU_RED SYSCTRL.EEWU_EN=0 1.0mA 5us/bit(*)

Measure: amplifier initialisation

tINIT

refer toMECONF.MEMODE=0MECTRL.SSME=1orMECONF.MEMODE=1

0.4mA 7.4ms

Temperature measurement

tTEMP

refer toMECTRL.TME_EN=1 0.54mA + external

temperature half bridge current

20us

Measure: CPU processing

tACTIVE

refer toSYSCTRL.EEWU_EN=0 1.5mA 0.3ms .. 2ms

program depended

LED flash tLED

refer toMECTRL.LED_EN=1SYSCTRL.EEWU_EN=0

4.5mA + 1.5mA CPU + (0..200mA) LED current

0.1ms

RED flash tRED_DUR REDCTRL.EN_RED=1 5mA 2msTable 5.2.3-1: Current Consumption




6 Register TableRegister Name Address Description

IRQSTAT 0x01 Interrupt Request Status RegisterINTM 0x02 Interrupt Unmask Register, locked by SYSCTRL.CONFLOCKWUEN 0x03 Wake-up Enable Register, locked by SYSCTRL.CONFLOCKSYSCTRL 0x04 System Control RegisterIRQ_MSKD 0x05 Masked Interrupt StatusSYSSTAT 0x06 System Status RegisterWDCONF 0x08 Watchdog Configuration Register,

automatically locked after first write access.GPIODIR 0x0C General Purpose IO Direction RegisterGPIOCTRL 0x0D General Purpose IO Control RegisterGPIOSTAT 0x0E General Purpose IO Status RegisterGPIOMIRQ 0x0F Masked Interrupt Request Flags (read only)OSCTRIM 0x10 Oscillators Trimming Register,

located in SFR, locked by SYSCTRL.CONFLOCKPOWCONF 0x11 Power Configuration Register,

located in SFR, locked by SYSCTRL.CONFLOCKPHYCONF1 0x12 Physical Interface Configuration Register 1,

locked by SYSCTRL.CONFLOCKPHYCONF2 0x13 Physical Interface Configuration Register 2,

locked by SYSCTRL.CONFLOCKLEDCONF 0x14 LED1 configuration register,

locked by SYSCTRL.CONFLOCKAMPCONF 0x15 Current-to-voltage converter/amplifier configuration register,

locked by SYSCTRL.CONFLOCK.MECONF 0x16 Measurement configuration register,

locked by SYSCTRL.CONFLOCK.REDCONF 0x17 Light Interface Configuration Register,

locked by SYSCTRL.CONFLOCKTXDDEL 0x20 Transmitter Configuration : Transmitting delayTXDDUR 0x21 Transmitter Configuration : Transmitting durationRXDCMP1 0x22 Receiving Timer Compare Value 1RXDCMP2 0x23 Receiving Timer Compare Value 2RXDBLK 0x24 Receiving Timer Blockage TimeRXDREAD 0x25 Receiving Timer Read TimeRXDCAP 0x26 Receiving Timer Captured ValuePHYCTRL 0x27 Physical Interface Control RegisterPHYSTAT 0x28 Physical Interface Status RegisterPHYMIRQ 0x29 Physical Interface Masked Interrupt Requests Flags (read only)ADCVAL10_H 0x30 High byte 10 bit ADC valueADCVAL10_L 0x31 Low byte 10 bit ADC valueADCVAL8 0x32 8 bit ADC valueMECTRL 0x33 Measurement Control RegisterREDCTRL 0x38 Light Interface Control Register




Register Name Address DescriptionTSTAT 0x40 Timer Status RegisterTCTRL 0x41 Timer Control RegisterTIMH 0x42 Recent Timer Value (high byte)TIML 0x43 Recent Timer Value (low byte)TCMPH 0x44 Timer Compare Register (high byte)TCMPL 0x45 Timer Compare Value (low byte)TCAPH 0x46 Timer Captured Value (high byte)TCAPL 0x47 Timer Captured Value (low byte)EECFG 0x50 EEPROM Configuration RegisterEEPLCK 0x51 EEPROM Programming Lock RegisterEECTRL 0x52 EEPROM Control RegisterEESTAT 0x53 EEPROM Status RegisterEEMIRQ 0x54 EEPROM Masked Interrupt Requests Flags (read only)

Table 6-1: Register Table




7 Package InformationThe E520.32 is available in a Pb free, RoHs compliant, SO14 plastic package according to JEDEC MS-012-F, variant AB.The package is classified to Moisture Sensitivity Level 3 (MSL 3) according to JEDEC J-STD-020 with a soldering peak temperature of (260 + 5)°C.

Note: Thermal resistance junction to ambient RTH,JA is 97°C/W, based on standard JESD-51-5.

Note: Dimensions in mm are are true, inch dimensions contain rounding errors.




- Page intentionally left blank -

Rev. Description of change Date(E.00) Initial manuscript draft (Internal Rev. No. 1.0)

E.01 Pg. 1: Feature list updated, ordering information added.Tab. 2.1.1.1-1, #12: Supply monitor hysteresisTab. 2.1.2-1, Changed “up modulation” to Type1, “down modulation” to Type2

#6: Input threshold for modulation Type 2 VTH,MOD2,30 changed#7: Input threshold for modulation Type 2 VTH,MOD2,31 changed#8 Maximum programmable modulation current IMOD_MAX change#9: Modulation current programming step, condition changed#10: Voltage drop at modulator VMOD_DROP #11: Voltage drop at modulator VMOD_DROP_50

Tab. 2.1.3-1 #1: Maximum LED current programming, added condition#2: LED current programming step, added condition

Tab. 2.1.4.1-1 #3: Detector conversion factor programming step changedTab. 2.1.4.3-1 Removed parameters DNL, INL, new parameter Resolution,

added footnoteTab. 2.1.5-1 #2, #5: added footnotes and changed condition

#6: New parameter temperature coefficient of impedanceCh. 3.1.5 Corrected table 3.1.5-1 Current consumptionCh. 3.3.2.1.3 Updated description of IRQSTAT.ME_IRQ (Tab. 3.3.2.1.3-2)

21 May 2012

E.01 Page 1: Temperature Range extended to -55°CCh. 1: ϑJ,max increased to 90°C; Ch. 1 & Ch. 3: ϑAMB,max incr. to 85°C, ϑAMB,B,EXT to 85°CTable 4.1.2-1: Modulation thresholds (#4 - #7) changed; #8 added minimum spec Ch. 5.2.3 power management chapter moved from Functional Description (ch. 5 ), removed description “analog part”Table 5.2.1.5-3, #15: changed to “EESTAT.IRQ_PGM”

30 Aug. 2012

E.02 Ch. 5.2.1.5 EEPROM, Description of Erasing and Programmin procedures 09 Oct. 2012






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8 Index

Table of ContentPin Description.................................................................................................................................... 3

1 Absolute Maximum Ratings................................................................................................................... 42 Electro-Static Discharge (ESD).............................................................................................................43 Recommended Operating Conditions...................................................................................................54 Electrical Characteristics....................................................................................................................... 6

4.1 Analog Characteristics.................................................................................................................. 64.1.1 Supply and References.........................................................................................................64.1.2 Physical Interface via Bus Terminal LN24.............................................................................74.1.3 LED Driver for Smoke Chamber............................................................................................74.1.4 Smoke Detection and Temperature Measurement Channel.................................................84.1.5 RED Light Interface...............................................................................................................94.1.6 Oscillators............................................................................................................................. 9

4.2 Digital Characteristics..................................................................................................................104.2.1 Central Processing Unit (CPU)............................................................................................104.2.2 Periphery............................................................................................................................. 10

5 Functional Description ........................................................................................................................115.1 General Functional Description...................................................................................................11

5.1.1 Smoke Detection................................................................................................................. 125.1.2 Temperature Measurement.................................................................................................125.1.3 Bus Interface via Supply Terminal LN24.............................................................................125.1.4 Red Light Interface..............................................................................................................13

5.2 Detailed Functional Description...................................................................................................145.2.1 Central Processing Unit (CPU)............................................................................................14

5.2.1.1 CPU EL3.5 Core..........................................................................................................145.2.1.2 Memory Map - Base Address Table............................................................................235.2.1.3 Interrupt vector............................................................................................................255.2.1.4 RAM............................................................................................................................ 255.2.1.5 E²PROM...................................................................................................................... 255.2.1.6 FLASH......................................................................................................................... 31

5.2.2 Periphery............................................................................................................................. 315.2.2.1 Main Control Unit.........................................................................................................315.2.2.2 Measurement Control Unit..........................................................................................375.2.2.3 Physical Interface Control Unit....................................................................................485.2.2.4 Red Light Interface Control Unit..................................................................................605.2.2.5 General Purpose IOs...................................................................................................625.2.2.6 Watchdog....................................................................................................................665.2.2.7 Universal Timer...........................................................................................................685.2.2.8 Special Function Registers (SFR)...............................................................................70

5.2.3 Power Management............................................................................................................716 Register Table..................................................................................................................................... 727 Package Information........................................................................................................................... 748 Index................................................................................................................................................... 77



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