INTRASYSTM EM1 CONTROL IN HIGH FREQUENCY COMMUNICATION SYSTEM

MOMBASAWALA M. J., G. DHARMARAJ & NARESH MADAN

Centre for Development of Telematics (C-DOT) 39, Main Pusa Road, New Delhi -110005 (INDIA)

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tabulated in Table - 1. The analysis of each component for BTL case is described in brief in this section. ABSTRACT :

This paper describes some noise reduction techniques and Eh4I control for high frequency telecommunication system which operates on internal clock frequency between 20 Mhz to 100 Mhz. Various power distribution techniques, signal and clock distribution and grounding structures were tried. Methods giving better results are described here. These if implemented in early design stage saves substantial design time and efforts.

1. INTRODUCTION :

One of the most serious problem brought about by an increase of operating frequency in telecom system is EM1

Table - 1 : Noise component weightage a id noise. This results out of the use of very fast logic in designs. Much of the EM1 control implementation described here belongs to the SDH system. SDH is an 2.1 Powcr Supply Noise : optical fibre based Synchronous Multiplexer and uses

The noise on 50mV is according to the design practice mostly digital circuit in its implementation. The internal With SMPS power supply, (-48V input to +5V output) operating frequency of the system is approximately PARD of 5OniV is easily achievable. 2OMbp.9, while tlie interface frequency to the external

world varies between 2Mbps (electrical) to 622Mbps (optical). The logic used in the realization of system has 202 Groul'd Bounce : typical risetime of 1 to 3 nsec. Because of these shoots,

The inductance of the lead in a device package, the large amount of EMI is associated with the circuit which includes reflections, crosstalk, ground bounce and radiated inductance of tlie connector pin and the inductance of the

ground plane of the PCB together forms a inductancc EMI. The control mechanism and the noise budgeting is described in Section -2. also ot-iginates out of which results into the shift of ground because of the ground loops depends ol, the location of switching current flowing through it. This shift in the comlnunicatillg devices system. ground loops internal ground reference voltage due to switching is called

in Section - 3. The device level EM1 reduction is described in Section - 4. Section - 5 deals with the grounding and earthing philosophy for telecom system.

2. NOISE BUDGETING :

Noise budgeting is required to ensure the operation of circuit in presence of noise. If the noise exceeds the noise margin of 1Wic circuits, it can lead to false triggering and high BER. Noise gets added to a signal in 3 places, viz. at the transmitter, at the transmission medium an8 at the receiver. It is assumed that the noise gets added in a simple algebraic manner [l],(wliich is not always the case) as

can be minimized by power supply distribution described ground bOUnCe. The magnitude of the ground bounce IS

give'' b!'lll Vgmi = Lgwi (ddt)Iciacliarge or I VWla 1 = Lx(( 1.52xV)+Trz)xC

....................... I

..................... 2

Consider DS3893 BTL turbo transceiver device driving BTL bus. The Rise time Tf= Package = PLCC-20, Therefore LyU, = 5nH

Ish* with 3')12 termination = 50 " c= Device Output

characteristics

swillg = ' Capacita11ce 37 pF

With Metral connector of Lpm = 23.4nH and the g~aund plane of 50" x 150" x 35pm size, the ground bounce with four ground plane in parallel is,

2

3

4

With the same parameters as listed in this section the measured value of ground bounce fer synchronous signal for DS3893 chip is 28mV, well within the hudget.

2.3 Voltage Distribution IZ d r q :

No guard trace Microstrip, K=0.25, lOOmV 83mV With guard trace Stripline, K=O.125, 50mV 32mV No guard trace Stripline, K=0.06, 50mV 21mV With guard trace

The large ground plane do riot &er zero impedance[4]. Typical ground plane impewce is expfessed in ohmdsq. andforthesizeof&eg"ee€s@m2.2thedc resistance is 0 .615m. With four planes in parallel and for the current of 5A flowing through the plane, the IZ drop is 1.85mV well within the budget.

2.4 Strip Crosstalk :

sstalk !&ween two conductors depends upon the mutual inductance and their mutual capacitance. Usually in digital problems, the inductive crosstalk is as big or larger than capacitive crosstalk. So we will concentrate on the inductive coupling mechanism and the crosstalk tesulting from it11 J. The crosstalk is given by, (refer fig -1)

Crosstalk = k+(l+(D+lQ2) ....................... 3

Where D = Distance between two traces H = Height of the trace from the GND plane E+ = Dielectric constant of the PCB K = Constant

I Trace

7-0 Trace -

I D

IH

1 GNRPlane ~r

L

Fig -1 : Crosstalk between two PCB traces

epends on the circuit risetime T, and the rfering traces. It is always less than 1. For

= €8 mils, IC= 0.5 and D= 22mils,

stalk 2OOmV (not acceptable).

The case shown in figure-1 is microstrip where the ground plane is located only on one $de of the trace. In case of stripline where the trace is surrounded by the ground plane on both the sides with similar value of W, the value of K of equation -3 is halved as compared to the microstrip case. Also the coupling between the traces in microstrip or stripline is halved by inserting a third line, grounded at both ends, between them. The coupling is halved again if the third line connects through Vias to local ground plane at regular intervals ( preferably 0.5")[51.

Table -2 shown the theoretically computed value of crosstalk and the experimental results obtained with the setup shown in fig-2[8]. The parameters are T, = 1 nsec, L = IOfi, D = 22 mils and H = 18 mils.

1 1 I Microstrip, K=0.5, I 200mV I 144mV I

Table -2 : Crosstalk value comparison

4+2.1v

+2.1v

Fig -2 : Crosstalk measurement setup

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2.5 Reflections : 20’ = Zo+(dl+Cd+Co) .................................... 6

The PCB traces cany high frequency signals from one end to the other. The length of the ljne in many cases is large enough to relate the propagation delay of the signal along the line to the rise or fall time of the signal carried by it. If the trace behaves like lumped circuit, theb the transmission line effects are not seen and no ringing and overshoot OCCUTS.

There is a general rule of the thumb that if the length of the line is less than one sixth of the length of the risetime, then the line behaves like lumped circuit and transmission line effects are not seen i.e.

Length of the trace <e 116 Len@ of T,

The key factor in determining if a trace should be treated as a transmission line rather than lumped load is

2 x Tpd x Trace length > T, ...................... 4

Where Tpd = Propagation delay per unit length of line

For T,=l nsec, transmission line effect will be observed if the length oftrace is more than 3”. The reflections can be avoided if forward and reverse reflection coefficients are zero. This requixes the load impedance equal to the trace characteristic impedance (loaded) Zo’ and Zo’ to the impedance of the driving devices output.

The budget for the reflection is 80mV, i.e. 8% of 1V swing available in BTL devices. A 10% error in transmission line impedance makes a 5% reflection. Therefore given the budget of reflection, it need to be doubled to find the allowed mismatch between the characteristi0 impedance and the terminating device impedance. For the budget under consideration, 8% of reflection leaves room for 16% of mismatch. If 8% tolerance is left for terminating device, 8% tolerance is available for tolerance in the chracteristic impedance.

The characteristic impedance Zo for stripline case is[9]

Zo = {60+c}x I~{~BG(O.~~X~~~W(O,~+T+W))} .......... 5

Where B = Separation betweep adjacent planes W = Width of the trace T = Height of the trace E, =Dielectric constant = 4.6 EOr FR-4 material

For FR-4 material Tpd = 2.2df i and for Zo = SOQ, CO = 2 . 2 ~ 5 0 = 4.4pF/ft.

For 10” trace with 4 vias, CO = 44x 10+12 + (0.5~4) = 38.66pF

For BTL bus in Cd max = 32.SpF and Cd m h = 16.4pF and therefore for Zo’ = 39Q, Zo max = 5 3 0 and 20 min = 32.8!2. This gives the average value of Zo = WOR

Therefore it can be seen that the trace length for BTL driven traces should be made with Zo = 500. This needs a 12 mils trace with H = 16mils (B= 33.4mils) and T = 1.4 mils (loz copper).

2.6 Radiated EM1 :

Electro magnetic interference @MI) emates from signal current flowing in large loops. In SDH system agairi concentrating on the bus which h e driven from the end and terminated from other end, the loop area of the signal. flowing is substantial. Figure - 3 shows the cross section of the connector having an add drop bus.

<..---.-‘.*--.- --. ‘. Loop i

L ............. ..................

Fig - 3 : Radiated EM1 from the loop

Such large loop causes lot of radiation for high frequency signal. The loop consisting of neariy 10” track and IO” return path (because at high frequency the signal return is through the path of least inductance which is below signal track) separated by nearly 0.4” distance. The loop formed will have an arc of 10~0.0157 square inch = 0.135 sq. inch. Therefore, A = 0.15 square inch. Above 30 Mhz both FCC & VDE limits are approximately 100pV/m as measured 3 m away from the equipment. The same value will k accepted for our calculation even though our signal frqwwy i s 20 Mhz.

The loaded impedance is,

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Calcukhg precise radiqteQ intensity levels from a digitzzl IKDQ13ct 4 a chancy business btxause se many factors affect

the outcome. Equation -7 meets the FCC & W E radiated emission limits and is the simple relation in turns of loop area, peak current, clock frequency and switching times of driven signal[ I ] .

E(in)

E = [1.4x10'18~A~Ip~Fc~,c~+(T10-90)1 V/m ....................... 7

37% 37% 37% loss loss loss

Where E = radiated electric field V/m at 3 meters A = radiating loop area in inch square I, = Peak current in Ampere Tlo-90 = signal rise time in Second Fclock = Clock frequency in Hz A = 0.15 sq. inch Ip = 50 mA Tlo-90 = 3nS = 3 ~ 1 0 - ~ Sec

E - 70 pV/m

For

Fclock = 20 Mhz = 20 x 1 O6 Hz,

The above value of field E isdue to one signal. For N signal the field will be either 9N or N times depending on signal correlation. For random signals the total emission is proportional to the sq. root of the number of signals and for correlated signals (such as clock lines), the emission can be as much as directly proportional to the number of signals.

Considering 12 signals in one metral connector and 12 signals per bus(which is the actual case) the effective number of signals will be average of n 2 and 12. We will assume it as Nt2 and the value is 6. This gives the value o f E a s : E total bus = 420pV at 3mt from system.

E(in)

The result is alarming and needs shielding of connector pins on backside to bring it down to the FCC acceptable limits.

37% 37% 37% loss loss loss

For a metallic shield, the reduction in the field strength per skin depth will be 37% as shown in fig - 4.

I One Skin Depth/

E(out)

'ig -4 : Loss in E in metal sheet due to skin effect

For steel, the skin depth of 20 Mhz frequency is 0.000003 inch. If I mm of shield is used the number of skin depths are 13123. For 420pV/m field input the output will be 4 2 0 ~ ( 0 . 6 7 ) ' ~ ' ~ ~ This means the field strength will be attenuated by nearly 114170 dB, meaning a very good shield bringing the equipment within FCC limits Therefore the back shield on the connector is strictly envisaged for SDH system.

2.7 Connector Crosstalk :

The crosstalk in the connector can be calculated theoretically and can be verified experimentally by SPICE simulation. The simulation result provided by manufacturer for metral connector indicates 6% crosstalk for lpsec risetime, i.e. 60mV for 1V BTL swing, if T, = Ipsec. Since T, = lnsec for BTL, the crosstalk which is proportional to T;' will be lo6 times less and will always fall within the set budget of 25mV.

2.8 Revised Noise Budget :

Depending on the above analysis the noise budget can be generalized for different families in percentage of available noise margin. This is indicated in Table - 3.

I Total

Table - 3 : Revised Noise Budget

Available margm = 6% of noise margin specified by the manufacturer. Likewise the budget can be made for any other logic family. It is important to note that his weightage given to noise component is according to SDH product design. For any other product, if the parameters change, the weightage to the budget allotted will change and it is required that the algebraic addition oP noise budget does not exceed the available noise margin. Otherwise the system performance cannot be guaranteed.

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2.9 PCB Layer Buildup :

To attain the noise budget of section - 2.8, it is required that the trace width W=121nils with H=16mils to give Zo=5OQ in stripline case. These traces should be separated by at least lOmils to keep crosstalk within limits. Also, all BTL signal lines with length more than 3" should be terminated to avoid reflection. The termination should preferably be done on the Backplane. Since the maximum length of the trace appears on Backplane, the PCB buildup for Backplane of 3.2" thickness is shown in fig -5.

Component 1 Smiisf GNDl

Inner 1 I6m GND2

GND3 Inner2

GND4 1 Sm Solder

Copper thickness on each layer = loz = 35pm Total PCB thickness = 3.2"

Fig-5 : PCB buildup to realize Noise Budget

3. Ground Loop Minimization :

The system which operates with low frequency f < 10 Mhz does not have much ground loop problems because as seen in Equation -7 of Sec 2.6, even if A is more, Fclock is low giving small E. However, for SDH kind of system with internal clock of 20 Mhz, the ground loop problem is much more serious[2,4].

In order to keep ground loops to minimum the system should use separated power supply for separate circuit. The realizable technique is to provide power supply on each card called On Board Power Supply (OBPS). The OBPS generates +5v, -5v, +12v and -12v for card from - 48V input to it and its output and input ground should have a high degree of isolation. The use of OBPS confines ground loops only to a card level. Consider fig-6a where centralized power supply exist. In this case the common impedance path is taken by all cards through loops L1, L2, L3 etc. However, in figdb with distributed power supply the loops gets coniined to cards only and therefore poses much less tlireat to the system performance due to interference. In this case the loop formation on Motherboard (Backplane) can be completely avoided.

> ... / .....

Ground S : Supply, C : card and L : Ground Loop

Fig - 6a : Ground loop with centralized Power Supply

Ground S : Supply, C : Card and L : Ground Loop

Fig : 6b : Ground Loops with Distributed Power Supply

Also in backplane connection the signal from one card to another card is through track and the return path will be just below the track through the ground plane. The routing on the motherboard should be planned in such a manner that two high frequency return paths do not cross each other and if they run parallel, their separation should be atleast 3 times the width of the track. If this is done, the common impedance coupling on the motherboard is completely avoided.

The formation of ground loop on cards can be minimized by ground segregation in such a way that the same ground plane gets connected to the ground planes of the motherboard for return path(41. The grounds separated on card level basis are :

1. -48V ground 2. Digigd ground 3. analog ground 4. BTL ground 5. VO ground

The devices are to be properly placed to get appropriate ground p l q e for their reference.

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4. EM1 Reduction by Device Choice :

HCMOS TTL ~

STTL

considerably reduces skew margin allowing slower T,. This solves to the larger extent the EMI problems.

150dB 270dB 135dB 158dB 225dB 113dB 170dB 240dB 120dB

Although most EMI cases seems to occur becaw of installation parameters wch as site, cabling, grounding etc., the real crux deeprob lem whether it is the source or the victim is actually an active device[3]. For active devices, the EMI susceptibility (and emission) is indicated by the Rating of Susceptibility RS where :

ECL-1OK I 164dB BTL I 170dB

RS = Device bandwidth/Device input noise ..... . . . . . _. . . . . . .8

230dE3 115dB 2 5 0 B 125dB

For common logic families RS,.is shown in Table 4.

I CMOS 1130dB I250dB I 125dB I

The families with higher number are most susceptible.

The experiment conducted for conducted and radiated EMI for various logic families are shown in Table - 5[6]

Lowest

I ACT ACT

Highest FCTA FCTA

Table - 5 : E M comparison of various logic families

The major improvement in device EMI reduction is achieved by using devices with slower rise and fall times. Consider figure 7 which shows data and the clock. The data is sampled at the positive edge of the clock. For SDH clock of 20 Mhz p5211S) the T, cqn be lowered if the skew between data and clock is minimized. The skew D consist of chip skew, daughtet cards skew, connector skew and motherboardskew. If the data and clocks are routed to get the same physical length of the trace, then it

I LorricO I

Logic 1 D2

Clock J i t t e r w I

D : Skew, D2 < D1 and Tr2 < T,,

Fig -7 : Use of slower T, with Skew minimization

5. System Level Growding & Earthing :

While there are two standard methods of system grounding Viz. single point grounding and multipoint grounding. The former is suitable cmly at low frequency up to 1Mhz. Above lMhz frequency multipoint grounding has to be used[4,7].

As indicated in Section-3 five types of ground are separated both on card and system. These grounds should not at all be connected to each other on daughter card or motherboard. Ideally all grounds should be separately earthed. This however is not practically feasible Therefore, these grounds should be connected to chassis to get the minimum lead impedance of the connecting lead. The preferred connection is AWG.2 wire @=6.541nm) having 8.53 m12 of impedance per lOcm at 20 Mhz frequency. The minimum wire size to be used in such connection is AWG 10 @=2.59mm) having 10.8 mR impedance per lOcm at 20 Mhz frequency.

The lead length of the connection should be same for all ground connection ana the bonding of these wires with chassis should be tight enough to give maximum of 2mLl impedance. The chassis of system is earthed, at a single earth pit available in the transmission room where this system is housed. This ensures the ground current going to earth rather than interference with each other. This arrangement eliminates common impedance coupling in ground ctments because the return #aths of various grounds are completely separated.

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6. Conclusion :

The EM1 reduction and control techniques described in this paper are proven for SDH kind of product. If these techniques are properly implemented the system passes FCC and VDE standards, and the system design iteration due to EM1 can be avoided. The techniques described here are for systems having predominantly digital design. However, the concepts can be extended for analogue systems also. The algebraic addition of noise component described in Section-2 seems to be giving higher noise value because in many cases noise components adds in root sum square (RSS) manner. Also the formulae used in the paper to work out the values of noise many times gives 30% higher value. Therefore, the analysis can be treated as worst case and the margin of 30% may be accounted for manufacturing and workmanship.

References.

[ 11 High speed digital design by Johnson and Graham. [2] EM1 control methodology and procedures by Michel Mardiguian. Volume-8, Interference Control Technical Inc., Gainesville. Virginia. 131 EM1 in components and devices by Micliel Mardiguain. Volume-5, Interference Control Technical Inc., Gainesville. Virginia. [4] Grounding and Bonding by Michel Mardiguian. Volume-2, Interference Control Technical Inc., Gainesville. Virginia. [ 51 Capacitance, Inductance and crosstalk analysis by Charles S. Walker, Artech House, London, 1990 [6] EMC test and design magazine July/Aug 1994 [7] EMC by David A. Weston [SI MECL System Design Handbook by Willam R. Blood Jr., Motorola Semiconductor Product Inc. [9] Transmission Line Effects in PCB Application, Motorola Semiconductor Application Note AN105 1

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