Static Random-Access Memory - Computer Sciencevito0681/pdf/memory.pdfStatic Random-Access Memory | VITO KLAUDIO 2 1. Objective The ultimate goal of this laboratory is to construct

STATIC RANDOM-ACCESS MEMORY

by VITO KLAUDIO

OCTOBER 10, 2015 CSC343 – FALL 2015 – PROF. IZIDOR GERTNER

Static Random-Access Memory | VITO KLAUDIO

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Table of contents

1. Objective .................................................................................... pg. 2

2. Functionality and Simulations ................................................ pg. 4

2.1 SR-LATCH ................................................................. pg. 5

2.2 Control SR-LATCH .................................................... pg. 7

2.3 D-LATCH ................................................................... pg. 9

2.4 MASTER-SLAVE D FLIP-FLOP .............................. pg. 11

2.5 Static RAM Cell .......................................................... pg. 14

2.6 16 x 4 SRAM .............................................................. pg. 17

3. 16x4 SRAM on the DE2-70 Board .......................................... pg. 22

4. Analysis ...................................................................................... pg. 27

5. Conclusion ................................................................................. pg. 30

6. Appendix.................................................................................... pg. 32


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1. Objective

The ultimate goal of this laboratory is to construct a 16 x 4 Static Random-Access Memory

unit. When we say 16 x 4 we mean that the memory will be composed of 16 memory spots and

each of them will be able to store 4 bits.

We will start our work with latches and flip-flops to get to the final objective. We will

explain how a latch works and what its purpose is. From the latches we will construct the flip-

flops. Explanations about the functionality of the flip-flops will be given. Flip-Flops then will be

used as the building block for the static random access memory unit. Latches are the most basic

storage units and they can store one bit.

We start with the SR latches, and explain what they do and why they are useful. In the next

step we introduce the Control SR latch, which is very similar to the regular SR but with one

condition that it has an extra input that can turn the latch off. Continuing our study of latches we

introduce the D flip flop, which solves a problem of having two inputs set at logical “1”

encountered in the SR latch. The D latch has only one input, and the control input is the same as

the one used previously. Latches will change their state as soon as the inputs change, but we

need to change the output after the inputs are changed. Hence, the next element that we consider

is the Master Slave D Flip-Flop. This unit is composed by connecting two D latches in series

with each other and controlling them with the same control input. We use this flip flop to

construct an SRAM cell.

Remember that all latches are used as storing units, they can store only 1 bit. We combine

them in order to create more storage capacity. To get an SRAM we combine two Master Slave D

Flip-Flop and use more inputs to have more control over our circuit. The Select Chip and Write

Enable inputs, together will act as a Control function to the circuit. The 16x1 SRAM cell will


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have 16 storage units since it will be composed of 16 SRAMs. The input will be fed into the

master flip flop and its output will serve as the input of the slave flip-flop. Another important

element used in this implementation is the TRI buffer, which will make decisions of whether to

output anything from the circuit or not. Afterwards we combine four 16x1 SRAMs to create our

final goal. Quartus’s feature of creating symbols will be very helpful in this case since it would

be tiresome to put 64 different SRAM cells on the screen at once and interconnect them

appropriately.

The next stage of our work is to set up the memory cells for the 16 x 4 SRAM based on the

cells. Our SRAM will be able to store multiple bits in various locations based on the inputs that

we will provide. The inputs will consists of the data input, the address input, which will be four

bits each. The Write Enable, Output Enable, and Chip Select inputs consist of one bit each. The

output will also be four bits, since we are storing four bits in each address. Since we have 16

storage elements, and the address is four bits we will be using a 4-to-16 decoder to decide the

storage element out of the SRAM cells.

After we complete the diagrams for the above mentioned circuits we will use the simulation

tools from Quartus to check our results. In particular we will be using the Vector Waveform

Simulator, which is a very powerful tool. It allows us to choose the waveform of the inputs

however we need to in order to achieve our goal.

The last thing to do is to display the values stored in memory on the 7 segment display. We

will use a decoder to convert our four bit binary number to hexadecimal format in order for the

display to output the data stored at a specific address. The result will be shown in hexadecimal

notation in one of the displays of the DE2-70 board.


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2. Functionality and Simulations

Latches are the most basic storage elements. A storage element is designed so that it can

maintain its state until a signal tells it do to otherwise. Latches are sequential devices, this means

that they watch their input continually and they can change their state at any time. Usually a

clock signal set to high is used as an enable signal. Sequential elements are designed in such a

way that they take into consideration not only the current input but the past inputs as well. This is

where the memory concept comes from: these elements remember what their inputs were at

arbitrarily past times.

A flip-flop is another storage element. These elements are simple circuits which store logic

states until the state is used at a later time. Flip-flops are sequential elements too, but these

elements sample their input and change their output only when the clock signal is changing.

There are two cases when the output can be changed. The first case is when the clock signal just

sets to high, and this is called a rising edge change. Otherwise, the output will change when the

clock signal goes to low, and this is called a trailing edge change. These elements are called edge

triggered, and they become active at either positive or negative edge. This means that they will

take input exactly at the time that the clock changes from high to low or from low to high.


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2.1. SR-LATCH

The name of this latch comes from its inputs. SR stands form Set / Reset latch. This latch is

composed of two NOR gates as represented in the schematics below:

As we can see the latch takes two inputs and generates two outputs, which are complements

of each other. We get different outputs when the functions Set and Reset change. For example,

when the Set function is high (logical “1”) and the Reset function is low (logical “0”) the output

Q of this latch will always be high (logical “1”) and the latch is said to be in a SET state. The

output Q will always be low (logical “0”) when the Reset function is set to high, and the Set

function is set to low. This state is called a RESET state. When both inputs are set to high the

output is undefined for this latch. Furthermore the latch will maintain its previous state if both

input functions are set to low. The following truth table summarizes the behavior of this latch:


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We implement this latch using the Quartus II block diagram editor and the default logic gates

provided to us. Then we simulate the latch in order to check if our implementation was correct.

A screenshot of the waveform of the simulation is shown below:

Note that the inputs are randomly selected in this simulation because we want to try as many

possible cases as we can.

We can see from the screenshot that whenever both inputs R and S go to high (logical “1”)

the output is set to low, and it retains its state until the next clock signal. From the results of this

simulation we can conclude that the implementation was correctly done.


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2.2. Control SR-LATCH

This latch is a modification of the original SR-latch. In this latch we use an extra control

function which is used to control state change. We use four NAND gates instead of the two gates

used in the previous latch. The schematic of the latch is shown in the following picture:

In this case, when the control function C is set to low (logical “0”) the latch will retain its

state and will not be subject to any change. This latch will work exactly like the SR-Latch if the

control function is set to high, i.e. it will be completely dependent on the Set and Reset functions.

The behavior of this latch is demonstrated by the truth table and equations below:

Qn in the above equations is the name for the Next State of the Q output. We do the same

thing for this latch, we implement it and simulate it via the Quartus II software. The following

screenshot displays the result of the simulation:


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Note that the Control input was purposely selected to be zero for a certain period of time and

then it is set to one. This was done in order to show that the latch is disabled when the control

function is set to low and this is confirmed by the output Q and Qnot which are undefined at that

instance. The R and S inputs are again chosen at random.

We can see that the simulation is working, because when the control input is set to high, the

latch will be working exactly like a SR-Latch. We can conclude that the implementation was

correctly done.


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2.3. D-LATCH

As we mentioned before, the SR-Latch has a problem. The output is undefined when both

inputs are set to high. We solve this problem by introducing the D-Latch which takes only one

input function and makes sure that the SR-Latch problem is resolved. The input D of this latch

will substitute both S and R of the previous latch. This latch is constructed using four NAND

gates and one NOT gate that will be used to get the complement of the input D. The schematic is

shown in the following diagram:

Remember that these latches all store one binary bit. It is obvious that we still need the

control signal for this latch and it has the same exact function as the SR-Latch. The D input is

sent to the top NAND gate as it comes in, and the complement of this input is send to the bottom

NAND gate. In this way we make sure that the inputs of the NAND gates can never be both

high. The behavior of this latch is represented by the following truth table and equations:


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From this particular latch we can construct flip flops, like the master slave D flip flop which

is introduced in the next section. We implement the D-Latch on Quartus again, and simulate it

through the Vector Waveform Simulator to get the following result:

Note that the Control input, like in the Control SR-Latch simulation, was purposely chosen in

that way. Our expectations are met since the undefined outputs mean that the latch is disabled.

The results of the simulation after the control input is set to high confirm the theory and the

truth table, hence the implementation is correct.


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2.4. MASTER SLAVE D FLIP – FLOP

We can design a master slave D flip-flop by connecting two D-Latches one after the other.

The first latch will act as the master, and the following latch is the slave and that is where the

name of this flip-flop comes from. Both latches use the same clock signal, but the first latch

inverts the clock signal. Furthermore, the output of the first latch acts as the input of the second

latch. The diagram below represents the schematics of this flip-flop:

The latch that is inside the green square is the first and master latch and the latch inside the

blue square is the slave latch. All the latches that we have seen are pulse-triggered, but this flip-

flop is in fact a negative edge-triggered circuit. This means that the output Q will be the same as

the input D at a falling-edge clock signal, hence the output can only change when the clock goes

from high to low (from logical “1” to logical “0”). This flip-flop is different from the latches in

another aspect. The state change of the flip-flop does not depend on the state of the clock-signal,

it is dependent only from the transition of the clock signal. The following truth table shows how

this flip-flop functions:


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In the table above, the left column is represents the clock signal. Dm represents the input and

Cm is the clock for the master D-Latch. Ds and Cs represent the input and clock of the slave D-

latch.

The previous input state is used to generate the global output when the clock transitions from

low to high. This behavior comes from the fact that at state “0” the slave latch does not change

while the master latch generates a new input for the slave latch. When the clock transitions again

from high to low, the roles are changed. In this case the master latch will not exhibit any change

while the slave state will produce based on the previous input.

Again, we implement this flip-flop on the Quartus II block diagram and run a simulation. The

results are depicted in the following screenshot:


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This simulation shows that the control function acts as a switch to the cell, if this input is

set to low, the cell cannot determine the output, therefore the X’s in the screenshot show it.

It is very important to notice, that because of the design of the Master Slave D Flip-Flop

we get output be the same as the input. We continue our study of flip-flops by introducing the

Static Random-Access Memory Cell concept in the next section.


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2.5. Static RAM Cell

A Static RAM Cell is created from the Master Slave D Flip-Flop that we discussed above.

This cell takes three inputs and generates one output. The IN input is the latch’s data input, while

SELECT_CHIP is used as an activation input. When this input is set to high, the cell will be

active and it will have the possibility to store data. On the other hand when SELECT_CHIP is set

to low the cell is turned off and it does not store data. The WRITE_ENABLE input tell the cell to

store the data that it received from the IN input. The schematics for a cell was generated using

the Quartus II software which provides all the gates.

Notice that the block diagram with the D symbol represents a D-Latch. The last element

before the output signal is generated is called a Tristate Logic Buffer and it is labeled as TRI in

the diagram.


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This buffer will produce its C output only when the B input is logical “1”. When the B input

is set to low, then the buffer is completely cut off and no output signal is generated. This buffer

is provided to us by the Quartus II collection of logic buffers and its behavior is described by the

following truth table:

This is all the information we need to know in order to produce a 16 x 4 SRAM.

Now, as always, we have to check that our implementation of this circuit is doing its job. We

perform the vector waveform simulation and get the results shown in the screenshot below:

Note that the Select Chip input was again set up in such a way as to display what happens

with the output when the input is set to low and it is shown in the simulation as a “Z”, this means


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the cell is asleep, no action can be performed since we “unplugged” the power from this cell. The

undefined symbols shown after the sleeping symbol are shown because at that instance the write

enable is set to low, which means that we cannot store anything at this time in the cell.

The result of this simulation clearly show that the implementation is correct and we can

continue to use these latches and flip-flops as building blocks towards our ultimate goal of

creating a 16x4 SRAM.


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2.6. 16 x 4 SRAM

We will use the cells that we described in the above section to implement our SRAM with 16

storage spots and 4 bits of wide.

We use 16 D Flip-Flops to produce a 16 x 1 SRAM cell and then combine four of these to

reach our final objective to create a 16 x 4 SRAM. We will take advantage of the Quartus II

symbol creation option to do this.

Our cell will get three inputs and produce an output. Input and WR will be 1-bit signal that

serve for all of the 16 flip flops the same, while the Select_Chip input will be provided by an

input vector of 8-bits.

The schematic of a 16 x 1 SRAM is displayed below:

As we can see we used 16 Master-Slave D Flip-Flops to achieve our goal. The next step is to

create another symbol from this scheme and call it SRAM16 in order to be able to use it for the

final SRAM which is a combination of four SRAM16s which will make our 16x4 SRAM


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complete. Remember that 16x4 means that there are 16 storage units and each of them can store

four bits. The final schematic is shown below:

We can see that the TRI buffers are very important to our design. Without the TRI we would

need to use a multiplexer to separate the outputs of each column. The TRI buffer cuts the output

of the other cells, and the only output will be the one coming from the cell that is on at the

moment. As you may have noticed we use a decoder to determine which storage unit is to be

used to store the input data. The output of the decoder is used to determine a row. The concept of

the decoder is shown in the following picture:

We use a 4 to 16 decoder since we need to determine which of the 16 rows will be chosen to

store the input. The VHDL code for the decoder that we use is shown in the appendix section of

this laboratory.


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There are several inputs to the 16 x 4 SRAM. We have the “datain” input vector of four bits

(from 3 to 0) that is the input which will be written to the SRAM at a certain address. The

“address” input is also a vector of four bits. This is the input to the decoder. The WE input is the

write/enable input, it tells the SRAM to store only when it is high, otherwise when the WE input

is set to low no writing to the SRAM will be allowed. OE represents the output/enable function,

it will allow the SRAM to output the value stored at a particular cell only if it set to high.

Otherwise, the TRI buffer will cut the output signal. CS is the chip select function. This acts as a

switch for the SRAM, i.e. when CS is set to low it will turn off the SRAM, and it will turn it on

when set to high.

The last task that we need to compute is to display the results on the 7-segment display of the

DE2-70 board. This can be done by converting our decimal values to hexadecimal digits that the

display can interpret. We will use the CASE statement of the VHDL code which has the same

function as the SWITCH statement in high level programming languages. The code for the 7-

segment display output is shown in the appendix section.

We will use pin assignment to tell the board all it needs to know about the inputs. The first

four switches, from 0 to 3 are used as the “datain” input. The “address” needed as input for the

decoder is assigned the next four switches, from 4 to 7. CS will be switch 17, OE will be switch

16 and WE will be represented by switch 15. The output will be displayed on the seven segment.

Before explaining how the seven segment display is activated, we will simulate the 16x4

SRAM diagram with the vector waveform simulator in order to check our results. The screenshot

below shows the results:


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Note that the inputs are selected at random for this simulation.

We can see from the screenshot that whenever CS, the chip control function, is set to low the

whole block is turned off. There can be no possible operations on this block and therefore we can

see the symbol “Z” in the waveform, meaning that the block is sleeping at that point. The block

will not wake up exactly when the CS input is switched to high, it will wait for the next cycle

since our flip flops are trailing edge-triggered.

Another point of interest is the behavior of the block when the WE, write/enable input, is set

to low. We can see that the output will be undefined, symbolized by “X” in the waveform, for

this case. This was expected since no writing operation in memory is allowed when WE is set to

low.

Our expectations were met, and we can say that the implementation of a 16x4 SRAM is

completed. The next step of this lab is to implement our design in the DE2-70 board and display

the output on the seven segment display. To do this, we will need to use the “dec_to_hex” code


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which was provided to us by the lab manual. This code translates the decimal value of the output

to a hexadecimal representation and it uses the segments of the display to show that hexadecimal.

The code is shown in the appendix section.

Furthermore, we need to write the pin assignment for this SRAM. I chose the input data to be

represented by the first four switches, meaning SW[0]…SW[3], and the input address will be

controlled by switches SW[4]…SW[7]. I used Switch number 15 to control the Write/Enable

input, switch number 16 to control the Chip Selection input, and switch number 17 to control

Output/Enable input. The display that I chose to show the hexadecimal values of the data stored

in the register is the first display of the board, i.e. HEX0. The full pin assignment file is shown in

the Appendix section of this laboratory.


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3. 16x4 SRAM on the DE2-70 Board In this section of the laboratory we show the actual implementation on the board of the 16x4

SRAM. The following pictures will show the results of experiment. Each picture will be

followed by the explanation it requires. Here we go:

The picture above is annotated for the purpose of making the inputs and output more visible.

The red arrows point to the OE, CS, and WE inputs on the board. The green square represents

the four bits of the input data. The blue square is set around the four bits of the address

representing the register. The orange circle shows where the display of the hexadecimal value of

the register will be shown.

In this picture we can see that the display is 0x0. This means that at memory address “0000”

we have the zero value stored, which is the default value. The data input at this instance is

“0000” also, but this does not matter right now because the write enable function is set to zero

and no writing to the register is allowed. Since the OE and CS are both set to high, the register is

allowed to display the number.


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This picture is a continuation of the previous one. We can see that the address location has

not changed, it still is set to “0000”, but the input data is changed. Now the input is set to be

“0111” which represents the number seven in hexadecimal. This number is shown on the display

because we have enabled the WE input, which lets the data be stored in the register at the

specified address, and we have enabled the OE input, which lets the result be displayed from the

register, and we have enabled the whole circuit by setting CS to high.


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In this picture we show what happens when we do not change the address of the register, but we

disable the WE input, and we change the input data. We can see that while the OE and CS inputs

are set to high we can still see the number 7 on the display even though the input data is set to the

value of “0000”. This happens because we set the WE input to low and no writing can be done

on this address at this time. We can only display the value stored, but cannot store a new value.

In this picture we are displaying the content of the register at address “0001”. The input data

in this case does not matter even because we have set the WE input to low, which means we

cannot write any value to this register. We just want to see what is in there, and therefore we

enable the whole memory by setting CS to high, and we allow it to display the value by setting

the OE input to high as well. Even though the input data is set to “1010”, we still get a 0x0 on the

display since we are just looking at this register and not writing to it.


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In this picture we change the state of the WE function from low to high. This action will

enable the memory to write data on the storage unit located at address “0001” and specifically it

will write the value of “1010” in hexadecimal representation which is 0xA, and that is what we

are seeing on the screen.

In this picture we disable the OE function and we can see that the output display shows oxF,

and that is the default notation for undefined, or not accessible. This means that we cannot access


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the data stored at the register corresponding to that address and therefore it is not accessible to

us.

In this picture we set the CS input to low, this means that the memory is shut down and no

operation can be done on it. This is why we see a 0xF display in the board. Anything we try to do

on with the other inputs will not change this value since the memory is off.

These pictures show that our implementation was correct and all the circuits are working

perfectly. We can say that we finally have reached our goal of setting up and running a 16x4

SRAM.


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4. Analysis

The difference between a latch and a flip-flop consist in their output. The output of the latch

can change as soon as its inputs change, while a flip-flop on the other hand is edge triggered.

This means that it needs a signal to go from high to low, or from low to high to change the

output.

An SR Latch takes two input, the Set and Reset functions. It is composed of two NOR gates.

The state of the Latch will be Set, when the Set function is set to high and the Reset function is

set to low. It will have a Reset state when the Reset is high and the Set is low. When both inputs

are set to low, then the Latch will maintain its previous state. The problem with the SR Latch

appears when both inputs are set to high: in this case the output is undefined.

The Control SR-Latch is a modified version of the SR-Latch explained above. This latch

takes three inputs, rather than two. The Control function is used to turn on and off the latch.

When the control is set to low, there will be no change in the output independent of the Set and

Reset inputs, the latch will be turned off. Otherwise, when the control input is set to high the

latch will function exactly like a SR-Latch. This is achieved by combining four NAND gates.

The D-Latch solves the problem of having two inputs set to high at the same time. This latch

takes only one input, and it complements its bit to use it for the bottom NAND gate. In this way

we are guaranteed to never have the same input for both gates at the same time.

To build a Master Slave D Flip-Flop we combine two D-Latches. We connect them in series.

The control input is used to control both latches at the same time. The input goes through the

first latch, the master, while the second latch’s input comes from the output of the first latch. In


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this way the second latch becomes the slave. The output of the slave latch is considered the

output of the global system.

The SRAM cell uses two Master Slave D Flip-Flops and takes more inputs and uses the TRI

buffer to decide on the output. The inputs are used to have more control over the flip-flops. The

select chip and write enable inputs are used to control the flip-flops. Connected by a NAND gate,

these two inputs go to the control input of both flip-flop in order to decide whether the circuit

should be turned off, or if we can be able to write data on the system. Remember, all these

circuits are used as storage elements.

We want to avoid having both inputs high in a SR-Latch because we do not want our output

to be undefined. We need to have some output when we are building on this basic block. When

we get to the high level, we don’t want our circuit to tell us that it is not able to define the output

of a pair of inputs. This scenario can never happen with a D-Latch because we use only one input

and complement its bit to be used as the second input, hence it is impossible to have the same

inputs at the same time.

The difference between the edge-triggered and level-triggered circuits is based on when the

output changes. For a level-triggered circuit the output will change when the clock signal is set to

a certain level, it can be changed while the signal is set to high, or when it is set to low. On the

other hand, an edge-triggered circuit will change its output if and only if the clock signal changes

from one state to the other. The output might change at the exact moment when the signal goes

from low to high, or it can change at the moment when the signal goes from high to low. The

flip-flop that we are using in this lab are edge-triggered, and specifically they are trailing edge-

triggered. This means that the output of our circuits will change at the exact moment when the

signal goes from high to low.


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An SRAM takes some inputs and produces an output. The inputs of the SRAM are the data to

be stored, the address of where the data will be stored, the write enable signal to tell the circuit

that we want to write in it, the output enable signal that lets the circuit know that we want to

display the contents of a certain address, and finally the chip select input which acts as a power

switch to the circuit. When the chip select signal is set to low, then the circuit will be shut off and

no activity can be performed on it. Otherwise, when the signal is set to high we can perform our

desired operations. If we want to store some data on the circuit we need to tell it the place, i.e.

the address of where the data will be store. We need to tell it what the input is by selecting the

input data, and most importantly we need to change the write enable signal from low to high in

order to store the data, since the circuit is edge-triggered. The output of the SRAM will be

content of a certain address, which we decide as an input to the system. The output will be

displayed if and only if the output enable signal is set to high, otherwise nothing will be

displayed. This is a very convenient circuit, since we can use this to implement registers on any

electronic device.


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5. Conclusion

In this laboratory we started small and grew up based on our building blocks to achieve our

final goal, that of constructing a 16x4 Static Random-Access Memory.

We began by introducing the SR-Latch which worked based on two input functions, the Set

and Reset. That is where this latch gets its name. This latch is the most basic storage unit, which

can store only one bit. We wanted to have some control over this latch, i.e. to shut it off when we

wanted to. Hence, we introduced the Control SR-Latch. This latch had an extra input, the C

(control) input which would turn the latch off when set to low. Otherwise, when C was high this

latch worked exactly like a SR-Latch.

We encountered a problem with the SR latches, their output was undefined when both Set

and Reset functions where set to high. This problem was solved by introducing the D-Latch. This

latch takes only one input, therefore no such problem could occur. We extended our knowledge

of latches by connecting two D-latches in series with each other and thus forming the D Flip-

Flop. This flip flop is called the Master-Slave Flip Flop because the first latch’s output is used as

the second latch’s input, therefore the second latch became the slave of the first latch which was

the master.

Based on this flip flop, we introduced the SRAM cell, which is basically the same as a

Master Slave D Flip Flop, but it took more inputs to make more decisions. We combined 16 of

these cells together to form a 16x1 SRAM. At this point, we almost finished our job. The only

thing remaining was to combine four SRAMs together and finally form our 16x4 SRAM.

All the elements used in this lab were implemented and simulated using the Quartus II

software, which gave us certainty that our devices work. The final implementation, the 16x4


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SRAM was also implemented on the DE2-70 board. The results achieved from testing this circuit

on the board show that our expectations were met and we completed our study of 16x4 SRAM.

Pictures of the simulations and the board were included in this lab to make it as clear as possible

how the SRAM worked. Furthermore, we had an analysis section, where we answered questions

about this laboratory. In this way, we show that we understand how the circuit works, and how to

use it when needed.

Overall, this was a very interesting laboratory. It gave us first hand, real world problems. We

use SRAM every day on our computers and any electronic device, but little did we know of its

internal components and how they work. By completing this lab, we have a much wider

knowledge of this, very important device. It is much clearer now on how the registers actually

work. All the time, we were told that the registers can store bits, but how they did it was never

taught to us. Now we have the insight of the register and we can continue our study of computer

organization since we have mastered its building block: the memory.


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6. Appendix

VHDL CODE FOR 4to16 DECODER:

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity decode4to16 is

port(

oct : in std_logic_vector(3 downto 0);

dec : out std_logic_vector(15 downto 0));

end decode4to16;

architecture arch of decode4to16 is

begin

with oct select

dec <= "0000000000000001" when "0000",

"0000000000000010" when "0001",

"0000000000000100" when "0010",

"0000000000001000" when "0011",

"0000000000010000" when "0100",

"0000000000100000" when "0101",

"0000000001000000" when "0110",

"0000000010000000" when "0111",

"0000000100000000" when "1000",

"0000001000000000" when "1001",

"0000010000000000" when "1010",

"0000100000000000" when "1011",

"0001000000000000" when "1100",

"0010000000000000" when "1101",

"0100000000000000" when "1110",

"1000000000000000" when "1111",

"0000000000000000" when others;

end arch;

VHDL CODE FOR HEX DISPLAY:

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Hexadecimal to 7 Segment Decoder for LED Display

ENTITY dec_to_hex IS

PORT( hex_digit : IN STD_LOGIC_VECTOR(3 DOWNTO 0);

segment_a, segment_b, segment_c, segment_d, segment_e, segment_f,

segment_g: OUT std_logic);

END dec_to_hex;

ARCHITECTURE a OF dec_to_hex IS

SIGNAL segment_data : STD_LOGIC_VECTOR(6 DOWNTO 0);

BEGIN

PROCESS (Hex_digit)

-- HEX to 7 segment Decoder for LED Display

BEGIN -- Hex-digit is the four bit binary value to display


33

CASE Hex_digit IS

WHEN "0000" =>

segment_data <= "1111110";

WHEN "0001" =>


WHEN "0010" =>


WHEN "0011" =>


WHEN "0100" =>


WHEN "0101" =>


WHEN "0110" =>


WHEN "0111" =>


WHEN "1000" =>


WHEN "1001" =>


WHEN "1010" =>


WHEN "1011" =>


WHEN "1100" =>


WHEN "1101" =>


WHEN "1110" =>


WHEN "1111" =>


END CASE;

END PROCESS;

-- extract segment data bits and invert

-- LED driver circuit is inverted

segment_a <= NOT segment_data(6);

segment_b <= NOT segment_data(5);

segment_c <= NOT segment_data(4);

segment_d <= NOT segment_data(3);

segment_e <= NOT segment_data(2);

segment_f <= NOT segment_data(1);

segment_g <= NOT segment_data(0);

END a;

PIN ASSIGNMENT:

To, Location

datain[0], PIN_N25

datain[1], PIN_N26

datain[2], PIN_P25

datain[3], PIN_AE14

address[0], PIN_AF14

address[1], PIN_AD13


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address[2], PIN_AC13

address[3], PIN_C13

WE, PIN_U4

CS, PIN_V1

OE, PIN_V2

segment_a, PIN_AF10

segment_b, PIN_AB12

segment_c, PIN_AC12

segment_d, PIN_AD11

segment_e, PIN_AE11

segment_f, PIN_V14

segment_g, PIN_V13

Documents

Static Random-Access Memory - Computer Sciencevito0681/pdf/memory.pdfStatic Random-Access Memory | VITO KLAUDIO 2 1. Objective The ultimate goal of this laboratory is to construct