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Altera Corporation 3–1January 2008

3. External MemoryInterfaces in Stratix II and

Stratix II GX Devices

Introduction Stratix ® II and Stratix II GX devices support a broad range of externalmemory interfaces such as double data rate (DDR) SDRAM, DDR2SDRAM, RLDRAM II, QDRII SRAM, and single data rate (SDR) SDRAM.Its dedicated phase-shift circuitry allows the Stratix II or Stratix II GXdevice to interface with an external memory at twice the system clockspeed (up to 300 MHz/600 megabits per second (Mbps) withRLDRAM II). In addition to external memory interfaces, you can also usethe dedicated phase-shift circuitry for other applications that require ashifted input signal.

Typical I/O architectures transmit a single data word on each positiveclock edge and are limited to the associated clock speed. To achieve a400-Mbps transfer rate, a SDR system requires a 400-MHz clock. Manynew applications have introduced a DDR I/O architecture as analternative to SDR architectures. While SDR architectures capture data onone edge of a clock, the DDR architectures captures data on both therising and falling edges of the clock, doubling the throughput for a givenclock frequency and accelerating performance. For example, a 200-MHzclock can capture a 400-Mbps data stream, enhancing systemperformance and simplifying board design.

Most new memory architectures use a DDR I/O interface. AlthoughStratix II and Stratix II GX devices also support the mature and wellestablished SDR external memory, this chapter focuses on DDR memorystandards. These DDR memory standards cover a broad range ofapplications for embedded processor systems, image processing, storage,communications, and networking.

Stratix II devices offer external memory support in every I/O bank. Theside I/O banks support the PLL-based interfaces running at up to200 MHz, while the top and bottom I/O banks support PLL- andDLL-based interfaces. Figure 3–1 shows Stratix II device memorysupport.

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3–2 Altera CorporationStratix II Device Handbook, Volume 2 January 2008

Introduction

Figure 3–1. External Memory Support

Bank 3 Bank 4Bank 11 Bank 9

PLL11 PLL5

PLL7

PLL1

PLL2

PLL4

PLL3

PLL10

Support PLL- andDLL-Based Implementations

Support PLL-BasedImplementation

Support PLL-BasedImplementation

Support PLL- andDLL-Based Implementations

V RE F0 B3 V RE F1B 3 V RE F2 B3 V RE F3B 3 V RE F4 B3 V REF0 B4 V RE F1 B4 V REF2 B4 VRE F3 B4 V RE F4 B4

Bank 8 Bank 7Bank 12 Bank 10

PLL12 PLL6

PLL8 PLL9V RE F4 B8 V RE F3B 8 V RE F2 B8 V RE F1B 8 V RE F0 B8 V REF4 B7 V RE F3 B7 V REF2 B7 VRE F1 B7 V RE F0 B7

V R E F 3 B 2

V R E F 2 B 2

V R E F 1 B 2

V R E F 0 B 2

B a n k 2

V R E F 3 B 1

V R E F 2 B 1

V R E F 1 B 1

V R E F 0 B 1

B a n k 1

V R E F 1 B 5

V R E F 2 B 5

V R E F 3 B 5

V R E F 4 B 5

B a n k 5

V R E F 1 B 6

V R E F 2 B 6

V R E F 3 B 6

V R E F 4 B 6

B a n k 6

V R E F 4 B 2

V R E F 0 B 5

V R E F 4 B 1

V R E F 0 B 6

DQS4T DQS3T DQS2T DQS1T DQS0T

DQS 4B DQ S3 B DQS 2B DQ S1 B DQ S0 BDQS8B DQS7B DQS6B DQS5B

DQS8T DQS7T DQS6T DQS5T

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Altera Corporation 3–3January 2008 Stratix II Device Handbook, Volume 2

External Memory Interfaces in Stratix II and Stratix II GX Devices

Table 3–1 summarizes the maximum clock rate Stratix II and Stratix II GXdevices can support with external memory devices.

This chapter describes the hardware features in Stratix II and Stratix II GXdevices that facilitate the high-speed memory interfacing for each DDRmemory standard. This chapter focuses primarily on the DLL-basedimplementation. The PLL-based implementation is described inapplication notes. It then lists the Stratix II and Stratix II GX featureenhancements from Stratix devices and briefly explains how eachmemory standard uses the Stratix II and Stratix II GX features.

f You can use this document with the following documents:

■ AN 325: Interfacing RLDRAM II with Stratix II & Stratix GX Devices■ AN 326: Interfacing QDRII & QDRII+ SRAM with Stratix II, Stratix,

& Stratix GX Devices■ AN 327: Interfacing DDR SDRAM with Stratix II Devices■ AN 328: Interfacing DDR2 SDRAM with Stratix II Devices

Table 3–1. Stratix II and Stratix II GX Maximum Clock Rate Support for External Memory Interfaces

Notes (1) , (2)

Memory Standards–3 Speed Grade (MHz) –4 Speed Grade (MHz) –5 Speed Grade (MHz)

DLL-Based PLL-Based DLL-Based PLL-Based DLL-Based PLL-Based

DDR2 SDRAM (3) , (5) 333 200 267 167 233 167

DDR SDRAM (3) 200 150 200 133 200 100

RLDRAM II 300 200 250 (4) 175 200 175

QDRII SRAM 300 200 250 167 250 167

QDRII+ SRAM 300 (6) 250 (6) 250 (6)

Notes to Table 3–1 :(1) Memory interface timing specifications are dependent on the memory, board, physical interface, and core logic.Refer to each memory interface application note for more details on how each specification was generated.

(2) The respective Altera MegaCore function and the EP2S60F1020C3 timing information featured in the Quartus ® IIsoftware version 6.0 was used to define these clock rates.

(3) This applies for interfaces with both modules and components.(4) You must underclock a 300-MHz RLDRAM II device to achieve this clock rate.(5) To achieve speeds greater than 267 MHz (533 Mbps) up to 333 MHz (667 Mbps), you must use the Altera DDR2

SDRAM Controller MegaCore function that features a new dynamic auto-calibration circuit in the data path forresynchronization. For more information, see the Altera web site at www.altera.com . For interfaces running at267 MHz or below, continue to use the static resynchronization data path currently supported by the releasedversion of the MegaCore function.

(6) The lowest frequency at which a QDRII+ SRAM device can operate is 238 MHz. Therefore, the PLL-basedimplementation does not support the QDRII+ SRAM interface.

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External Memory Standards

ExternalMemoryStandards

The following sections briefly describe the external memory standardssupported by Stratix II and Stratix II GX devices. Altera offers a completesolution for these memories, including clear-text data path, memorycontroller, and timing analysis.

DDR and DDR2 SDRAMDDR SDRAM is a memory architecture that transmits and receives dataat twice the clock speed. These devices transfer data on both the risingand falling edge of the clock signal. DDR2 SDRAM is a second generationmemory based on the DDR SDRAM architecture and transfers data toStratix II and Stratix II GX devices at up to 333 MHz/667 Mbps. Stratix IIand Stratix II GX devices can support DDR SDRAM at up to200 MHz/400 Mbps. For PLL-based implementations, Stratix II andStratix II GX devices support DDR and DDR2 SDRAM up to 150 MHzand 200 MHz, respectively.

Interface Pins

DDR and DDR2 SDRAM devices use interface pins such as data (DQ),data strobe (DQS), clock, command, and address pins. Data is sent andcaptured at twice the system clock rate by transferring data on the clock’spositive and negative edge. The commands and addresses still only useone active (positive) edge of a clock. DDR and DDR2 SDRAM usesingle-ended data strobes (DQS). DDR2 SDRAM can also use optionaldifferential data strobes (DQS and DQS#). However, Stratix II andStratix II GX devices do not use the optional differential data strobes forDDR2 SDRAM interfaces since DQS and DQSn pins in Stratix II andStratix II GX devices are not differential. You can leave the DDR SDRAMmemory DQS# pin unconnected. Only the shifted DQS signal from theDQS logic block is used to capture data.

DDR and DDR2 SDRAM ×16 devices use two DQS pins, and each DQSpin is associated with eight DQ pins. However, this is not the same as the×16/×18 mode in Stratix II and Stratix II GX devices (see “Data and DataStrobe Pins” on page 3–14 ). To support a ×16 DDR SDRAM device, youneed to configure Stratix II and Stratix II GX devices to use two sets of DQpins in ×8/×9 mode. Similarly if your ×32 memory device uses four DQSpins where each DQS pin is associated with eight DQ pins, you need to

configure Stratix II and Stratix II GX devices to use four sets of DQS/DQgroups in ×8/×9 mode.

Connect the memory device’s DQ and DQS pins to Stratix II andStratix II GX DQ and DQS pins, respectively, as listed in Stratix II andStratix II GX pin tables. DDR and DDR2 SDRAM also uses active-highdata mask, DM, pins for writes. You can connect the memory’s DM pins

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to any of Stratix II and Stratix II GX I/O pins in the same bank as the DQpins of the FPGA. There is one DM pin per DQS/DQ group in a DDR orDDR2 SDRAM device.

You can also use I/O pins in banks 1, 2, 5, or 6 to interface with DDR and

DDR2 SDRAM devices. These banks do not have dedicated circuitry,though, and can only support DDR SDRAM at speeds up to 150 MHz andDDR2 SDRAM at speeds up to 200 MHz. DDR2 SDRAM interfaces usingthese banks are supported using the SSTL-18 Class I I/O standard.

f For more information, see AN 327: Interfacing DDR SDRAM withStratix II Devices and AN 328: Interfacing DDR2 SDRAM with Stratix IIDevices .

If the DDR or DDR2 SDRAM device supports error correction coding(ECC), the design will use an extra DQS/DQ group for the ECC pins.

You can use any of the user I/O pins for commands and addresses to theDDR and DDR2 SDRAM. You may need to generate these signals fromthe system clock’s negative edge.

The clocks to the SDRAM device are called CK and CK# pins. Use any ofthe user I/O pins via the DDR registers to generate the CK and CK#signals to meet the DDR SDRAM or DDR2 SDRAM device’s t DQSS requirement. The memory device’s t DQSS specification requires that thewrite DQS signal’s positive edge must be within 25% of the positive edgeof the DDR SDRAM or DDR2 SDRAM clock input. Using regular I/Opins for CK and CK# also ensures that any PVT variations on the DQSsignals are tracked the same way by these CK and CK# pins. Figure 3–2 shows a diagram that illustrates how to generate these clocks.









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Figure 3–2. Clock Generation for External Memory Interfaces in Stratix II and Stratix II GX Devices

Notes to Figure 3–2:(1) CK and CK# are the clocks to the memory devices.(2) DK and DK# are for RLDRAM II interfaces. You can generate DK# and DK from separate pins if the difference of

the Quartus II software’s reported clock-to-out time for these pins meets the RLDRAM II device’s t CKDK specification.

Read and Write Operations

When reading from the memory, DDR and DDR2 SDRAM devices sendthe data edge-aligned with respect to the data strobe. To properly read thedata in, the data strobe needs to be center-aligned with respect to the datainside the FPGA. Stratix II and Stratix II GX devices feature dedicatedcircuitry to shift this data strobe to the middle of the data window.Figure 3–3 shows an example of how the memory sends out the data anddata strobe for a burst-of-two operation.

QD

QD

LE IOEVCC

VCC

CK# (1)

DK# (2)

CK (1)

DK (2)

QD

QD

clk

VCC

VCC

GND

GND

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Figure 3–3. Example of a 90° Shift on the DQS Signal Notes (1) , (2)

Notes to Figure 3–3:(1) RLDRAM II and QDRII SRAM memory interfaces do not have preamble and postamble specifications.(2) DDR2 SDRAM does not support a burst length of two.(3) The phase shift required for your system should be based on your timing analysis and may not be 90°.

During write operations to a DDR or DDR2 SDRAM device, the FPGA

needs to send the data to the memory center-aligned with respect to thedata strobe. Stratix II and Stratix II GX devices use a PLL to center-alignthe data by generating a 0° phase-shifted system clock for the write datastrobes and a –90° phase-shifted write clock for the write data pins forDDR and DDR2 SDRAM. Figure 3–4 shows an example of therelationship between the data and data strobe during a burst-of-fourwrite.

DQS atFPGA pin

DQ atFPGA pin

DQS atIOE registers

DQ at

IOE registers

90˚ degree

DQ pin to register delay

DQS pin to register delay

Preamble Postamble

(3)

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Figure 3–4. DQ and DQS Relationship During a DDR and DDR2 SDRAM Write Notes (1) , (2)

Notes to Figure 3–4:(1) This example shows a write for a burst length of four. DDR SDRAM also supports burst lengths of two.(2) The write clock signals never go to hi-Z state on RLDRAM II and QDRII SRAM memory interfaces because they use

free-running clocks. However, the general timing relationship between data and the read clock shown in this figurestill applies.

f For more information on DDR SDRAM and DDR2 SDRAM

specifications, refer to JEDEC standard publications JESD79C and JESD79-2, respectively, from www.jedec.org , or see AN 327: InterfacingDDR SDRAM with Stratix II Devices and AN 327: Interfacing DDRSDRAM with Stratix II Devices .

RLDRAM II

RLDRAM II provides fast random access as well as high bandwidth andhigh density, making this memory technology ideal for high-speednetwork and communication data storage applications. The fast randomaccess speeds in RLDRAM II devices make them a viable alternative to

SRAM devices at a lower cost. Additionally, RLDRAM II devices haveminimal latency to support designs that require fast response times.

Interface Pins

RLDRAM II devices use interface pins such as data, clock, command, andaddress pins. There are two types of RLDRAM II memory: common I/O(CIO) and separate I/O (SIO). The data pins in a RLDRAM II CIO deviceare bidirectional while the data pins in a RLDRAM II SIO device areunidirectional. Instead of bidirectional data strobes, RLDRAM II usesdifferential free-running read and write clocks to accompany the data. Asin DDR or DDR2 SDRAM, data is sent and captured at twice the systemclock rate by transferring data on the clock’s positive and negative edge.The commands and addresses still only use one active (positive) edge ofa clock.

If the data pins are bidirectional, as in RLDRAM II CIO devices, connectthem to Stratix II and Stratix II GX DQ pins. If the data pins areunidirectional, as in RLDRAM II SIO devices, connect the RLDRAM IIdevice Q ports to the Stratix II and Stratix II GX device DQ pins and

DQS atFPGA Pin

DQ atFPGA Pin

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connect the D ports to any user I/O pins in I/O banks 3, 4, 7, or 8 foroptimal performance. RLDRAM II also uses active-high data mask, DM,pins for writes. You can connect DM pins to any of the I/O pins in thesame bank as the DQ pins of the FPGA when interfacing withRLDRAM II CIO devices to any of the I/O pins in the same bank as the D

pins when interfacing with RLDRAM II SIO devices. There is one DM pinper RLDRAM II device. You can also use I/O pins in banks 1, 2, 5, or 6 tointerface with RLDRAM II devices. However, these banks do not havededicated circuitry and can only support RLDRAM II devices at speedsup to 200 MHz. RLDRAM II interfaces using these banks are supportedusing the 1.8-V HSTL Class I I/O support.

Connect the RLDRAM II device’s read clock pins (QK) to Stratix II orStratix II GX DQS pins. Because of software requirements, you mustconfigure the DQS signals as bidirectional pins. However, since QK pinsare output-only pins from the memory, RLDRAM II memory interfacingin Stratix II and Stratix II GX devices requires that you ground the DQSpin output enables. Stratix II and Stratix II GX devices use the shifted QKsignal from the DQS logic block to capture data. You can leave the QK#signal of the RLDRAM II device unconnected, as DQS and DQSn inStratix II and Stratix II GX devices are not differential pins.

RLDRAM II devices also have input clocks (CK and CK#) and writeclocks (DK and DK#).

You can use any of the user I/O pins for commands and addresses.RLDRAM II also offers QVLD pins to indicate the read data availability.Connect the QVLD pins to the Stratix II or Stratix II GX DQVLD pins,

listed in the pin table.

1 Because the Quartus II software treats the DQVLD pins like DQpins, you should ensure that the DQVLD pin is assigned to thepin table’s recommended pin.


When reading from the RLDRAM II device, data is sent edge-alignedwith the read clock QK and QK#. When writing to the RLDRAM II device,data must be center-aligned with the write clock (DK and DK#). TheRLDRAM II interface uses the same scheme as in DDR or DDR2 SDRAMinterfaces, where the dedicated circuitry is used during reads tocenter-align the data and the read clock inside the FPGA and the PLLcenter-aligns the data and write clock outputs. The data and clockrelationship for reads and writes in RLDRAM II is similar to those in DDRand DDR2 SDRAM as shown in Figures 3–3 and 3–4.

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f For details on RLDRAM II, see AN 325: Interfacing RLDRAM II withStratix II & Stratix GX Devices .

QDRII SRAM

QDRII SRAM is the second generation of QDR SRAM devices. Bothdevices can transfer four words per clock cycle, fulfilling therequirements facing next-generation communications system designers.QDRII SRAM devices provide concurrent reads and writes, zero latency,and increased data throughput, allowing simultaneous access to the sameaddress location. QDRII SRAM is available in burst-of-2 and burst-of-4devices. Burst-of-2 devices support two-word data transfer on all readand write transactions, and burst-of-4 devices support four-word datatransfer

Interface Pins

QDRII SRAM uses two separate, unidirectional data ports for read andwrite operations, enabling QDR data transfer. QDRII SRAM uses sharedaddress lines for reads and writes. QDRII SRAM burst-of-two devicessample the read address on the rising edge of the clock and sample thewrite address on the falling edge of the clock while QDRII SRAM burst-of-four devices sample both read and write addresses on the clock’srising edge. Connect the memory device’s Q ports (read data) to theStratix II or Stratix II GX DQ pins. You can use any of the Stratix II orStratix II GX device user I/O pins in I/O banks 3, 4, 7, or 8 for the D ports(write data), commands, and addresses. The control signals are sampledon the rising edge of the clock. You can also use I/O pins in banks 1, 2, 5,or 6 to interface with QDRII SRAM devices. However, these banks do nothave dedicated circuitry and can only support QDRII SRAM devices atspeeds up to 200 MHz. QDRII SRAM interfaces using these banks aresupported using the 1.8-V HSTL Class I I/O support.

QDRII SRAM uses the following clock signals:

■ Input clocks K and K#■ Output clocks C and C#■ Echo clocks CQ and CQ#

Clocks C#, K#, and CQ# are logical complements of clocks C, K, and CQ,respectively. Clocks C, C#, K, and K# are inputs to the QDRII SRAM whileclocks CQ and CQ# are outputs from the QDRII SRAM. Stratix II andStratix II GX devices use single-clock mode for single-device QDRIISRAM interfacing where the K and K# are used for write operations, andCQ and CQ# are used for read operations. You should use both C or C#and K or K# clocks when interfacing with a bank of multiple QDRIISRAM devices with a single controller.





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You can generate C, C#, K, and K# clocks using any of the I/O registersvia the DDR registers. Because of strict skew requirements between K andK# signals, use adjacent pins to generate the clock pair.

Connect CQ and CQ# pins to the Stratix II or Stratix II GX DQS and DQSn

pins for DLL-based implementations. You must configure DQS andDQSn as bidirectional pins. However, since CQ and CQ# pins areoutput-only pins from the memory, the Stratix II or Stratix II GX deviceQDRII SRAM memory interface requires that you ground the DQS andDQSn output enable. To capture data presented by the memory, connectthe shifted CQ signal to the input latch and connect the active-high inputregisters and the shifted CQ# signal is connected to the active-low inputregister. For PLL-based implementations, connect QK to the input of theread PLL and leave QK# unconnected.


Figure 3–5 shows the data and clock relationships in QDRII SRAMdevices at the memory pins during reads. Data is output one-and-a-halfclock cycles after a read command is latched into memory. QDRII SRAMdevices send data within a t CO time after each rising edge of the read clockC or C# in multi-clock mode, or the input clock K or K# in single clockmode. Data is valid until t DOH time after each rising edge of the read clockC or C# in multi-clock mode or the input clock K or K# in single clockmode. The CQ and CQ# clocks are edge-aligned with the read data signal.These clocks accompany the read data for data capture in Stratix II andStratix II GX devices.

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Figure 3–5. Data and Clock Relationship During a QDRII SRAM Read Note (1)

Notes to Figure 3–5:(1) This relationship is at the memory device. The timing parameter nomenclature is based on the Cypress QDRII

SRAM data sheet for CY7C1313V18.(2) tCO is the data clock-to-out time and t DOH is the data output hold time between burst.(3) tCLZ and t CHZ are bus turn-on and turn-off times respectively.(4) tCQD is the skew between the rising edge of CQ or CQ# and the data edges.(5) tCCQO and t CQOH are skew measurements between the C or C# clocks (or the K or K# clocks in single-clock mode)

and the CQ or CQ# clocks.

When reading from the QDRII SRAM, data is sent edge-aligned with therising edge of the echo clocks CQ and CQ#. Both CQ and CQ# are shiftedinside the FPGA using DQS and DQSn logic blocks to capture the data inthe DDR IOE registers in DLL-based implementations. In PLL-basedimplementations, CQ feeds a PLL, which generates the clock to capturethe data in the DDR IOE registers.

When writing to QDRII SRAM devices, data is generated by the writeclock while the K clock is 90° shifted from the write clock, creating acenter-aligned arrangement.

Read and write operations occur during the same clock cycle onindependent read and write data paths along with the cycle-shared

address bus. Performing concurrent reads and writes does not change thefunctionality of either transaction. If a read request occurs simultaneouslywith a write request at the same address, the new data on D is forwardedto Q. Therefore, latency is not required to access valid data.

f For more information on QDRII SRAM, go to www.qdrsram.com or seeAN 326: Interfacing QDRII & QDRII+ SRAM with Stratix II, Stratix, &Stratix GX Devices .

QA QA + 1 QA + 2 QA + 3

C/K

C#/K#

CQ

CQ#

Q

t CO (2) t CO (2)

t CLZ (3)

t CCQO (5) t CQOH (5)

t CQD (4)

t CQD (4)

t DOH (2) t CHZ (3)

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Stratix II andStratix II GXDDR Memory

SupportOverview

This section describes Stratix II and Stratix II GX features that enablehigh-speed memory interfacing. It first describes Stratix II andStratix II GX memory pins and then the DQS phase-shift circuitry and theDDR I/O registers. Table 3–2 shows the I/O standard associated with theexternal memory interfaces.

Stratix II and Stratix II GX devices support the data strobe or read clocksignal (DQS) used in DDR SDRAM, DDR2 SDRAM, RLDRAM II, andQDRII SRAM devices with dedicated circuitry. Stratix II and Stratix II GXdevices also support the DQSn signal (the DQS complement signal) for

external memory types that require them, for example QDRII SRAM.DQS and DQSn signals are usually associated with a group of data (DQ)pins. However, these are not differential buffers and cannot be used inDDR2 SDRAM or RLDRAM II interfaces.

1 You can also interface with these external memory deviceswithout the use of dedicated circuitry at a lower performance.

f For more information, see the appropriate Stratix II or Stratix II GXmemory interfaces application note available at www.altera.com .

Stratix II and Stratix II GX devices contain dedicated circuitry to shift theincoming DQS signals by 0°, 22.5°, 30°, 36°, 45°, 60°, 67.5°, 72°, 90°, 108°,120°, or 144°, depending on the delay-locked loop (DLL) mode. There arefour DLL modes. The DQS phase-shift circuitry uses a frequencyreference to dynamically generate control signals for the delay chains ineach of the DQS and DQSn pins, allowing it to compensate for process,

Table 3–2. External Memory Support in Stratix II and Stratix II GX Devices

Memory Standard I/O Standard

DDR SDRAM SSTL-2 Class II

DDR2 SDRAM SSTL-18 Class II (1)

RLDRAM II (2) 1.8-V HSTL Class I or II (1)

QDRII SRAM (2) 1.8-V HSTL Class I or II (1)

Notes to Table 3–2 :(1) Stratix II and Stratix II GX devices support 1.8-V HSTL/SSTL-18 Class I and II

I/O standards in I/O banks 3, 4, 7, and 8. In I/O banks 1, 2, 5, and 6, Class I issupported for both input and output operations, while Class II is only supportedfor input operations for these I/O standards.

(2) For maximum performance, Altera recommends using the 1.8-V HSTL I/Ostandard. RLDRAM II and QDRII SRAM devices also support the 1.5-V HSTLI/O standard.



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Stratix II and Stratix II GX DDR Memory Support Overview

voltage, and temperature (PVT) variations. This phase-shift circuitry has been enhanced in Stratix II and Stratix II GX devices to support morephase-shift options with less jitter.

Besides the DQS dedicated phase-shift circuitry, each DQS and DQSn pin

has its own DQS logic block that sets the delay for the signal input to thepin. Using the DQS dedicated phase-shift circuitry with the DQS logic block allows for phase-shift fine-tuning. Additionally, every IOE in aStratix II or Stratix II GX device contains six registers and one latch toachieve DDR operation.

DDR Memory Interface Pins

Stratix II and Stratix II GX devices use data (DQ), data strobe (DQS andDQSn), and clock pins to interface with external memory.

Figure 3–6 shows the DQ, DQS, and DQSn pins in the Stratix II orStratix II GX I/O banks on the top of the device. A similar arrangement isrepeated at the bottom of the device.

Figure 3–6. DQ and DQS Pins Per I/O Bank

Data and Data Strobe Pins

Stratix II and Stratix II GX data pins for the DDR memory interfaces arecalled DQ pins. Stratix II and Stratix II GX devices can use either bidirectional data strobes or unidirectional read clocks. Depending on theexternal memory interface, either the memory device’s read data strobesor read clocks feed the Stratix II or Stratix II GX DQS (and DQSn) pins.

PLL 11 PLL 5

I/OBank 11

I/OBank 3

I/OBank 9

I/OBank 4

DQSPhaseShift

Circuitry

DQ Pins

DQ Pins

DQS Pin

DQSn Pin

DQSn Pin

DQS Pin

Up to 8 Sets of DQ & DQS Pins


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Stratix II and Stratix II GX DQS pins connect to the DQS pins in DDR andDDR2 SDRAM interfaces or to the QK pins in RLDRAM II interfaces. TheDQSn pins are not used in these interfaces. Connect the Stratix II orStratix II GX DQS and DQSn pins to the QDRII SRAM CQ and CQ# pins,respectively.

In every Stratix II or Stratix II GX device, the I/O banks at the top (I/O banks 3 and 4) and bottom (I/O banks 7 and 8) of the device support DDRmemory up to 300 MHz/600 Mbps (with RLDRAM II). These I/O bankssupport DQS signals and its complement DQSn signals with DQ busmodes of ×4, ×8/×9, ×16/×18, or ×32/×36.

In ×4 mode, each DQS/DQSn pin drives up to four DQ pins within thatgroup. In ×8/×9 mode, each DQS/DQSn pin drives up to nine DQ pinswithin that group to support one parity bit and the eight data bits. If theparity bit or any data bit is not used, the extra DQ pins can be used asregular user I/O pins. Similarly, with ×16/×18 and ×32/×36 modes, eachDQS/DQSn pin drives up to 18 and 36 DQ pins respectively. There aretwo parity bits in the ×16/×18 mode and four parity bits in the ×32/×36mode. Tables 3–3 through 3–6 show the number of DQS/DQ groups andnon-DQS /DQ supported in each Stratix II or Stratix II GXdensity/package combination, respectively, for DLL-basedimplementations.

Table 3–3. Stratix II DQS and DQ Bus Mode Support (Part 1 of 2) Note (1)

Device Package Number of×4 Groups

Number of×8/×9 Groups



EP2S15 484-pin FineLine BGA 8 4 0 0

672-pin FineLine BGA 18 8 4 0





1,020-pin FineLine BGA 36 18 8 4

EP2S90 484-pin Hybrid FineLine BGA 8 4 0 0

780-pin FineLine BGA 18 8 4 01,020-pin FineLine BGA 36 18 8 4





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EP2S180 1,020-pin FineLine BGA 36 18 8 4


Note to Table 3–3 :(1) Check the pin table for each DQS/DQ group in the different modes.

Table 3–3. Stratix II DQS and DQ Bus Mode Support (Part 2 of 2) Note (1)





Table 3–4. Stratix II non-DQS and DQ Bus Mode Support Note (1)

Device Package Number of

×4 Groups

Number of

×8/×9 Groups

Number of

×16/×18 Groups

Number of

×32/×36 GroupsEP2S15 484-pin FineLine BGA 13 7 3 1








1,020-pin FineLine BGA 51 25 12 61,508-pin FineLine BGA 51 25 12 6




EP2S180 1,020-pin FineLine BGA 51 25 12 6



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1 To support the RLDRAM II QVLD pin, some of the unused ×4

DQS pins, whose DQ pins were combined to make the bigger×8/×9, ×16/×18, or ×32/×36 groups, are listed as DQVLD pinsin the Stratix II or Stratix II GX pin table. DQVLD pins are forinput-only operations. The signal coming into this pin can becaptured by the shifted DQS signal like any of the DQ pins.

Table 3–5. Stratix II GX DQS and DQ Bus Mode Support Note (1)

Device PackageNumber of×4 Groups




EP2SGX30CEP2SGX30D


EP2SGX60CEP2SGX60D


EP2SGX60E 1,152-pin FineLine BGA 36 18 8 4

EP2SGX90E 1,152-pin FineLine BGA 36 18 8 4

EP2SGX90F 1,508-pin FineLine BGA 36 18 8 4

EP2SGX130G 1,508-pin FineLine BGA 36 18 8 4


Table 3–6. Stratix II GX Non-DQS and DQ Bus Mode Support Note (1)





EP2SGX30 780-pin FineLine BGA 18 8 4 2

EP2SGX60 780-pin FineLine BGA 18 8 4 21,152-pin FineLine BGA 25 13 6 3

EP2SGX90 1,152-pin FineLine BGA 25 13 6 3


EP2SGX130 1,508-pin FineLine BGA 25 12 6 3


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The DQS pins are listed in the Stratix II or Stratix II GX pin tables asDQS[17..0]T or DQS[17..0]B . The T denotes pins on the top of thedevice and the B denotes pins on the bottom of the device. Thecomplement DQSn pins are marked as DQSn[17..0]T orDQSn[17..0]B . The corresponding DQ pins are marked as

DQ[17..0]T[3..0] , where [17..0] indicates which DQS group thepins belong to. Similarly, the corresponding DQVLD pins are marked asDQVLD[8..0]T , where [8..0] indicates which DQS group the pins belong to. The numbering scheme starts from right to left on the package bottom view. When not used as DQ, DQS, or DQSn pins, these pins areavailable as regular I/O pins. Figure 3–7 shows the DQS pins in Stratix IIor Stratix II GX I/O banks.

1 The Quartus II software treats DQVLD pins as regular DQ pins.Therefore, you must ensure that the DQVLD pin assigned inyour design corresponds to the pin table’s recommendedDQVLD pins.

Figure 3–7. DQS Pins in Stratix II and Stratix II GX I/O Banks Notes (1) , (2) , (3)

Notes to Figure 3–7 :(1) There are up to 18 pairs of DQS and DQSn pins on both the top and bottom of the device. See Table 3–3 for the exact

number of DQS and DQSn pin pairs in each device package.(2) See Table 3–7 for the available DQS and DQSn pins in each mode and package.(3) Each DQS pin has a complement DQSn pin. DQS and DQSn pins are not differential.

The DQ pin numbering is based on ×4 mode. There are up to 8 DQS/DQ

groups in ×4 mode in I/O banks 3 and 8 and up to 10 DQS/DQ groups in×4 mode in I/O banks 4 and 7. In ×8/×9 mode, two adjacent ×4 DQS/DQgroups plus one parity pin are combined; one pair of DQS/DQSn pinsfrom the combined groups can drive all the DQ and parity pins. Sincethere is an even number of DQS/DQ groups in an I/O bank, combininggroups is efficient. Similarly, in ×16/×18 mode, four adjacent ×4 DQS/DQgroups plus two parity pins are combined and one pair of DQS/DQSnpins from the combined groups can drive all the DQ and parity pins. In

PLL 11 PLL 5

I/OBank 11I/OBank 3 I/OBank 9 I/OBank 4

DQSPhase

ShiftCircuitry

DQ Pins

DQ Pins

DQS Pin

DQSn Pin

DQSn Pin

DQS Pin



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×32/×36 mode, eight adjacent DQS/DQ groups are combined and onepair of DQS/DQSn pins can drive all the DQ and parity pins in thecombined groups.

Table 3–7 shows which DQS and DQSn pins are available in each mode

and package in the Stratix II or Stratix II GX device family.

1 On the top and bottom side of the device, the DQ and DQS pinsmust be configured as bidirectional DDR pins to enable the DQSphase-shift circuitry. The DQSn pins can be configured as input,output, or bidirectional pins. You can use the altdq and

altdqs megafunctions to configure the DQ and DQS/DQSnpaths, respectively. However, Altera highly recommends thatyou use the respective Altera memory controller IP Tool Benchfor your external memory interface data paths. The data path isclear-text and free to use. You are responsible for your owntiming analysis if you use your own data path. If you only wantto use the DQ and/or DQS pins as inputs, you need to set theoutput enable of the DQ and/or DQS pins to ground.

Stratix II or Stratix II GX side I/O banks (I/O banks 1, 2, 5, and 6) supportall the memory interfaces supported in the top and bottom I/O banks. Foroptimal performance, use the Altera memory controller IP Tool Bench topick the data and strobe pins for these interfaces. Since these I/O banksdo not have any dedicated circuitry for memory interfacing, they cansupport DDR SDRAM at speeds up to 150 MHz and other DDR memoriesat speeds up to 200 MHz. You need to use the SSTL-18 Class I I/Ostandard when interfacing with DDR2 SDRAM devices using pins in I/O bank 1, 2, 5, or 6. These I/O banks do not support the SSTL-18 Class II and

Table 3–7. Available DQS and DQSn Pins in Each Mode and Package Note (1)

Mode

Package

484-Pin FineLine BGA484-Pin Hybrid FineLine BGA

672-Pin FineLine BGA780-Pin FineLine BGA

1,020-Pin FineLine BGA1,508-Pin FineLine BGA

×4 7, 9, 11, 13 Odd-numbered pins only All DQS and DQSn pins

×8/×9 7,11 3, 7, 11, 15 Even-numbered pins only

×16/×18 N/A 5, 13 3, 7, 11, 15

×32/×36 N/A N/A 5, 13

Note to Table 3–7 :(1) The numbers correspond to the DQS and DQSn pin numbering in the Stratix II or Stratix II GX pin table. There are

two sets of DQS/DQ groups, one corresponding with the top side of the device and one with the bottom side ofthe device.

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1.8-V HSTL Class II I/O standards on output and bidirectional pins, butyou can use SSTL-18 Class I or 1.8-V HSTL Class I I/O standards formemory interfaces.

1 The Altera memory controller IP Tool Bench generates the

optimal pin constraints that allow you to interface thesememories at high frequency.

Table 3–8 shows the maximum clock rate supported for the DDR SDRAMinterface in the Stratix II or Stratix II GX device side I/O banks.

Clock Pins

You can use any of the DDR I/O registers to generate clocks to thememory device. For better performance, use the same I/O bank as thedata and address/command pins.

Command and Address Pins

You can use any of the user I/O pins in the top or bottom bank of thedevice for commands and addresses. For better performance, use thesame I/O bank as the data pins.

Other Pins (Parity, DM, ECC and QVLD Pins)

You can use any of the DQ pins for the parity pins in Stratix II andStratix II GX devices. The Stratix II or Stratix II GX device family hassupport for parity in the ×8/×9, ×16/×18, and ×32/×36 mode. There isone parity bit available per 8 bits of data pins.

The data mask, DM, pins are only required when writing to DDRSDRAM, DDR2 SDRAM, and RLDRAM II devices. A low signal on theDM pins indicates that the write is valid. If the DM signal is high, thememory will mask the DQ signals. You can use any of the I/O pins in thesame bank as the DQ pins (or the RLDRAM II SIO’s and QDRII SRAM’sD pins) for the DM signals. Each group of DQS and DQ signals in DDR

Table 3–8. Maximum Clock Rate for DDR and DDR2 SDRAM in Stratix II or Stratix II GX Side I/O Banks

Stratix II or Stratix II GXDevice Speed Grade

DDR SDRAM(MHz)

DDR2 SDRAM(MHz)

QDRII SRAM(MHz)

RLDRAM II(MHz)

-3 150 200 200 200

-4 133 167 167 175

-5 133 167 167 175

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and DDR2 SDRAM devices requires a DM pin. There is one DM pin perRLDRAM II device. The DDR I/O output registers, clocked by the –90°shifted clock, creates the DM signals, similar to DQ output signals.

1 Perform timing analysis to calculate your write-clock phase

shift.

Some DDR SDRAM and DDR2 SDRAM devices support error correctioncoding (ECC), which is a method of detecting and automaticallycorrecting errors in data transmission. In a 72-bit DDR SDRAM interface,there are eight ECC pins in addition to the 64 data pins. Connect the DDRand DDR2 SDRAM ECC pins to a Stratix II or Stratix II GX deviceDQS/DQ group. The memory controller needs extra logic to encode anddecode the ECC data.

QVLD pins are used in RLDRAM II interfacing to indicate the read dataavailability. There is one QVLD pin per RLDRAM II device. A high onQVLD indicates that the memory is outputting the data requested.Similar to DQ inputs, this signal is edge-aligned with QK/QK# signalsand is sent half a clock cycle before data starts coming out of the memory.You need to connect QVLD pins to the DQVLD pin on the Stratix II orStratix II GX device. The DQVLD pin can be used as a regular user I/Opin if not used for QVLD. Because the Quartus II software does notdifferentiate DQVLD pins from DQ pins, you must ensure that yourdesign uses the pin table’s recommended DQVLD pin.

DQS Phase-Shift Circuitry

The Stratix II or Stratix II GX phase-shift circuitry and the DQS logic block control the DQS and DQSn pins. Each Stratix II or Stratix II GXdevice contains two phase-shifting circuits. There is one circuit for I/O banks 3 and 4, and another circuit for I/O banks 7 and 8. The phase-shifting circuit on the top of the device can control all the DQS and DQSnpins in the top I/O banks and the phase-shifting circuit on the bottom ofthe device can control all the DQS and DQSn pins in the bottom I/O banks. Figure 3–8 shows the DQS and DQSn pin connections to the DQSlogic block and the DQS phase-shift circuitry.

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Figure 3–8. DQS and DQSn Pins and the DQS Phase-Shift Circuitry Note (1)

Notes to Figure 3–8:(1) There are up to 18 pairs of DQS and DQSn pins available on the top or the bottom of the Stratix II or Stratix II GX

device, up to 8 on the left side of the DQS phase-shift circuitry (I/O banks 3 and 8), and up to 10 on the right side(I/O bank 4 and 7).

(2) Clock pins CLK[15..12]p feed the phase-shift circuitry on the top of the device and clock pins CLK[7..4]p feedthe phase-shift circuitry on the bottom of the device. You can also use a phase-locked loop (PLL) clock output as areference clock to the phase-shift circuitry. The reference clock can also be used in the logic array.

(3) You can only use PLL 5 to feed the DQS phase-shift circuitry on the top of the device and PLL 6 to feed the DQSphase-shift circuitry on the bottom of the device.

Figure 3–9 shows the connections between the DQS phase-shift circuitryand the DQS logic block.

DQSPin

DQSnPin

DQSnPin

DQSPin

DQSPin

DQSnPin

DQSPin

DQSnPin

From PLL 5 (3)

CLK[15..12]p (2)

to IOE to IOE to IOE to IOEto IOE to IOEto IOE

Δ tΔ tΔ tΔ tΔ tΔ t Δ t

to IOE

DQSPhase-Shift

CircuitryΔ t DQS Log

Blocks

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Figure 3–9. DQS Phase-Shift Circuitry and DQS Logic Block Connections Note (1)

Notes to Figure 3–9:(1) All features of the DQS phase-shift circuitry and the DQS logic block are accessible from the altdqs megafunction

in the Quartus II software. You should, however, use Altera’s memory controller IP Tool Bench to generate the datapath for your memory interface.

(2) DQS logic block is available on every DQS and DQSn pin.(3) There is one DQS phase-shift circuit on the top and bottom side of the device.(4) The input reference clock can come from CLK[15..12]p or PLL 5 for the DQS phase-shift circuitry on the top side

of the device or from CLK[7..4]p or PLL 6 for the DQS phase-shift circuitry on the bottom side of the device.(5) Each individual DQS and DQSn pair can have individual DQS delay settings to and from the logic array.(6) This register is one of the DQS IOE input registers.

6

6

P h a s e

O f f s e

t

C o n

t r o l

6

P h a s e o

f f s e t

s e

t t i n g s

f r o m

t h e

l o g

i c a r r a y

P h a s e

O f f s e t

S e t t i n g s

I n p u

t r e

f e r e n c e

c l o c k

( 4 )

u p n

d n

c l o c k e n a

b l e

D L L

6

a d d n s u

b

P h a s e

C o m p a r a

t o r D

e l a y

C h a

i n s

U p

/ D o w n

C o u n

t e r

D

Q

D

Q

E N

E N

U p

d a

t e

E n a

b l e

C i r c u i t r y

6

6

6

6

6

6

D Q S D e

l a y

S e

t t i n g s t o a n

d f r o m

t h e

L o g i c

A r r a y

( 5 )

D Q S D e

l a y

S e

t t i n g s

f r o m

t h e

D Q S P h a s e - S

h i f t

C i r c u i t r y

D Q S o r

D Q S n

D

Q S D e

l a y

C h a

i n

B y p a s s

D Q S L o g

i c B l o c k

( 2 )

D Q S L o g

i c B l o c k

( 2 )

D Q S L o g

i c B l o c k

( 2 )

D Q S P h a s e - S

h i f t C i r c u

i t r y ( 3 )

D Q S o r

D Q S n

D Q S o r

D Q S n

N O T

P o s t a m

b l e C i r c u

i t r y

g a

t e d

_ d q s c o n

t r o l

D Q S

b u s

P R N

C L R N

Q D F F

r e s e

t

E n a

b l e N

A

B

V C C

D Q S '

S C L R

( 6 )

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The phase-shift circuitry is only used during read transactions where theDQS and DQSn pins are acting as input clocks or strobes. The phase-shiftcircuitry can shift the incoming DQS signal by 0°, 22.5°, 30°, 36°, 45°, 60°,67.5°, 72°, 90°, 108°, 120°, or 144°. The shifted DQS signal is then used asclocks at the DQ IOE input registers.

Figure 3–3 shows an example where the DQS signal is shifted by 90°. TheDQS signals goes through the 90° shift delay set by the DQS phase-shiftcircuitry and the DQS logic block and some routing delay from the DQSpin to the DQ IOE registers. The DQ signals only goes through routingdelay from the DQ pin to the DQ IOE registers and maintains the 90°relationship between the DQS and DQ signals at the DQ IOE registerssince the software will automatically set delay chains to match the routingdelay between the pins and the IOE registers for the DQ and DQS inputpaths.

All 18 DQS and DQSn pins on either the top or bottom of the device canhave their input signal phase shifted by a different degree amount but allmust be referenced at one particular frequency. For example you can havea 90° phase shift on DQS0T and have a 60° phase shift on DQS1T bothreferenced from a 200-MHz clock. Not all phase-shift combinations aresupported, however. The phase shifts on the same side of the device mustall be a multiple of 22.5° (up to 90°), a multiple of 30° (up to 120°), or amultiple of 36° (up to 144°).

In order to generate the correct phase shift with the DLL used, you mustprovide a clock signal of the same frequency as the DQS signal to the DQSphase-shift circuitry. Any of the CLK[15..12]p clock pins can feed the

phase circuitry on the top of the device (I/O banks 3 and 4) or any of theCLK[7..4]p clock pins can feed the phase circuitry on the bottom of thedevice (I/O banks 7 and 8). Stratix II and Stratix II GX devices can alsouse PLLs 5 or 6 as the reference clock to the DQS phase-shift circuitry onthe top or bottom of the device, respectively. PLL 5 is connected to theDQS phase-shift circuitry on the top side of the device and PLL 6 isconnected to the DQS phase-shift circuitry on the bottom side of thedevice. Both the top and bottom phase-shift circuits need unique clockpins or PLL clock outputs for the reference clock.

1 When you have a PLL dedicated only to generate the DLL inputreference clock, you must set the PLL mode to “NoCompensation” or the Quartus ® II software will change itautomatically. Because there are no other PLL outputs used, thePLL doesn’t need to compensate for any clock paths.

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DLL

The DQS phase-shift circuitry uses a delay-locked loop (DLL) todynamically measure the clock period needed by the DQS/DQSn pin (seeFigure 3–10 ). The DQS phase-shift circuitry then uses the clock period togenerate the correct phase shift. The DLL in the Stratix II or Stratix II GXDQS phase-shift circuitry can operate between 100 and 400 MHz. Thephase-shift circuitry needs a maximum of 256 clock cycles to calculate thecorrect input clock period. Data sent during these clock cycles may not beproperly captured.

1 Although the DLL can run up to 400 MHz, other factors mayprevent you from interfacing with a 400-MHz external memorydevice.

1 You can still use the DQS phase-shift circuitry for any memoryinterfaces that are less than 100 MHz. The DQS signal will be

shifted by 2.5 ns and you can add more shift by using the phaseoffset module. Even if the DQS signal is not shifted exactly to themiddle of the DQ valid window, the IOE should still be able tocapture the data in this low frequency application.

There are four different frequency modes for the Stratix II or Stratix II GXDLL. Each frequency mode provides different phase shift, as shown inTable 3–9.

In frequency mode 0, Stratix II devices use a 6-bit setting to implement thephase-shift delay. In frequency modes 1, 2, and 3, Stratix II devices onlyuse a 5-bit setting to implement the phase-shift delay.

The DLL can be reset from either the logic array or a user I/O pin. Thissignal is not shown in Figure 3–10 . Each time the DLL is reset, you mustwait for 256 clock cycles before you can capture the data properly.

Table 3–9. Stratix II and Stratix II GS DLL Frequency Modes

FrequencyMode Frequency Range (MHz) Available

Phase ShiftNumber of

Delay Chains

0 100–175 30, 60, 90,120

12

1 150–230 22.5, 45,67.5, 90

16

2 200–310 30, 60, 90,120

12

3 240–400 (C3 speed grade)240–350 (C4 and C5 speed grades)

36, 72, 108,144

10

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1 The input reference clock for the DQS phase-shift circuitry onthe top side of the device can come from CLK[15..12]p orPLL 5. The input reference clock for the DQS phase-shiftcircuitry on the bottom side of the device can come fromCLK[7..4]p or PLL 6.

Table 3–10 lists the maximum delay in the fast timing model for theStratix II DQS delay buffer. Multiply the number of delay buffers that youare using in the DQS logic block to get the maximum delay achievable inyour system. For example, if you implement a 90° phase shift at 200 MHz,you use three delay buffers in mode 2. The maximum achievable delayfrom the DQS block is then 3 × .416 ps = 1.248 ns.

Table 3–10. DQS Delay Buffer Maximum Delay in Fast Timing Model

Frequency

Mode

Maximum Delay Per Delay Buffer

(Fast Timing Model)Unit

0 0.833 ns

1, 2, 3 0.416 ns

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Figure 3–10. Simplified Diagram of the DQS Phase-Shift Circuitry Note (1)

Notes to Figure 3–10 :(1) All features of the DQS phase-shift circuitry are accessible from the altdqs megafunction in the Quartus II software.

You should; however, use Altera’s memory controller IP Tool Bench to generate the data path for your memoryinterface.

(2) The input reference clock for the DQS phase-shift circuitry on the top side of the device can come fromCLK[15..12]p or PLL 5. The input reference clock for the DQS phase-shift circuitry on the bottom side of thedevice can come from CLK[7..4]p or PLL 6.

(3) Phase offset settings can only go to the DQS logic blocks.(4) DQS delay settings can go to the logic array and/or to the DQS logic block.

The input reference clock goes into the DLL to a chain of up to 16 delayelements. The phase comparator compares the signal coming out of theend of the delay element chain to the input reference clock. The phasecomparator then issues the upndn signal to the up/down counter. Thissignal increments or decrements a six-bit delay setting (DQS delaysettings) that will increase or decrease the delay through the delayelement chain to bring the input reference clock and the signals comingout of the delay element chain in phase.

The DQS delay settings contain the control bits to shift the signal on theinput DQS pin by the amount set in the altdqs megafunction. For the 0°shift, both the DLL and the DQS logic block are bypassed. Since Stratix IIand Stratix II GX DQS and DQ pins are designed such that the pin to IOEdelays are matched, the skew between the DQ and DQS pin at the DQ IOEregisters is negligible when the 0° shift is implemented. You can feed theDQS delay settings to the DQS logic block and the logic array.

6

6

6

PhaseOffset

Control

6

Phase offset settingsfrom the logic array

Phase offsetsettings (3)

DQS delay

settings (4)

Input referenceclock (2) upndn

clock enable

DLL

6

addnsub

PhaseComparator

Delay Chains

Up/DownCounter

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Phase Offset Control

The DQS phase-shift circuitry also contains a phase offset control modulethat can add or subtract a phase offset amount from the DQS delay setting(phase offset settings from the logic array in Figure 3–10 ). You should usethe phase offset control module for making small shifts to the input signaland use the DQS phase-shift circuitry for larger signal shifts. For example,if you need the input signal to be shifted by 75°, you can set the altdqs megafunction to generate a 72° phase shift with a phase offset of +3°.

You can either use a static phase offset or a dynamic phase offset toimplement the additional phase shift. The available additional phase shiftis implemented in 2s-complement between settings –64 to +63 forfrequency mode 0, and between settings –32 to +31 for frequency modes1, 2, and 3. However, the DQS delay settings are at the maximum atsetting 64 for frequency mode 0, and at the maximum at setting 32 forfrequency modes 1, 2, and 3. Therefore, the actual physical offset setting

range will be 64 or 32 subtracted by the DQS delay settings from the DLL.

For example, if the DLL determines that to achieve 30° you will need aDQS delay setting of 28, you can subtract up to 28 phase offset settingsand you can add up to 36 phase offset settings to achieve the optimaldelay.

1 Each phase offset setting translates to a certain delay, asspecified in the DC & Switching Characteristics of Stratix III Deviceschapter in volume 2 of the Stratix III Device Handbook.

When using the static phase offset, you can specify the phase offsetamount in the altdqs megafunction as a positive number for addition ora negative number for subtraction. You can also have a dynamic phaseoffset that is always added to, subtracted from, or both added to andsubtracted from the DLL phase shift. When you always add or subtract,you can dynamically input the phase offset amount into thedll_offset[5..0] port. When you want to both add and subtractdynamically, you control the addnsub signal in addition to thedll_offset[5..0] signals.

DQS Logic Block

Each DQS and DQSn pin is connected to a separate DQS logic block (seeFigure 3–11 ). The logic block contains DQS delay chains and postamblecircuitry.

http://www.altera.com/literature/hb/stx3/stx3_siii52001.pdf




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1 The input reference clock for the DQS phase-shift circuitry onthe top side of the device can come from CLK[15..12]p orPLL 5. The input reference clock for the DQS phase-shiftcircuitry on the bottom side of the device can come fromCLK[7..4]p or PLL 6.

Figure 3–11. Simplified Diagram of the DQS Logic Block Note (1)

Notes to Figure 3–11 :(1) All features of the DQS logic block are accessible from the altdqs megafunction in the Quartus II software. You

should; however, use Altera’s memory controller IP Tool Bench to generate the data path for your memory interface.(2) The input reference clock for the DQS phase-shift circuitry on the top side of the device can come from

CLK[15..12]p or PLL 5. The input reference clock for the DQS phase-shift circuitry on the top side of the devicecan come from CLK[7..4]p or PLL 6.

(3) This register is one of the DQS IOE input registers.

D

Q

D

Q

E N

E N

U p d a

t e

E n a

b l e

C i r c u i t r y

6

6

6

6

6

6

D Q S D e

l a y

S e

t t i n g s

f r o m

t h e

D Q S P h a s e -

S h i f t C i r c u i t r y

D Q S o r

D Q S n

P i n

I n p u

t R e

f e r e n c e

C l o c k

( 2 )

D Q S D e

l a y C h a

i n

B y p a s s

P h a s e

O f f s e t

S e

t t i n g s

6 6

N O T

P o s t a m

b l e C i r c u i t r y

g a

t e d

_ d q s c o n

t r o l

D Q S b u s

P R N

C L R N

Q D F F

r e s e

t

E n a

b l e N

A

B

V C C

D Q S '

S C L R

( 3 )

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DQS Delay Chains

The DQS delay chains consist of a set of variable delay elements to allowthe input DQS and DQSn signals to be shifted by the amount given by theDQS phase-shift circuitry or the logic array. There are four delay elementsin the DQS delay chain; the first delay chain closest to the DQS pin caneither be shifted by the DQS delay settings or by the sum of the DQS delaysetting and the phase-offset setting. The number of delay chains used istransparent to the users because the altdqs megafunction automaticallysets it. The DQS delay settings can come from the DQS phase-shiftcircuitry on the same side of the device as the target DQS logic block orfrom the logic array. When you apply a 0° shift in the altdqs megafunction, the DQS delay chains are bypassed.

The delay elements in the DQS logic block mimic the delay elements inthe DLL. When the DLL is not used to control the DQS delay chains, youcan input your own 6- or 5-bit settings using thedqs_delayctrlin[5..0] signals available in the altdqs megafunction. These settings control 1, 2, 3, or all 4 delay elements in theDQS delay chains. The amount of delay is equal to the sum of the delayelement’s intrinsic delay and the product of the number of delay stepsand the value of the delay steps.

Both the DQS delay settings and the phase-offset settings pass through alatch before going into the DQS delay chains. The latches are controlled by the update enable circuitry to allow enough time for any changes inthe DQS delay setting bits to arrive to all the delay elements. This allowsthem to be adjusted at the same time. The update enable circuitry enablesthe latch to allow enough time for the DQS delay settings to travel fromthe DQS phase-shift circuitry to all the DQS logic blocks before the nextchange. It uses the input reference clock to generate the update enableoutput. The altdqs megafunction uses this circuit by default. SeeFigure 3–12 for an example waveform of the update enable circuitryoutput.

The shifted DQS signal then goes to the DQS bus to clock the IOE inputregisters of the DQ pins. It can also go into the logic array forresynchronization purposes. The shifted DQSn signal can only go to theactive-low input register in the DQ IOE and is only used for QDRII SRAMinterfaces.

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Figure 3–12. DQS Update Enable Waveform

DQS Postamble Circuitry

For external memory interfaces that use a bidirectional read strobe likeDDR and DDR2 SDRAM, the DQS signal is low before going to or coming

from a high-impedance state. See Figure 3–3 . The state where DQS is low, just after a high-impedance state, is called the preamble and the statewhere DQS is low, just before it returns to a high-impedance state, iscalled the postamble. There are preamble and postamble specificationsfor both read and write operations in DDR and DDR2 SDRAM. The DQSpostamble circuitry ensures data is not lost when there is noise on theDQS line at the end of a read postamble time. It is to be used with one ofthe DQS IOE input registers such that the DQS postamble control signalcan ground the shifted DQS signal used to clock the DQ input registers atthe end of a read operation. This ensures that any glitches on the DQSinput signals at the end of the read postamble time do not affect the DQIOE registers.

f See AN 327: Interfacing DDR SDRAM with Stratix II Devices and AN 328:Interfacing DDR2 SDRAM with Stratix II Devices for more details.

DDR Registers

Each IOE in a Stratix II or Stratix II GX device contains six registers andone latch. Two registers and a latch are used for input, two registers areused for output, and two registers are used for output enable control. Thesecond output enable register provides the write preamble for the DQSstrobe in the DDR external memory interfaces. This active low output

enable register extends the high-impedance state of the pin by a half clockcycle to provide the external memory’s DQS write preamble timespecification. Figure 3–13 shows the six registers and the latch in theStratix II or Stratix II GX IOE and Figure 3–14 shows how the second OEregister extends the DQS high-impedance state by half a clock cycleduring a write operation.

Update EnableCircuitry Output

System Clock

DQS Delay Settings(Updated every 8 cycles)

DLL Counter Update (Every Eight Cycles)

6 bit

DLL Counter Update (Every Eight Cycles)







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Figure 3–13. Bidirectional DDR I/O Path in Stratix II and Stratix II GX Devices Note (1)

Notes to Figure 3–13 :(1) All control signals can be inverted at the IOE. The signal names used here match with Quartus II software naming

convention.(2) The OE signal is active low, but the Quartus II software implements this as active high and automatically adds an

inverter before input to the A OE register during compilation.(3) The A OE register generates the enable signal for general-purpose DDR I/O applications.(4) This select line is to choose whether the OE signal should be delayed by half-a-clock cycle.(5) The BOE register generates the delayed enable signal for the write strobes or write clocks for memory interfaces.(6) The tristate enable is by default active low. You can, however, design it to be active high. The combinational control

path for the tristate is not shown in this diagram.(7) You can also have combinational output to the I/O pin; this path is not shown in the diagram.(8) On the top and bottom I/O banks, the clock to this register can be an inverted register A’s clock or a separate clock

(inverted or non-inverted). On the side I/O banks, you can only use the inverted register A’s clock for this port.

DQ

DFF

DQ

ENADQ

DFF

Input Re g ister B I

Input Re g ister A I

Latch C

D Q

DFF

D Q

DFF

01

Output Re g ister A O

Output Re g ister B O

D Q

DFF

D Q

DFF

OR2

TRI I/O Pin (7)

OE Re g ister B OE

OE Re g ister A OE

Log ic Array

dataout_l

dataout_h

outclock

datain_h

datain_l

OE

inclock

ne g _re g _out

I

0

(5)

(4)

(6)

(3)

combout

1

(2)

Latch TCHLA

(8)

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Figure 3–14. Extending the OE Disable by Half-a-Clock Cycle for a Write Transaction Note (1)

Note to Figure 3–14 :(1) The waveform reflects the software simulation result. The OE signal is an active low on the device. However, the

Quartus II software implements this signal as an active high and automatically adds an inverter before the A OE register D input.

Figures 3–15 and 3–16 summarize the IOE registers used for the DQ andDQS signals.

D0

D0 D2

D1

D1 D3

D2 D3

Preamble Postamble

System clock(outclock for DQS)

OE for DQS(from logic array)

datain_h(from logic array)

datain_l(from logic array)

OE for DQ(from logic array)

Write Clock(outclock for DQ,

− 90 ° phase shiftedfrom System Clock)

DQS

DQ

Delay by Half a Clock Cycle

90˚

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Figure 3–15. DQ Configuration in Stratix II or Stratix II GX IOE Note (1)

Notes to Figure 3–15 :(1) You can use the altdq megafunction to generate the DQ signals. You should, however, use Altera’s memory

controller IP Tool Bench to generate the data path for your memory interface. The signal names used here matchwith Quartus II software naming convention.

(2) The OE signal is active low, but the Quartus II software implements this as active high and automatically adds aninverter before the OE register A OE during compilation.

(3) The outclock signal for DDR, DDR2 SDRAM, and QDRII SRAM interfaces has a 90° phase-shift relationship withthe system clock. For 300-MHz RLDRAM II interfaces with EP2S60F1020C3, Altera recommends a 75° phase-shiftrelationship.

(4) The shifted DQS or DQSn signal can clock this register. Only use the DQSn signal for QDRII SRAM interfaces.(5) The shifted DQS signal must be inverted before going to the DQ IOE. The inversion is automatic if you use the

altdq megafunction to generate the DQ signals. Connect this port to the combout port in the altdqs megafunction.

(6) On the top and bottom I/O banks, the clock to this register can be an inverted register A’s clock or a separate clock(inverted or non-inverted). On the side I/O banks, you can only use the inverted register A’s clock for this port.

DQ

DFF

DQ

LATCH

ENADQ

DFF

Input Re g ister A I

Input Re g ister B ILatch C

D Q

DFF

D Q

DFF

01

D Q

DFF

TRI

DQ Pin

OE Re g ister A OE



Log ic Array

Latch

dataout_l

dataout_h

outclock (3)

datain_h

datain_l

OE

inclock (from DQS bus)

ne g _re g _out

I

(5)

(4)

(2)

(6)

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Figure 3–16. DQS Configuration in Stratix II or Stratix II GX IOE Note (1)

Notes to Figure 3–16 :(1) You can use the altdqs megafunction to generate the DQS signals. You should, however, use Altera’s memory

controller IP Tool Bench to generate the data path for your memory interface. The signal names used here matchwith Quartus II software naming convention.

(2) The OE signal is active low, but the Quartus II software implements this as active high and automatically adds aninverter before OE register A OE during compilation. In RLDRAM II and QDRII SRAM, the OE signal is alwaysdisabled.

(3) The select line can be chosen in the altdqs megafunction.(4) The datain_l and datain_h pins are usually connected to ground and V CC, respectively.(5) DQS postamble circuitry and handling is not shown in this diagram. For more information, see AN 327: Interfacing

DDR SDRAM with Stratix II Devices and AN 328: Interfacing DDR2 SDRAM with Stratix II Devices .(6) DQS logic blocks are only available with DQS and DQSn pins.

(7) You must invert this signal before it reaches the DQ IOE. This signal is automatically inverted if you use the altdq megafunction to generate the DQ signals. Connect this port to the inclock port in the altdq megafunction.

D Q

DFF

D Q

DFF

01



OE Re g ister B OE

OE Re g ister A OE

D Q

DFF

D Q

DFF

OR2

TRI DQS Pin (5)

Log ic Array

system clock

datain_l (4)

datain_h (4)

OE

(3)

combout (7)

(2)

0

1







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For interfaces to DDR SDRAM, DDR2 SDRAM, and RLDRAM II, theStratix II or Stratix II GX DDR IOE structure requires you to invert theincoming DQS signal to ensure proper data transfer. This is not requiredfor QDRII SRAM interfaces if the CQ signal is wired to the DQS pin andthe CQ# signal is wired to the DQSn pin. The altdq megafunction, by

default, adds the inverter to the inclock port when it generates DQ blocks. The megafunction also includes an option to remove the inverterfor QDRII SRAM interfaces. As shown in Figure 3–13 , the inclock signal’s rising edge clocks the A I register, inclock signal’s falling edgeclocks the B I register, and latch C I is opened when inclock is 1. In a DDRmemory read operation, the last data coincides with DQS being low. Ifyou do not invert the DQS pin, you will not get this last data as the latchdoes not open until the next rising edge of the DQS signal.

Figure 3–17 shows waveforms of the circuit shown in Figure 3–15 .

The first set of waveforms in Figure 3–17 shows the edge-alignedrelationship between the DQ and DQS signals at the Stratix II orStratix II GX device pins. The second set of waveforms in Figure 3–17 shows what happens if the shifted DQS signal is not inverted; the lastdata, D n, does not get latched into the logic array as DQS goes to tristateafter the read postamble time. The third set of waveforms in Figure 3–17 shows a proper read operation with the DQS signal inverted after the 90°shift; the last data, D n, does get latched. In this case the outputs of registerAI and latch C I, which correspond to dataout_h and dataout_l ports,are now switched because of the DQS inversion. Register A I, register B I,and latch C I refer to the nomenclature in Figure 3–15 .

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Figure 3–17. DQ Captures with Non-Inverted and Inverted Shifted DQS

DQ at the pin

DQS shiftedby 90˚

Output of register A 1(dataout_h)

Output of latch C 1(dataout_l)

Output of register B 1

DQS inverted andshifted by 90˚

Output of register A 1(dataout_h)

Output of latch C 1(dataout_l)

Output of register B 1

DQS at the pin

Shifted DQS Signal is Not Inverted

Shifted DQS Signal is Inverted

DQ & DQS Signals

Dn − 1

Dn − 2

Dn − 2

Dn − 2

Dn − 1

Dn

Dn

Dn − 3 Dn − 1

Dn − 1 Dn

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Enhancements In Stratix II and Stratix II GX Devices

PLL

When using the Stratix II and Stratix II GX top and bottom I/O banks(I/O banks 3, 4, 7, or 8) to interface with a DDR memory, at least one PLLwith two outputs is needed to generate the system clock and the writeclock. The system clock generates the DQS write signals, commands, andaddresses. The write clock is either shifted by –90° or 90° from the systemclock and is used to generate the DQ signals during writes.

For DDR and DDR2 SDRAM interfaces above 200 MHz, Altera alsorecommends a second read PLL to help ease resynchronization.

When using the Stratix II and Stratix II GX side I/O banks 1, 2, 5, or 6 tointerface with DDR SDRAM devices, two PLLs may be needed per I/O bank for best performance. Since the side I/O banks do not havededicated circuitry, one PLL captures data from the DDR SDRAM andanother PLL generates the write signals, commands, and addresses to the

DDR SDRAM device. Stratix II and Stratix II GX side I/O banks cansupport DDR SDRAM up to 150 MHz.

EnhancementsIn Stratix II andStratix II GXDevices

Stratix II and Stratix II GX external memory interfaces support differsfrom Stratix external memory interfaces support in the following ways:

■ A PLL output can now be used as the input reference clock to theDLL.

■ The shifted DQS signal can now go into the logic array.■ The DLL in Stratix II and Stratix II GX devices has more phase-shift

options than in Stratix devices. It also has the option to add phaseoffset settings.

■ Stratix II and Stratix II GX devices have DQS logic blocks with eachDQS pin that helps with fine tuning the phase shift.

■ The DQS delay settings can be routed from the DLL into the logicarray. You can also bypass the DLL and send the DQS delay settingsfrom the logic array to the DQS logic block.

■ Stratix II and Stratix II GX devices support DQSn pins.■ The DQS/DQ groups now support ×4, ×9, ×18, and ×36 bus modes.■ The DQS pins have been enhanced with the DQS postamble circuitry.

Conclusion Stratix II and Stratix II GX devices support SDR SDRAM, DDR SDRAM,DDR2 SDRAM, RLDRAM II, and QDRII SRAM external memories.Stratix II and Stratix II GX devices feature high-speed interfaces thattransfer data between external memory devices at up to 300 MHz/600Mbps. DQS phase-shift circuitry and DQS logic blocks within theStratix II and Stratix II GX devices allow you to fine-tune the phase shiftsfor the input clocks or strobes to properly align clock edges as needed tocapture data.

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ReferencedDocuments

This chapter references the following documents:

■ AN 325: Interfacing RLDRAM II with Stratix II & Stratix GX Devices■ AN 326: Interfacing QDRII & QDRII+ SRAM with Stratix II, Stratix, &

Stratix GX Devices■

AN 327: Interfacing DDR SDRAM with Stratix II Devices■ AN 328: Interfacing DDR2 SDRAM with Stratix II Devices■ DC & Switching Characteristics of Stratix III Devices chapter in

volume 2 of the Stratix III Device Handbook

DocumentRevision History

Table 3–11 shows the revision history for this chapter.

Table 3–11. Document Revision History

Date andDocument

VersionChanges Made Summary of Changes

January 2008,v4.5

Added the “Referenced Documents” section. —

Minor text edits.

No change For the Stratix II GX Device Handbook only:Formerly chapter 8. The chapter number changeddue to the addition of the Stratix II GX Dynamic Reconfiguration chapter. No content change.

—

May 2007,v4.4

Updated the “Phase Offset Control” section. —

Updated Figure 3–2 . —

Updated Table 3–1 . —

Added Table 3–4 and Table 3–6 . —

Updated Note (1) to Figure 3–10 . —

February 2007v4.3

Added the “Document Revision History” section tothis chapter.

—

April 2006, v4.2 Chapter updated as part of the Stratix II Device Handbook update.

—

No change Formerly chapter 7. Chapter number change onlydue to chapter addition to Section I inFebruary 2006; no content change.

—

December 2005v4.1

Chapter updated as part of the Stratix II Device Handbook update.

—

October 2005v4.0

Added chapter to the Stratix II GX Device Handbook .

—
















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Document Revision History