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T-Mobile’s Wi-Fi / Cell phone T-mobile just announced a new
phone that can operate normally as a cell phone, but when it’s near a “T-mobile wireless hotspot” (you could own at home), it switches
to Wi-Fi & calls are FREE. Yes, FREE.
Computer Organization and Design
Lecture 18 – CPU Design: Designing a Single-cycle CPU
theonlyphoneyouneed.com
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Five Components of a Computer
Processor
Computer
Control
Datapath
Memory(passive)
(where programs, data live whenrunning)
Devices
Input
Output
Keyboard, Mouse
Display, Printer
Disk (where programs, data live when not running)
Datapath Summary• 为了执行指令,我们需要基于数据变换的
数据通道 datapath
• 控制器 controller 使得变换正确地进行P
C
inst
ruct
ion
me
mor
y
+4
rtrs
rd
regi
ste
rs
ALU
Da
tam
em
ory
imm
Controller
opcode, funct
CPU clocking (1/2)
• 单周期 CPU: 指令的所有阶段在一个长的时钟周期中完成 .
• The clock cycle is made sufficient long to allow each instruction to complete all stages without interruption and within one cycle.
对每个指令 , 如何控制数据通道中信息的流动 ?
1. InstructionFetch
2. Decode/ Register
Read
3. Execute 4. Memory5. Reg. Write
Outline of Today’s Lecture
• Design a processor: step-by-step• 指令集的要求• 满足指令集要求的硬件器件• 详细讨论部分数据通道
How to Design a Processor: step-by-step1. 分析指令集结构 (ISA) 数据通道需求
• 每个指令的含义由寄存器变换给定• 数据通道必须包含用于 ISA 寄存器的存储单元• 数据通道必须支持每个寄存器的变换
2. 选择数据通道组件并建立时钟规则3. 组装数据通道以满足需要4. 分析每个指令的实现以确定影响寄存器变换的
控制点设置 .5. 组装控制逻辑
Review: The MIPS Instruction Formats• All MIPS instructions are 32 bits long. 3 formats:
• R-type
• I-type
• J-type
• The different fields are:• op: operation (“opcode”) of the instruction• rs, rt, rd: the source and destination register specifiers• shamt: shift amount• funct: selects the variant of the operation in the “op”
field• address / immediate: address offset or immediate value• target address: target address of jump instruction
op target address
02631
6 bits 26 bits
op rs rt rd shamt funct
061116212631
6 bits 6 bits5 bits5 bits5 bits5 bits
op rs rt address/immediate
016212631
6 bits 16 bits5 bits5 bits
Step 1a: The MIPS-lite Subset for today
• ADDU and SUBU•addu rd,rs,rt•subu rd,rs,rt
• OR Immediate:•ori rt,rs,imm16
• LOAD and STORE Word•lw rt,rs,imm16•sw rt,rs,imm16
• BRANCH:•beq rs,rt,imm16
op rs rt rd shamt funct
061116212631
6 bits 6 bits5 bits5 bits5 bits5 bits
op rs rt immediate
016212631
6 bits 16 bits5 bits5 bits
op rs rt immediate
016212631
6 bits 16 bits5 bits5 bits
op rs rt immediate
016212631
6 bits 16 bits5 bits5 bits
寄存器变换语言 Register Transfer Language• RTL 给出指令的含义
• 所有的指令都从取指开始
{op , rs , rt , rd , shamt , funct} MEM[ PC ]
{op , rs , rt , Imm16} MEM[ PC ]
inst Register Transfers
ADDU R[rd] R[rs] + R[rt]; PC PC + 4
SUBU R[rd] R[rs] – R[rt]; PC PC + 4
ORI R[rt] R[rs] | zero_ext(Imm16); PC PC + 4
LOAD R[rt] MEM[ R[rs] + sign_ext(Imm16)]; PC PC + 4
STORE MEM[ R[rs] + sign_ext(Imm16) ] R[rt]; PC PC + 4
BEQ if ( R[rs] == R[rt] ) then PC PC + 4 + (sign_ext(Imm16) || 00) else PC PC + 4
Step 1: Requirements of the Instruction Set• 内存 (MEM)
• instructions & data (will use one for each)• Registers (R: 32 x 32)
• read RS• read RT• Write RT or RD
• PC• Extender (sign/zero extend)• Add/Sub/OR unit for operation on register(s) or extended immediate
• Add 4 or extended immediate to PC• Compare registers?
Step 2: Components of the Datapath•Combinational Elements
•Storage Elements• Clocking methodology
Combinational Logic Elements (Building Blocks)
•Adder
•MUX
•ALU
32
32
A
B32
Sum
CarryOut
32
32
A
B32
Result
OP
32A
B32
Y32
Select
Ad
der
MU
XA
LU
CarryIn
ALU Needs for MIPS-lite + Rest of MIPS• Addition, subtraction, logical OR, ==:
ADDU R[rd] = R[rs] + R[rt]; ...
SUBU R[rd] = R[rs] – R[rt]; ...
ORI R[rt] = R[rs] | zero_ext(Imm16)...
BEQ if ( R[rs] == R[rt] )...
• Test to see if output == 0 for any ALU operation gives == test. How?
• 书上还有加法和 SLT (1 if A < B, 0 其他情况 )
• ALU follows chap 5
Storage Element: Idealized Memory
• 内存 ( 理想化 )• 一个输入总线 : Data In• 一个输出总线 : Data Out
• 内存字的选择 :• 地址选择何字放在 Data Out 上• Write Enable = 1: 选择相应的内存地址字通过 Data In 写入总线
• 时钟输入 Clock input (CLK) • CLK 仅仅是写入操作时起作用• 在读入操作时是组合逻辑 :
Address valid Data Out valid after “access time.”
Clk
Data In
Write Enable
32 32DataOut
Address
Storage Element: Register (Building Block)
• Similar to D Flip Flop except N-bit input and output Write Enable input
• Write Enable: negated (or deasserted) (0):
Data Out will not change asserted (1):
Data Out will become Data In on positive edge of clock
clk
Data In
Write Enable
N N
Data Out
Storage Element: Register File• Register File consists of 32 registers:
• Two 32-bit output busses: busA and busB• One 32-bit input bus: busW
• Register is selected by:• RA (number) selects the register to put on busA (data)• RB (number) selects the register to put on busB (data)• RW (number) selects the register to be written
via busW (data) when Write Enable is 1• Clock input (clk)
• The clk input is a factor ONLY during write operation• During read operation, behaves as a combinational
logic block: RA or RB valid busA or busB valid after “access time.”
Clk
busW
Write Enable
3232
busA
32busB
5 5 5RWRA RB
32 32-bitRegisters
Step 3: Assemble DataPath meeting requirements
• Register Transfer Requirements Datapath Assembly
• Instruction Fetch
• Read Operands and Execute Operation
3a: Overview of the Instruction Fetch Unit
• The common RTL operations• Fetch the Instruction: mem[PC]• Update the program counter:
Sequential Code: PC PC + 4 Branch and Jump: PC “something else”
32
Instruction WordAddress
InstructionMemory
PCclk
Next AddressLogic
3b: Add & Subtract• R[rd] = R[rs] op R[rt] Ex.: addU rd,rs,rt
• Ra, Rb, and Rw come from instruction’s Rs, Rt, and Rd fields
• ALUctr and RegWr: control logic after decoding the instruction
32Result
ALUctr
clk
busW
RegWr
32
32
busA
32
busB
5 5 5
Rw Ra Rb
32 32-bitRegisters
Rs RtRd
AL
U
op rs rt rd shamt funct061116212631
6 bits 6 bits5 bits5 bits5 bits5 bits
Already defined the register file & ALU
Peer Instruction
A. Our ALU is a synchronous device
B. We should use the main ALU to compute PC=PC+4
C. The ALU is inactive for memory reads or writes.
ABC1: FFF2: FFT3: FTF4: FTT5: TFF6: TFT7: TTF8: TTT
How to Design a Processor: step-by-step• 1. Analyze instruction set architecture (ISA)
datapath requirements• meaning of each instruction is given by the register transfers
• datapath must include storage element for ISA registers
• datapath must support each register transfer• 2. Select set of datapath components and establish clocking methodology
• 3. Assemble datapath meeting requirements• 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer.
• 5. Assemble the control logic (hard part!)