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FPGA Based Fine Resolution Flash TDC(Time to digital convertior)
with
two stage interpolation
- h!am "!er-#$%&D''
-*+ternal Pro,ect at BARC(& " division)-"nternal guide P.
/a!a0rishnan
-*+ternal guide-Dr &. Chandratre
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Contents• "ntroduction• iterature urve!• 12,ective• Flash TDC•
Carr! chains• "nterpolation principles• 3utts "nterpolator• $ phase
cloc0 generation• TDC architecture• Re4erences
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"ntroduction(#5 )• A TDC or Time to Digital convertor is an
electronic circuit which
converts time interval between two events to digital form .
• 6ow is it di7erent 4rom a 2asic digital counter8
• A digital counter9s resolution is limited m! the time period
o4 thecloc0. But a TDC is independent o4 cloc0 period and
providesmuch :ner resolution;however the! lac0 in range.
• "n realit!; 2oth counter and TDC wor0 together to
provideaccurate time duration(0nown as interpolation).
• A ash TDC uses dela! chain to calculate time interval and
has
neglegible conversion time.
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"ntroduction( 5 )• "mplentation in FPGA provides shoter design
cycle
and less expensive design over A "Cimplementation.
• 6owever; the resolution will 2e much less than that o4 TDC
2ased on A "C technolog!.
• Interpolation techniques are used to provide
better accuracy within a given range.
• Nutts Interploator is the most popularl! usedinterpolator
techni
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=h! FPGA8• onger design c!cles 4or A "C 2ased
design.
• ower design cost.
•
%ore predicta2le design c!cle.• 6ard timing anal!sis not re
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iterature urve!(#5 )• "n # >; ?alis@ et al. # an FPGA 2ased
approach;their
design used a variation o4 conventional dela! line ando7ered a
time resolution o4 '' ps.
•
"n ''' ; a rapid progress in electronics technol0og!allowed them
to achieve a time resolution o4 #'' ps
• Resolution values 2etween ' ps to '' ps were achievedusing
dedicated dela! chain techin
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iterature urve!( 5 )• "n ''E; A Aloisio et al. use di7erential
tapped
dela! line to improve resolution upto ' ps.
•
presented another FPGA 2ased high presicionshort time interval
meausrement s!stem.
• > used two stage interpolation to improve the
accurac! o4 the time measurement.• E used two phas cloc0 and
dual edge two stage
interpolation 4or 4pga implementation.
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=or0ing o4 Flash TDC
D I
IJ
D I
IJ
D I
IJ
D I
IJ
t ttt
TAR T
T1P
#t
I# I I I$# '' '
Dela! chain
#
#t
#
#t
#
#t
1utput in thermometer code5unar! code
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Challenges in FPGA implementation
• Routing 2etween logic elements 2ecomesunpredicta2le to the
user;due tooptimi@ation algorithm used 2! the so4tware.
• This might add larger interconnect dela!2etween the dela!
2loc0 which a7ects theresolution o4 the output.
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olution8• Kse o4 dedicated Carr! chains o4 the
FPGA 2oard.• These carr! chains are designed 2!
the vendors 4or general purposeapplication.
• These chain structures provide shortpre de:ned routes 2etween
identicallogic elements.
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"nterpolation(#5 )• To o2tain high resolution and a wide
measurment range with accurac! theadvanced time interpolation
techni
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"nterpolation( 5 )
• "nterpolation uses 4our phase cloc0 (FPC)that is cloc0 shi4ted
2! '; ';#E'; >'degrees
• The two-stage interpolation method involves the decomposition
o4 the measuredtime interval T into :ve partsH 3TC; TA#; TA ;
TB#;
• The product 3TC consists o4 an integer num2er 3 o4 such cloc0
periods TC; whose
leading pulse edges appear 2etween the leading edges o4 the TART
and T1Ppulses.
• The num2er 3 is counted 2! the 2inar! counter; commonl! called
the maincounter.
• The time interval 2etween the TART pulse edge and the nearest
cloc0 edge issimultaneousl! measured 2! two interpolator stages in
the TART channel.
• "n the F" ; when a TART signal appears; the nearest FPC edge
is detected. incethe widths o4 the FPC time segments are 0nown 4rom
cali2ration; the time TA# can2e calculated accuratel!.
• "n the " ; the time interval TA 2etween the TART edge and the
nearest FPC edgeis measured.
• imilar operations are 4ollowed 4or stop interpolator
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Timing diagram o4 Two stageinterpolation.
TART
T1P
C 1C?
FPC
Find the nearest FPC edge 4rom the TART pulse
%easure TA# 2etween nearest FP edge and cloc0
TA#
%easure TA 2etween nearest FP edge and start
TA 3tc TB TB#
%easure TB 2etween nearest FP edge and start%easure 3tc using
counter%easure TB# 2etween nearest FP edge and cloc0
TO3tc TA# TA Q(TB# TB )
'' #E' >'
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3utt9s interpolator• Consist o4 $ Nip Nops7#;7 ;7 ;7$
• F4# is triggered 2! the startpulse
• 7 ;7 is a two 2it shi4tregister; usedto :nd nearest cloc0 edge
orsecond cloc0 *dge.(during thistime :ne counter is on)
• F4$ is used to trigger thecoarse counter as an whenthe nearest
cloc0 edge is4ound.
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Cloc0 generation on the4pga chip
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TDC convertor architecture
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Phases o4 the Pro,ect
hasestages
!b"ective #T$Design%&ynt
hesis.
&imulation
Testing
# ingle phasedualinterpolationtdc
Done &eri:ed -
Two phase dualinterpolationtdc
Done "nprogress.
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Four phase dual
interpolationtdc
Done - -
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Re4erences(#5 )• # ?alis@ / # > Review o4 methods 4or time
interval
measurements with picosecond resolution %etrologia $# Q#
• /ansson /; %ant!niemi A and ?ostamovaara / ''' C%1
time-to-digital converter with 2etter than #' ps
single-shotprecision "*** /. olid tate Circuits $# # E Q
• 6wang C; Chen P and Tsao 6 ''$ A high-precision
time-to-digital converter using a two-level conversion scheme
"***
Trans. 3ucl. ci. # # $ Q
• $ Tisa ; otito A; Giudice A and Sappa F ''
%onolithictime-to-digital converter with ' ps resolution Proc. "***
"nt.
!mp. Circuits and !stems; " CA vol # pp # Q
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Re4erences( 5 )• R @plet et al;MA $ ps time digiti@er with a
two-phase
cloc0 and dual-edge two-stage interpolation in a
:eldprogramma2le gate arra! device L
• @plet R; ?alis@ / and @!manows0i R '''
"nterpolating time counter with #'' ps resolution on asingle
FPGA device "*** Trans. "nstrum. %eas $ E> QE• > Sielins0i %;
Cha2ers0i D and Gr@ela0 '' Time-
interval measuring modules with a short deadtime%etrol. %eas.
!st. #' $#Q #
• E ie D; Shang I; Ii G and u D '' Cascading dela!line
time-to-digital converter with > ps resolution and areduced
num2er o4 dela! cells Rev. ci. "nstrum.
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T6A3? U1K
