TFT(Thin Film Transistor) LCD II

Hanyang Univer sity Integrat ed Electronics Lab oratory

O. K. Kwon Nov. 2000

TFT(Thin Film Transistor) LCD II



Contents

• TFT-LCD Overview– Structure of TFT-LCD Panel (Back Light System, Polarizer, Color Filter)– Pixel Structure– TFT Fabrication– TFT-LCD Driver (Data & Gate Driver) and Interface System

• Issues and Technologies of TFT-LCD– High Gray Scale– Low Power Consumption– High Aperture Ratio– Wide Viewing Angle– Large Size Display



Gray Scale Generation

• Various gray scale generation Methods– Decoder-Based DAC

– Resistor-String DAC

– Capacitor DAC• Weighted Capacitance Type DAC

• Split Weighted Capacitance Type DAC

• C-2C Type DAC

– Ramp Method

– Dithering Method

– FRC(Frame Rate Control)

– Shindou Method



Digital Data Driver _Decoder Based DAC

• DAC Using Decoder• Pros

– Clear and fast operation– Relatively simple circuit

• Cons– As many external voltage

sources and analog switches as gray scales

– Many voltage source : High system costs

– Many analog switches : Large area

– Impractical for high gray scale

Decoder

3bit data

V1V3V5V7

V0V2V4V6

3-to-8 decoder based DAC

Pass gatearray



Digital Data Driver_Resistor String DAC

• 8 bit Resistor String DAC– External voltage sources– 8-resistor string between

neighboring voltage sources• 256 analog voltage levels

• Pros– Less voltage sources than decoder-

only type– More accurate than capacitor DAC

• Cons– Static currents– Difficult to implement accurate

resistance– Area increase with gray scale

VREF1VREF2

VREF(N-1)VREF(N)

OUT

D0 D1 D2 D3 D4 D5 D6 D7

ReferenceGenerator ROM Type Decoder

8-bit resistor string DAC



Digital Data Driver_Capacitor DAC

• Capacitor DAC – Analog voltage generation controlling charge sharing between capacitors– Binary weighted capacitor

• Pros– No static current– Less external voltages (1 or 2)– Easier to control thermal oxide thickness Uniform capacitors

C 2C 4C 8CC 2C 4C 8C

16/15C

CReset

VREF1

VREF2

Vout

• Cons– Large area : DAC unit at every line– Variable data line capacitance

• When OP-AMP not used– Less accurate than R-DAC



Digital Data Driver_C-2C DAC

• 8-bit D/A Converter with -correction– Reference voltages can be adjusted to the LCD’s non-linear V-T

characteristics • Small area of DAC compared with weighted capacitor type• Power consumption is reduced

VO

Vr-

Vr+

C C C C C C

2C 2C 2C 2C

D0 D1 D2 D3 D4

Vr-Vr+

—D7—D6—D5

Reference voltages

Reference voltage selector(upper 3-bit decoder) 5-bit C-2C DAC



Digital Data Driver_Ramp method

• DAC Using Ramp Signal : 6Bit• Structure

– Shift register, Input register, Storage register, Counter, Analog switch

– Externally supplied ramp signal• Operation

– When a counter counts up to 111111, it turns-off the analog switch.

– If an input data is 111111, the analog switch is turned-off as soon as the data is loaded

– If an input data is 000000, the analog switch keeps being turned-on until the counter counts from 000000 to 111111.

– The counter determines when to turn-off the switch

Data Inputregister

5-bitcounter

LoadClock

Externalramp

Externalramp

Counter Output

DAC Output

Data= 000010

Data= 111101



Digital Data Driver_Ramp method

1 2 3 4 50

V(volt)20

40

60

80

100

T(%)V7

V6

V5

V4

V3

V2

V1

V0

V-T nonlinearity compensation using ramp signalV-T characteristics of LC

000 001 010 011 100 101 110 111

Time

ExternalRamp

CounterOutput

V1

V2

V3V3

V3

V2

V1

• Cons– Complex circuitry ( 6bit counter at every data line )– Ramp signal distortion due to RC delay and noise

• Pros – -correction by control of voltage step V1, V2 , V3 (See below)– No resistor, capacitor or amplifier Better uniformity



Digital Data Driver_Dither method

• Principles – V4 represents 12th gray, V5 represents 16th

gray– Group 4 pixels as a unit– 4 pixels select 12th gray, 12th gray on average– 3 pixels select 12th gray, 13th gray on average– 2 pixels select 12th gray, 14th gray on average– 1 pixel select 12th gray, 15th gray on average– All pixels select 16th gray, 16th gray on average

Brig

htne

ss(g

ray

scal

e)

Driving voltage

by 8-voltage levelsby Dither-method

V1 V2 V3 V4 V5 V6 V7 V8

16th

12th

12 12 16

12 12

12th

12

12 12

13th

16 12

12

14th

16

16

12

15th

16

16 16

16th

16

16

16

Gray Scale Interpolation using Dither-MethodDriving Voltage and Gray Scale

• Cons– Reduced resolution



Digital Data Driver_Frame Rate Control

• Frame Rate Control - Temporal average

Gray Scale Using FRCFrameGray-Scale

White

Black

High-LevelGray-scale

Low-LevelGray-scale

V0 V0 V0 V0

V0 V0

V0V0

V1 V1

V1V1

V2 V2

V2V2

1 2 3 4

4-level V-T characteristics

1

10

V0 V1 V2

a

b

c

d

Voltage(rms)

Tran

smitt

ance

(arb

.uni

t)

V02

+ V1212

V02

+ V2212

V12

+ V221

2

• Cons– Should increase to prevent flicker– High speed addressing required unsuitable for high gray scale

• Principle– V0, V1 alternation :

– V0, V2 alternation :

22 1021 VVrms

22 2021 VVrms



Digital Data Driver_Shindou method[1/2]

• Principle– Alternation of Vi, Vj of which duty ratio is m:n– Average voltage transferred to pixel – Controlling m and n : interpolation between Vi and Vj

• Theoretical Background– An periodic function f(x) can be expressed in Fourier series

– Data line and pixel act as a low pass filter – Harmonics are suppressed and DC (average value) component are

transferred to pixel

1

0 )sincos(2

)(n

nn nxbnxaaxf

.) . . . 1,2,3,(n ,cos)(1 nxdxxfan

.) . . . 1,2,3,(n ,sin)(1 nxdxxfbn

nmnVmV

V jiaverage

m nVi

Vj



Digital Data Driver_Shindou method[2/2]

• Operation– SC selects neighboring two voltage sources according to higher 3bits D5,

D6, D7.– ISG generates 32 kinds of pulse T whose duty ratios are 31:1~0:32 using

TMs according to lower 5bits D0, D1, D2, D3, D4, D5.– The selected two voltage levels are interpolated by the generated pulse T

D0D1D2

D3D4

D5

D6D7

SCC

S0S32S64S96

S128S160

S192

S224

S256

TM4

TM3

TM2

TM1

TN0

V256

V224

V192

V160

V128

V96

V64

V32

V0

ASW0

ASW32ASW64

ASW96

ASW128ASW160

ASW192

ASW224ASW256

OUT

D8

D0D1D2

D3D4

D5

D6D7

SC

S0S32S64S96

S128S160

S192

S224

S256

TM4

TM3

TM2

TM1

TN0

D0D1D2

D3D4

D5

D6D7

S0S32S64S96

S128S160

S192

S224

S256

IS

ISG

T

TM4

TM3

TM2

TM1

TM0T

2T

4T

8T

16T

Output Stage Using Shindou Method Structure of SCC Waveforms of TMs



Issues and Technologies for High Gray Scale

• Issues Vp compensation

• Capacitor coupling structure Vp compensation structure

– Random offset of the output buffer• Offset compensation structure

– Area Increases of the DAC• Compact DAC data driver (SID ’00)

• New Driving Method for 8bit gray scale is needed



Vp problems

Vp problem(Gate Voltage Feedthrough)

VP

VGn

VD

VP

VP

VP

CS

CLC

CGD

VGn

VGn-1

VD

LCSGP

GPGP CCC

CVV



Vp problems

• What troubles in Vp ?

• To reduce Vp– Pixel design optimization

Vp compensation circuit too complex

– Novel methods are needed.

Uneven parasitic capacitance in all pixels

Uneven Vp in all pixelsAsymmetric charging characteristic

Degradation of gray scale

1

1

GSSTGLC

GGSP CCC

VCV



Vp Compensation Driving

• LC voltage at the end of selection

CLC CST

Row n-1

Vg,n-1

CGS

Row n

Vg,n

Column

Vg,n-1

Vg,n

Tr

t

tVcomp

oncompensatifor ST

GSgcomp

STLCGS

STcomp

SLCGS

GSgcolLC C

CVVCCC

CVCCC

CVVV



Random offset of the output buffer

• Random Offset

Process variations between channel-to-channel, chip-to-chip, wafer-to-wafer

With Offset Cancellation Technique

Without Offset Cancellation Technique

Decrease of Yield

Difficult



• Why Difficult ?

– Different loads of OP-AMP• Calibration mode < 1pF• Driving mode > 100pF

– Difficult to design OP-AMP • Solutions

– OP-AMP with internal offset calibration– External offset calibration technique– Driving methods insensitive to offset voltage

Random offset of the output buffer

Vin

SW1

SW2

SW3C

VosOP-AMP

TFT-LCD Panel Loads

Driver

loads < 1pF loads > 100pF

Common Offset Cancellation Circuit



Area Increases of the DAC

• DAC– Resistor String DAC – Capacitor DAC etc.

V00

V01

V02

V03

V04

V251

V252

V253

V254

V255

V0

V8

R00

R01

R02

R03

R04

R252

R253

R254

R255

ResistorString

Vout

Rom Type Decoder

D0 D1 D2 D3 D4 D5 D6 D7

8-bit DAC Area

10-bit DAC Area

8-bit DAC

4 times larger

• Solutions - New DAC schemes

1-bit increase

doubled DAC area (in resistor string DAC)



Digital Data Driver_Area-efficient driver [1/2]

Compact(Area Efficient) LCD Driver

DRVOUT<384>

AnalogSampleCircuit

AnalogHold

Circuit

Buffer

AnalogSampleCircuit

AnalogHold

Circuit

Buffer

AnalogSampleCircuit

AnalogHold

Circuit

Buffer

AnalogSampleCircuit

AnalogHold

Circuit

Buffer

AnalogSampleCircuit

AnalogHold

Circuit

Buffer

AnalogSampleCircuit

AnalogHold

Circuit

Buffer

Control Logic

6-BitDAC

(6 Stage)

AnalogSampleCircuit

AnalogHold

Circuit

Buffer

Data

Vgamma

36

8

DRVOUT<1>

DRVOUT<2>

DRVOUT<3>

DRVOUT<4>

DRVOUT<383>

• Operation– Once the data are converted to parallel, they are fed into six DACs– The result is six analog voltages, which are multiplexed onto sample and hold

cells, one for each output



Digital Data Driver_Area efficient driver [2/2]

• Pros– Area-efficient

• 6bit * 384 DACs are needed for conventional data driver• 6bit * 6 DACs + 384 sample and hold circuits for compact driver

– Low power consumption because of the reduced static currents of DACs

• Cons– Sample and hold circuits errors are included (inapplicable to high gray scale)



Low Power Consumption

• OverviewImprovement of transmission rate of panel

Improvement of light utilization rate Excellent-efficiency

power supply circuit

Reduction of panel load driving power

Low voltage drive circuits

• Improvement of panel aperture ratio• High transmission rate color filters, polarizers

Backlight Unit 60%

Circuit Unit 40%

• Efficiency improvement of light guides• Improvement of light emission efficiency of CCFT

• Panel load capacity reduction• Energy recovery driving• Reduced frame rate

• 5V 3.3V

• Efficiency improvement of

DC/DC converter



Power Breakdown of Data Driver

Black Black and WhiteVertical Stripe

PolarityInversion Line/Dot Column Line/Dot Column

Analog DCPower

(VDDa=10V)145mW 145mW 145mW 145mW

DigitalPower

(VDDd=2.5V)5mW 5mW 15mW 15mW

InterfaceBus Power 14mW 14mW 21mW 21mW

Panel ACPower 275mW 0.52mW 139mW 0.34mW

Total 439mW 164mW 320mW 181mW

Panel AC Power

Analog DC Power

Interface Bus Power

Digital Power

Power Consumption

(12.1 inch SVGA ,SID ’97)



Low Power Driving(AC Power Reduction)

• Equation of the Panel AC Power Consumption

• Two approaches to reduce AC power

AVEDDAC IVP

2ROW

SWINGLSDDFVCNV

Reduce FROW Reduce VSWING

•MFD(Multi-Field Driving) •Charge Sharing

•Triple Charge Sharing

•Stepwise Source Driving

•RLC Resonant Method



Low Power Driving - Multi-Field Driving [1/3]

• Background – Total power consumption (TPC) = Static power consumption (SPC)

+Dynamic Power Consumption (DPC)– DPC is 70% of TPC, so refresh rate must be slow down for TPC

reduction, because DPC is directly proportional to refresh rate– Slower refresh rate causes more visible flicker! Multi-Field DrivingField

12

34

56

7

123

• Multi-Field Driving Method– Divide 1 frame into 3 sub-field– The polarity of adjacent field is

opposite– In spite of reduced refresh rate, Flicker

frequency remains at the same level due to averaging effect




• Flicker Compensation– In the case that refresh rate is reduced from 60Hz to 20Hz– Flicker frequency for each line : 2TS (three times longer than original one)– Flickers for adjacent three lines occur at different phase– Average flicker frequency for three serial lines : 2/3 TS

In spite of reducing refresh rate into 1/3 of original one, flicker frequency remains at the same level

(a) Flicker for one line (b) Flicker for adjacent three lines (C) Average flicker for adjacent three lines

i(t)

VS

2nTs (2n+1)Ts (2n+2)Ts t

VS

TsVS

Ts23

t t

i(t) ia(t)VP VN

(a) (b) (c)




• Power Consumption Reduction

• Pros. - power saving efficiency > 50%

• Cons. - Inapplicable to moving image

- extra frame memory

- complex

100

50

Pow

er(%

)

1 3 5 11 13

55

3419 18 16

557

15

45

Interlaced Subfield Images

Dynamic Power ConsumptionStatic Power Consumption



Low Power Driving - Charge Sharing [1/2]

• Operation – Now Mth row was driven and (M+1)th row is about to be driven– Neighboring data lines store video signals of opposite polarities– Shortly before driving Mth row, every switch is disconnected from output buffer and

connected to CL

– Every data line has medium voltage level due to charge sharing– Signal CR controls the switches

Architecture

Conventional Data Driver

1 2 3 N-1 N4

Panel

CR

CL

RL

CL

RL

CL

RL

CL

RL

CL

RL

CL

RL

AMP

CR

Vcom

#M row line time

GND

VDD

Vswing

Gray ScaleDecision time

#M+1 row line time

VL

VH


Positive VideoSignals

NegativeVideoSignals

ChargeSharing time

ChargeSharing time

ChargeSharing time

12

Waveform and timing diagram



Low Power Driving - Charge Sharing [2/2]

• Power Consumption Analysis– Vpos voltage level of video signal

of positive polarity– Vneg voltage level of video signal

of negative polarity

– Half of Vswing is supplied by charge sharing and only the other half comes from the external source

AC

ROWswingLDDSharingeargCh

P

]FVCN[VP

21

221

0.4 0.6 0.8 1.00

10

20

30

40

50

0.1 s

Pow

er S

avin

g Ef

ficie

ncy

[%]

charge time [ s]

0.2 s 0.3 s 0.4 s 0.5 s

• Pros. - applicable to moving image - no degradation of image quality - very simple - power saving efficiency < 50% •Cons. - power saving efficiency < 50%



Low Power Driving - Triple Charge Sharing [1/3]

Architecture Waveform and Timing Diagram

Conventional Data DriverCEXT

SEL1

SEL2

SEL3

CL

New Driver

Panel

CL CL CL CL

RL RL RL RL RL

1 2 3 N-1 N

AMP

GND

VL

SEL1

SEL2

SEL3

Vcom

#M row line timeTriplecharge sharing

Triplecharge sharing

VDD

Vswing

Vswing13


#M+1 row line time

VH








• Convergence of the voltage of CEXT

VL

VH

500 1000 1500 2000time [ X row line time ]

VEXTVSWING

3

VDD

GND

VSWING

LEXT CNC If

after thousands of row line time

SWINGLEXT VVV31




Vswing

13Vswing

SEL1

SEL2

SEL3

Vcom

#M row line timeTriplecharge sharing


GND

VDD


#M+1 row line time

VL

VH





AMP

Power consumed in Gray Scale Decision Time :

Conventional Data DriverCEXT

SEL1

SEL2

SEL3

CL

New Driver

Panel

CL CL CL CL

RL RL RL RL RL

1 2 3 N-1 N

AMP

ACSHARING_CHARGE_TRIPLE PP31

• Pros. - applicable to moving image - no degradation of image quality - simple - power saving efficiency < 66.6%

• Cons. - row line time extension method is needed



Low Power Driving - Stepwise Source Driving [1/3]

1H 2H 3HVDD (10V)

VCOM (5V)

GND

positive video

negative video

fully supplied by amplifier (VDD)

1H 2H 3HVDD (10V)

VCOM (5V)

GND

positive video

negative video

VH

VL

5.5V

A

B

C

D

Conventional Source Driving Stepwise Source Driving

Power supply amplifier

Power supply

Voltage swing

Polaritymodulator VL

Polaritymodulator VH

amplifier amplifier

A B C D




• Schematic Diagram

AMP_H AMP_L AMP_H AMP_L AMP_H AMP_L AMP_H AMP_L

MUX_B

MUX_A MUX_A MUX_A MUX_A MUX_A MUX_AMUX_A

MUX_B MUX_B MUX_B MUX_B MUX_B MUX_B

PMOdd

PMEven

EO

CON

PIXEL

VH

VL

CLOAD

7.75V

2.25V

3.35V

4.45V

5.55V

6.65V

CT1

CT2

CT3

CT4

SW0

SW1

SW2

SW3

SW4

SW5

Architecture of DriverPolarity Modulator




• Pros. - applicable to moving

image - no degradation of

image quality - power saving

efficiency < 84.5%

• Cons. - row line time

extension method is needed - voltage overcharging

1H 2H

polaitymodulation

gray scaledecision

polaitymodulation

gray scaledecision

black

black

blackVL

VDD

VH

1H 2H

polaitymodulation

gray scaledecision

polaitymodulation

gray scaledecision

white

VL

VH

whitewhite

Waveform in All-Black image

Waveform in All-White image



Low Power Gate Driving_RLC Resonant Method [1/2]

• Operation– RLC resonant operation

whose oscillation is interrupted after half oscillation

– Oscillation sensing circuitry sense the ON-resistance of the switch

CL

LVS/2

Schematic View of Driving CircuitrySimplified Structure



Low Power Gate Driving_RLC Resonant Method [2/2]

• Operation time range– Charging (discharging) time

is divided into two oscillation time and two charge sharing time

• Power dissipation

• Applicable to gate and data driver of LCD

fNCVVP

LNCtNLC

VV

pixLOSTSrlcR

pixSWING

pixSLOST

4

Timing diagram



Low Analog DC Power_Class-B Buffer

• Operation– Nonlinear circuits are included (inverter and comparator)– Output NMOS and PMOS are

turned on by series-shunt feedback of input/output voltage

• Pros– Low static current

• Cons– Sensitive to the offset voltage

of comparators

VDD

VSS

VinVout

Vos1

Vos2

Cmp1

Cmp2

Block diagram of class-B output buffer



High Aperture Ratio

• Aperture ratio decreases as pixel pitch shrinks

• Use of Black matrix– Prevent light transmittance

through a pixel surrounding area

• High aperture ratio structure– Shield CS(storage capacitor)

structure– ITO Shield Plane structure

Aperture of a Single Pixel

Black matrix

TFT

Storage Capacitance

ApertureArea

Gate Line

Data Line



High Aperture Ratio

• Shield-CS structure– Shield-CS pattern(electro-static layer) functions as a common

electrode of a storage capacitance– Coupling capacitance between the signal line and the pixel electrode

can be reduced– This permits close layout between signal electrode and the pixel

electrode

• ITO-shield plane structure– Transparent electrode is placed between the signal line and the pixel

electrode– This electrode works as a ground plane and shields capacitive

coupling – Transverse electric field is reduced due to the same reason as the

shield CS



High Aperture Ratio

Alginment margin

Aperture Area

Signal Line

Alginment margin

Aperture Area

Signal Line

Shield Cs

Signal Line

Pixel Electrode

Liquid Crystal

Insulator

Shield and storage capacitance

electrode

ConventionalStructure

Shield -CS

ITO ShieldPlane

Black Matrix

No Black Matrix



High Aperture RatioBlack matrix

Conventional Structure Shield -CS ITO Shield PlaneAperture area

CS

50 ~ 70% 70 ~ 80% 80 ~ 90%



Wide Viewing Angle

• Conventional TN Structure– Anisotropic Structure of

LC molcule– Imperfect light control (Use of Polarizer)– Viewing angle

dependence is intrinsic problem of LCD

– Gray scale inversion occurrs

Viewing Angle90°(H), 40°(V) Aperture Ratio 50~70%



Wide Viewing Angle

• Vertical Alignment Mode

• Advantages– Wide viewing angle without

gray scale inversion– High contrast ratio(~300:1)– Fast response time(~25ms)

• Disadvantages– Material Limitation(LC)– Use of compensation film– Adoption of multi-domain

technology– Complicate LC process– Unstable alignment to

mechanical shock

Viewing Angle140°(H), 120°(V)

Aperture Ratio > 80%



Wide Viewing Angle

• In-Plane Switchig• Advantages

– Wide viewing angle without gray scale inversion

– Low flicker level(Unvisible)

– Low cost• Disadvantages

– Slow response time(>45ms)

– Low transmittance(<4%)– Crosstalk– High driving voltage Viewing Angle

160°(H), 160°(V) Aperture Ratio< 40%



Large Panel Size and High-Resolution

• Issues

– Shortage of the Row Line Time

• Solutions

– Dual Line Scanning

– Display Area Division Scanning

– LiTEX(Line Time Extension)



Row Line Time and Resolution

35

30

25

20

15

10

5

0 50 55 60 65 70 75 80

XGASXGAUXGAQXGA

Frame Rate(Hz)

Row

Lin

e Ti

me

(se

c)

Large-Size High -Resolution

Increase of parasitic loads

Increase of RC charging time

Decrease ofrow line time

Deterioration of Image Quality

Needs for Increase techniques of row line time



Effective Mobility and Resolution

• Effective mobility : minimum mobility necessary to achieve the maximum aperture ratio

• Effective mobility is increased as panel size is larger

• Effective mobility is increased as the resolution of panel is higher

XGASXGAUXGAQXGA

Pixel Pitch (m)

Effe

ctiv

e m

obili

ty (C

m2/v

s)

0.0

0.5

1.0

1.5

2.0

2.5

150 200 250 300



Dual Line Scanning Method

• Dual Line Scanning Method– Pros. : Doubled Row Line Time– Cons. : Decrease of Vertical Resolution (1/2 of conventional)

• Display-Area division scanning– Pros. : Doubled Row Line Time– Cons. : Cost Increase (Doubled Driver LSIs)

G1G2G3G4

1H 1H 1H 1H

TFT-LCD panel

Driver LSIs



Line Time Extension Method

• Primitive Scanning Waveforms

LiTEXScanning

Conventional Scanning

1H

G1G2G3G4

1H 1H 1H

Extended Line TimeT1

Image Differentiation from G1T2

G1G2G3G4



Conclusions

• We have surveyed the driving methods and driver circuits.

• Reviewed issues and key Technologies – High Gray Scale

• New Driving Method for 8bit gray scale

– Low Power Consumptions• Multi-Field Driving Method

• Charge Sharing, Triple Charge Sharing, Stepwise Driving, RLC resonant

• Low Analog DC Power : precharging method, Class-B buffer

– High Aperture Ratio : Shield-Cs, ITO Shield Plane

– Wide Viewing Angle : VA, IPS

– High-Resolution : Dual line scanning, LiTEX

Documents

TFT(Thin Film Transistor) LCD II