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Timepix vs Timepix3. Timepix (2006). Broad experience with different type of sensors: Si N-on-P, P-on-N (from 50um to 2mm thick) and edgeless CdTe w ith Ohmic and Schottky contacts (1mm) GaAs (500um) >350 paper citations >200 wafers produced (107 chips/wafer) - PowerPoint PPT Presentation
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Timepix vs Timepix3Timepix (2006) Timepix3 (2013)
Pixel arrangement 256 x 256
Pixel size 55 x 55 µm²
Technology 250nm CMOS 130nm CMOS
Acquisition modes
1) Charge (iTOT)2) Time (TOA)3) Event counting (PC)
1) Time (TOA) AND Charge (TOT)2) Time (TOA)3) Event counting (PC) AND integral charge (iTOT)
Trigger-less
Readout Type 1) Frame based 1) Data driven (DD)2) Frame based (FB)
Zero suppressed readout NO YES
Dead time per pixel > 300 µsreadout time of one frame
> 475 nsPulse measurement time + packet transfer time
Minimum timing resolution 10 ns 1.562 ns
TOT Energy resolution ~300-600 e-FWHM
Minimum detectable charge >750 e- >500 e-
Collection Polarity e- and h+ (with leakage current compensation up to ~2nA/pixel)
Radiation hardness <250 krad Expected <200 Mrad (still to be measured)
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Timepix (2006)
• Broad experience with different type of sensors:– Si N-on-P, P-on-N (from 50um to 2mm thick) and edgeless– CdTe with Ohmic and Schottky contacts (1mm)– GaAs (500um)– >350 paper citations
• >200 wafers produced (107 chips/wafer)• Access to Timepix wafers possible• Different readout systems available from the Medipix2
collaboration:– Most versatile DAQ is FITPIX. USB interface from CTU Prague (
http://www.widepix.cz)
3
Timepix3 (2013)• Chip available since September 2013:
– Chip is fully functional
• Currently running the first wafer probing campaing prior bump-bonding to standard Si sensor (300 µm)
• Difficult availability to chips/wafers:– Priority to cover the Medipix3 collaboration needs– 12 wafers available (105 chips/wafer)– Production run (48 wafers) to be ordered as soon as first Si assemblies
validate the chip performance
• 3 readout DAQ under design:– SPIDR (NIKHEF/CERN) 10 Gbps link– FITPIX3 (Prague) USB 2.0 link– MERLIN (Diamond, UK)
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Frame basedand zero-supressed readout
• Maximum frame rate: 1300 fps @5.12Gbps
Acquisition time
Address[16-bit]0xA Data[28-bits]
Data Packet (48 bits)
48bit 48bit 48bit 48bit 48bit
End of Command (48 bits)
Shutter
Qin
DataOut
ChipID [32b]0x71 0xA0
5
Event-by-event data driven and zero-supressed readout
• Achievable count rate: – uniformly distributed events → ~40 Mhits/s/cm2 @5.12Gbps
• Full matrix readout: ~800 µs @5.12Gbps
Acquisition time
Address[16-bit]0xB Data[28-bits]
Data Packet (48 bits)
48bit 48bit 48bit 48bit 48bit 48bit
End of Command (48 bits)
Shutter
Qin
DataOut
ChipID [32b]0x71 0xB0
6
Tpeak < 25ns
Pixel Operation in TOA & TOT
TOT (10 bits) =4
Preamp Out
Disc Out
Clk (40MHz)
FTOA (4 bits)=7VCO Clk (640MHz)
TOT Clk (40MHz)
TOA (14-bit) 16383X TOA (14 bits)=16383
16384 0 2 3 41638316382 1
Pixel Readout Starts (475ns→ 19 clock cycles)
Global TOA (14-bit)
7
Tpeak < 25ns
Pixel Operation in TOA only
Preamp Out
Disc Out
Clk (40MHz)
FTOA (4 bits)=7VCO Clk (640MHz)
TOA (14-bit) 16383X TOA (14 bits)=16383
16384 0 2 3 41638316382 1
Pixel Readout Starts (475ns→ 19 clock cycles)
Global TOA (14-bit)
8
Pixel Operation in PC and iTOT
Preamp Out
Clk (40MHz)
Shutter
Pixel readoutcan start in
Data Driven orFrame based
Disc Out
3 0 PC (14 bits)=31 2PC (10-bit)
50 iTOT (14 bits)=51 2 3 4iTOT (14-bit)
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Timepix3 Pixel Schematic
Global threshold (LSB= ~10e-)
Front-end (Analog)LeakageCurrentcompensation
Preamp
Inputpad
1 pixel
VCO@640MHz
Super pixel (Digital)
Controlvoltage
Common for 8 pixels
640MHz
TpA TpB
TestBit MaskBit
Front-end (Digital)
Counters &
Latches
clock(40MHz)
Time stamp
14-bitsSynchronizer
&Clock gating
OP Mode
4-bit LocalThreshold
~50mV/ke-
TOA (14-bit) FTOA (4-bit)TOT (10-bit)TOA & TOT
TOA (14-bit) FTOA (4-bit)TOA
iTOT (14-bit) PC (10-bit)PC & iTOT3fF
3fF
Deserializer[1x31]
Super pixel FIFO
[2x31]
Data outto EOC
37-b
its
clock(40MHz)
Token arbitration
31-b
its
handshake
10
Tim
epix
3 Fl
oorp
lan
Reset DACOutExtDAC
BandGapGlobal DACs
EoC[0]
PLLx 2,4,8 and 16
Output Block
PPul[0]
DataInEnableInT0_SyncShutter
EnablePowerPulsingExtTPulse
SLVS_TERM
DataOut[7:0]ClkOutData
ClkIn40PLLOut
ClkO
ut40
,80,
160
or 3
20
Pixe
l Mat
rix
E-Fuses32 bits
VDDA/GNDAVDDPLL/GNDPLL
SuperPixel[0]
SuperPixel[0]
SuperPixel[63]
SuperPixel[63]
SuperPixel[0]SuperPixel[63]
Bus Controller48 bit bus
VDDA33
VDD/GND
Pixel MatrixData controller
Clk4
0
Perip
hery
Buffered Bias Voltage
OscBias640
Slow
Con
trol
&Co
mm
and
Dec
oder
Analog Periphery Control Logic
IOPa
ds
Rese
t
EoC[1]
PPul[1]
PPul[2]
OscB[2]
EoC[126]
EoC[127]
PPul[127]
OscB[63]
PPul[128]
OscB[0]
14100 µm
1408
0 µm
1260
µm
870
µm
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1 BandGap 18 Global DACs
EoC[0]
PLL 8x Serializer8b10b DDR
E-Fuses32 bitsCl
k40
Buffered bias voltages
VCO bias 640MHz
Slow Control&
Command Decoder
Analog Periphery Control Logic
EoC[1]
EoC[2]
VCO Buffer[2]
EoC[126]
EoC[127]
VCO Buffer[63]VCO Buffer [0]
1260
µm Bus
Controller
Timepix3 Active Periphery
Data output DDR 8b10b encoding(1 to 8 links) Up to 8x640 Mbps (5.12 Gbps)
Periphery bus(3.84Gbps)
64 VCO control voltage buffers
128 End of Column logic
12
14100 µm
1621
0 µm
Sens
itive
Are
a (1
4080
µm
)
Active Periphery (1260 µm)
Pad extenders (870 µm)
Timepix3 Layout
Double column:2x256pixels64 super pixels
55 µm
55 µ
m
Super Pixel (SP):•2x4 pixels•110x220 μm2
Full Pixel Matrix:256x256 pixels128 double columns
8192 VCOs (640MHz)177 Mtransistors
Active Periphery
Pad Extenders:Removed if TSV
Analog Front-End:•13x55 μm2
•<25% pixel area
VCO (FTOA):•9.6x20 μm2
•< 0.8% SP area
IO Pad on digital area:•Careful shielding•Pad is ½ of Timepix
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Medipix chip family
0 100 200 300 400 500 600 7000.01
0.1
1
10
CMOS process [nm]
Tra
ns
isto
r d
en
sit
y p
er
pix
el
[trt
s/µ
m2
]
Medipix1 (1998)
Clicpix (2013)
Medipix2 (1998)
Timepix (2006)
Timepix3 (2013)
Medipix3RX (2011)
ESE Seminar – X.Llopart 14
Timepix3 readout → SPIDR (Nikhef)• Speedy PIxel Detector Readout (SPIDR):
– Readout system for Medipix3 and Timepix3 (single upto quads)– 1 x 10Gbps Ethernet link IO
• First chips available since beginning of September• All measurements reported use data readout @640Mbps/link
Timepix3 Chip
VC707Evaluation Board
10 GbitEthernet
Virtex 7 FPGA
25th February 2014
ESE Seminar – X.Llopart 15
Timepix3 CERN PCBs
25th February 2014
Timepix3 CERN chip board
Timepix3 Probe card
Timepix3 translator FMC/VHDCI
ESE Seminar – X.Llopart 16
250 Test Pulses in 1 pixel [Threshold scan in PC & iTOT mode, 1 pixel]
0
100
200
300
400
500
-25 0 25 50 75 100 125 150 175 200 225 250
Couu
nts
Threshold DAC [LSB]
Noise Floor
TP=988e-
TP=1542e-
TP=2004e-
ENC ~5.7 LSBrms = ~60 e-
y = 10.4 e-/LSBR² = 0.999
0
500
1000
1500
2000
2500
-25 0 25 50 75 100 125 150 175 200 225 250
Couu
nts
Threshold DAC [LSB]
Assuming: Ctest=3fF → Tpulse=20e-/mV
25th February 2014
ESE Seminar – X.Llopart 17
0
2000
4000
6000
8000
10000
0 10 20 30 40 50 60 70 80 90 100Co
unts
ENC [e-]
Full Matrix ENC[Threshold scan over noise floor in PC & iTOT mode]
µ = 59.9e-
σ = 2.85e-
9 pixels not responding
15 pixels ENC > 80e-
1 256
256
1X (column number)
Y
0 25 50 75 100
• ENC matches predictions from simulations• No significant digital coupling into analog FE
25th February 2014
ESE Seminar – X.Llopart 18
0
1000
2000
3000
4000
5000
6000
7000
8000
9000
-1500 -1250 -1000 -750 -500 -250 0 250 500 750 1000 1250 1500
Coun
ts
[e-]
Pixel-to-pixel Threshold Equalization[Threshold scan over noise floor in PC & iTOT mode]
1 256
256
1X (column number)
Y
-1500 -750 0 750 1500
µ0 = -762e-
σ0 = 195e-
1 256
256
1X (column number)
Y
-1500 -750 0 750 1500
µF = 762e-
σF = 197e-
1 256
256
1X (column number)
Y
-1500 -750 0 750 1500
µeq = 0e-
σeq = 35e-
Pixel DAC = 0x0 Pixel DAC = 0xF
25th February 2014
ESE Seminar – X.Llopart 19
Full chip minimum threshold [Equalized pixel matrix, 16 pixels masked]
1248
163264
128256512
1024204840968192
163843276865536
0 100 200 300 400 500 600 700 800 900 1000
Num
ber o
f acti
ve p
ixel
s
Threshold [e-]
TOA and TOT in Data Driven Readout mode
PC and iTOT in Sequential Readout mode
TOA and TOT (VCO ON) ~500e-
ENC of ~77e-rms PC and iTOT ~400e-
ENC of ~60e-rms
~100e-
25th February 2014
20
More information
• Timepix3 PH-ESE seminar to come Feb. 25:http://indico.cern.ch/event/267425/ Everybody welcome to join.
