TLV717P 150-mA, Low-Dropout Regulator With Foldback

TLV717xx Series

GND

EN

IN OUTVIN VOUT

On

Off

CIN COUT

1 FCeramic

m

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.

TLV717PSBVS176B –OCTOBER 2011–REVISED APRIL 2016

TLV717P 150-mA, Low-Dropout Regulator With Foldback Current Limit for PortableDevices

1

1 Features1• Very Low Dropout: 215 mV at 150 mA• Accuracy: 0.5% (typical)• Low IQ: 35 µA• Available in Fixed-Output Voltages:

1.2 V to 5 V• High PSRR:

– 70 dB at 1 kHz– 50 dB at 1 MHz

• Stable With Effective Output Capacitance:0.1 µF

• Foldback Current Limit• Package: 1-mm × 1-mm DQN(1) See the Package Option Addendum at the end of this

document for a complete list of available voltage options.(2) See Input and Output Capacitor Requirements for more

details.

2 Applications• PCs and Notebooks• Smart Phones• Portable Electronics and Battery-Powered Devices• Electronic Point of Sale

3 DescriptionThe TLV717P series of low-dropout (LDO) linearregulators are low quiescent current LDOs withexcellent line and load transient performance and aredesigned for power-sensitive applications. Thesedevices provide a typical accuracy of 0.5%.

The TLV717P series offer current foldback thatthrottles down the output current with a decrease inload resistance. The typical value at which currentfoldback initiates is 350 mA; the typical value of theoutput short current limit value is 40 mA.

Furthermore, these devices are stable with aneffective output capacitance of only 0.1 µF. Thisfeature enables the use of cost-effective capacitorsthat have higher bias voltages and temperaturederating. The devices regulate to specified accuracywith no output load.

The TLV717P series is available in a 1-mm × 1-mmDQN package that makes them ideal for hand-heldapplications. The TLV717P provides an activepulldown circuit to quickly discharge output loads.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)TLV717P X2SON (4) 1.00 mm × 1.00 mm

(1) For all available packages, see the orderable addendum atthe end of the data sheet.

Typical Application Circuit

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Table of Contents1 Features .................................................................. 12 Applications ........................................................... 13 Description ............................................................. 14 Revision History..................................................... 25 Pin Configuration and Functions ......................... 36 Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 46.2 ESD Ratings.............................................................. 46.3 Recommended Operating Conditions....................... 46.4 Thermal Information .................................................. 46.5 Electrical Characteristics........................................... 56.6 Typical Characteristics .............................................. 6

7 Detailed Description .............................................. 97.1 Overview ................................................................... 97.2 Functional Block Diagram ......................................... 97.3 Feature Description................................................... 97.4 Device Functional Modes........................................ 10

8 Application and Implementation ........................ 118.1 Application Information............................................ 118.2 Typical Application .................................................. 11

9 Power Supply Recommendations ...................... 1310 Layout................................................................... 13

10.1 Layout Guidelines ................................................. 1310.2 Layout Example .................................................... 1310.3 Power Dissipation ................................................. 13

11 Device and Documentation Support ................. 1411.1 Device Support...................................................... 1411.2 Documentation Support ........................................ 1411.3 Community Resource............................................ 1411.4 Trademarks ........................................................... 1411.5 Electrostatic Discharge Caution............................ 1411.6 Glossary ................................................................ 14

12 Mechanical, Packaging, and OrderableInformation ........................................................... 15

4 Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (February 2012) to Revision B Page

• Deleted all instances of TLV717xx; Replaced with generic part number, TLV717P.............................................................. 1• Updated Applications. ............................................................................................................................................................ 1• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation

section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, andMechanical, Packaging, and Orderable Information section ................................................................................................. 1

• Changed TJ = –25°C to TJ = 25°C in the conditions statement in Absolute Maximum Ratings............................................. 4• Changed TA to TJ throughout Electrical Characteristics ......................................................................................................... 5• Changed TA to TJ in the conditions statement in Typical Characterisitcs ............................................................................. 6• Changed TA to TJ in the conditions statement in Typical Characterisitcs ............................................................................. 7• Changed TA to TJ in the conditions statement in Typical Characterisitcs ............................................................................. 8• Changed junction temperature range from –40°C to 125°C to –40°C to 85°C in Overview .................................................. 9• Deleted TLV717xx functional block diagram .......................................................................................................................... 9

Changes from Original (October 2011) to Revision A Page

• Changed document status from Product Preview to Production Data ................................................................................... 1


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GND OUT

EN IN

3 4

2 1OUT GND

IN EN

1 2

4 3

3

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5 Pin Configuration and Functions

DQN Package4-Pin X2SON

Top ViewDQN Package4-Pin X2SONBottom View

Pin FunctionsPIN

I/O DESCRIPTIONNAME NO.

EN 3 I Enable pin. Driving EN over 1.2 V turns on the regulator. Driving EN below 0.4 V puts the regulatorinto shutdown mode.

GND 2 — Ground pin

IN 4 IInput pin. A small capacitor is recommended from this pin to ground to assure stability. See theInput and Output Capacitor Requirements section in the Application and Implementation for moredetails.

OUT 1 ORegulated output voltage pin. A small 1-μF ceramic capacitor is recommended from this pin toground to assure stability. See the Input and Output Capacitor Requirements section in theApplication and Implementation for more details.

Thermalpad — — Connect to GND for improved thermal performance.


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4




(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, which do not imply functional operation of the device at these or any other conditions beyond those indicated under RecommendedOperating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6 Specifications

6.1 Absolute Maximum RatingsAt TJ = 25°C, unless otherwise noted. All voltages are with respect to GND. (1)

MIN MAX UNIT

Voltage

Input range, VIN –0.3 6

VEnable range, VEN –0.3 VIN + 0.3

Output range, VOUT –0.3 6

Current Maximum output, IOUT Internally limited

Output short-circuit duration Indefinite

Continuous total power dissipation, PDISS See Thermal Information

TemperatureJunction, TJ –55 150

°CStorage junction, Tstg –55 150

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD RatingsVALUE UNIT

V(ESD) Electrostatic dischargeHuman-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000

VCharged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±500

6.3 Recommended Operating Conditionsover operating junction temperature range (unless otherwise noted)

MIN MAX UNITVIN Input voltage 1.7 5.5 VVOUT Output voltage 1.2 5 VIOUT Output current 0 150 mAVEN Enable pin voltage 0 VIN VTJ Junction temperature –40 85 °C

6.4 Thermal Information

THERMAL METRICTLV717P

UNITDQN (X2SON)4 PINS

RθJA Junction-to-ambient thermal resistance 393.3 °C/WRθJC(top) Junction-to-case(top) thermal resistance 140.3 °C/WRθJB Junction-to-board thermal resistance 330 °C/WψJT Junction-to-top characterization parameter 6.5 °C/WψJB Junction-to-board characterization parameter 329 °C/WRθJC(bot) Junction-to-case(bottom) thermal resistance 147.5 °C/W


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6.5 Electrical CharacteristicsAt operating temperature range (TJ = –40°C to 85°C), TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.7 V (whichever is greater), IOUT = 10 mA, VEN= VIN, and COUT = 1 µF, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITVIN Input voltage range 1.7 5.5 VVOUT Output voltage range 1.2 5 VIOUT Output current 150 mA

DC output accuracyTJ = +25°C 0.5%VOUT ≥ 1.2 V, –40°C ≤ TJ ≤ +85°C –1.5% 1.5%VOUT ≤ 1.2 V 25 mV

ΔVO/VIN Line regulation VOUT(NOM) + 0.5 V ≤ VIN ≤ 5.5 V 1 5 mVΔVO/IOUT Load regulation 0 mA ≤ IOUT ≤ 150 mA 10 20 mV

VDO Dropout voltage VIN = 0.98 × VOUT(NOM),IOUT = 150 mA

1.2 V ≤ VOUT < 1.5 V 330 500mV1.5 V ≤ VOUT < 1.8 V 330 450

1.8 V ≤ VOUT ≤ 5 V 215 350IGND Ground pin current IOUT = 0 mA 35 55 µAISHDN Shutdown current VEN ≤ 0.4 V, 2 V ≤ VIN ≤ 4.5 V 0.1 0.5 µA

PSRR Power-supplyrejection ratio

VIN = 3.3 V, VOUT = 2.8 V,IOUT = 30 mA

f = 10 Hz 70

dBf = 100 Hz 70f = 1 kHz 65f = 10 kHz 60f = 100 kHz 43

VNOISE Output noise voltage BW = 100 Hz to 100 kHz, VIN = 2.3 V, VOUT = 1.8 V,IOUT = 10 mA 55 µVRMS

tSTR Start-up time COUT = 1 μF, IOUT = 150 mA 100 µsISC Short current limit VIN = min (VOUT(NOM) + 1 V, 5.5 V), VOUT = 0 V 40 mAVHI Enable high (enabled) 0.9 VIN VVLO Enable low (disabled) 0 0.4 VIEN EN pin current EN = 5.5 V 0.01 µARPULLDOWN Pulldown resistor 120 Ω

UVLO Undervoltage lockout VIN rising 1.6 V


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Output Current (mA)

50 150

0.3

0.25

0.2

0.15

0.1

0.05

0

Dro

pout V

oltage (

V)

60 70 80 90

G005

+85 C°

+25 C°

- °40 C

100 130 140120110

Temperature ( C)°

-40 85

2.838

2.828

2.818

2.808

2.798

2.788

2.778

2.768

2.758

Outp

ut V

oltage (

V)

-27.5 -15 -2.5 10

G006

10 mA

150 mA

22.5 60 72.547.535

Input Voltage (V)

3 5.5

2.9

2.88

2.86

2.84

2.82

2.8

2.78

2.76

2.74

2.72

2.7

Outp

ut V

oltage (

V)

3.5 4 4.5 5

G003

+85 C°

+25 C°

- °40 C

I = 150 mAOUT

Fixed Output Voltage Versions (V)

1.5 5

0.3

0.25

0.2

0.15

0.1

Dro

pout V

oltage (

V)

2 2.5 3 3.5

G004

+85 C°

+25 C°

- °40 C

4 4.5

I (mA)OUT

0 200

2.9

2.88

2.86

2.84

2.82

2.8

2.78

2.76

2.74

2.72

2.7

V(V

)O

UT

20 40 60 80 100

G001

120 140 160 180

+85 C°

+25 C°

- °40 C

Input Voltage (V)

3 5.5

2.9

2.88

2.86

2.84

2.82

2.8

2.78

2.76

2.74

2.72

2.7

Outp

ut V

oltage (

V)

3.5 4 4.5 5

G002

+85 C°

+25 C°

- °40 C

I = 10 mAOUT

6




6.6 Typical CharacteristicsAt operating temperature range (TJ = –40°C to 85°C), TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.7 V (whichever is greater), IOUT= 10 mA, VEN = VIN, and COUT = 1 µF, unless otherwise noted.

Figure 1. Load Regulation Figure 2. Line Regulation

Figure 3. Line Regulation Figure 4. Dropout Voltage vs Fixed Output Voltage Versions

Figure 5. Dropout Voltage vs Output Current Figure 6. Output Voltage vs Temperature


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Frequency (Hz)

10 10M

80

70

60

50

40

30

20

10

0

Pow

er-

Supply

Reje

ction R

atio (

dB

)

100 1k 10k

G011

100k 1M

I = 30 mAOUT

I = 150 mAOUTV V = 0.5 V-IN OUT

Frequency (Hz)

10 10M

80

70

60

50

40

30

20

10

0

Po

we

r-S

up

ply

Re

jectio

n R

atio

(d

B)

100 1k 10k

G012

100k 1M

I = 30 mAOUT

I = 150 mAOUTV V = 1 V-IN OUT

Temperature ( C)°

-40 85

45

40

35

30

25

20

15

10

5

0

Gro

un

d P

in C

urr

en

t (

A)

m

-27.5 -15 -2.5 10

G009

22.5 60 72.547.535

I = 0 mAOUT

Output Current (mA)

0 350

3

2.5

2

1.5

1

0.5

0

Ou

tpu

t V

olta

ge

(V

)

50 100 150 200

G010

250 300

+85 C°

+25 C°

- °40 C

Input Voltage (V)

3 5.5

45

40

35

30

25

20

15

10

5

0

Gro

un

d P

in C

urr

en

t (

A)

m

3.5 4 4.5 5

G007

+85 C°

+25 C°

- °40 C

I = 0 mAOUT

Output Current (mA)

0 150

3000

2500

2000

1500

1000

500

0

Gro

un

d P

in C

urr

en

t (

A)

m

25 50

G008

+85 C°

+25 C°

- °40 C

75 100 125

7




Typical Characteristics (continued)At operating temperature range (TJ = –40°C to 85°C), TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.7 V (whichever is greater), IOUT= 10 mA, VEN = VIN, and COUT = 1 µF, unless otherwise noted.

Figure 7. Ground Pin Current vs Input Voltage Figure 8. Ground Pin Current vs Output Current

Figure 9. Ground Pin Current vs Temperature Figure 10. Output Voltage vs Output Current

Figure 11. TLV71728PSRR vs Frequency Figure 12. TLV71728PSRR vs Frequency


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Input Voltage (V)

3.6 4.3

90

80

70

60

50

40

30

20

10

0

Po

we

r-S

up

ply

Re

jectio

n R

atio

(d

B)

3.7 3.8 3.9

G013

4 4.1

1 kHz

10 kHz

100 kHz

4.2

Frequency (Hz)

10 10M

10

1

0.1

0.01

0

No

ise

Sp

ectr

al D

en

sity (

V/

)m

ÖH

z

100 1k 10k

G014

100k 1M

1.2

2.8

5

8




Typical Characteristics (continued)At operating temperature range (TJ = –40°C to 85°C), TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.7 V (whichever is greater), IOUT= 10 mA, VEN = VIN, and COUT = 1 µF, unless otherwise noted.

Figure 13. PSRR vs Input Voltage Figure 14. Output Spectral Noise Density vs Frequency


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Foldback CurrentLimit

UVLO

Bandgap

IN

EN

OUT

LOGIC

120 W

GND


9




7 Detailed Description

7.1 OverviewThe TLV717P belongs to a new family of next-generation value low-dropout (LDO) regulators. These devicesconsume low quiescent current and deliver excellent line and load transient performance. These characteristics,combined with low noise, very good PSRR with little (VIN – VOUT) headroom, make this family of devices ideal forRF portable applications.

This family of regulators offers current foldback. Device operating junction temperature is –40°C to 85°C.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Internal Current LimitThe TLV717P has an internal foldback current limit that helps to protect the regulator during fault conditions. Thecurrent supplied by the device is gradually throttled down as the output voltage decreases. When the output isshorted, the LDO supplies a typical current of 40 mA. Output voltage is not regulated when the device is incurrent limit, and is VOUT = ILIMIT × RLOAD. The advantage of foldback current limit is that the ILIMIT value is lessthan the fixed current limit. Therefore, the power that the PMOS pass transistor dissipates [(VIN – VOUT) × ILIMIT] ismuch less.

The TLV717P PMOS pass element has a built-in body diode that conducts current when the voltage at OUTexceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is anticipated,external limiting to 5% of the rated output current is recommended.


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Feature Description (continued)7.3.2 ShutdownThe enable pin (EN) is active high. The device is enabled when the voltage at the EN pin goes above 0.9 V. Thisrelatively lower voltage value required to turn the LDO on can be exploited to power the LDO with a GPIO ofrecent processors whose GPIO logic 1 voltage level is lower than traditional microcontrollers. The device isturned off when the EN pin is held at less than 0.4 V. When shutdown capability is not required, EN can beconnected to the IN pin.

7.3.3 Undervoltage Lockout (UVLO)The TLV717P uses an undervoltage lockout circuit (UVLO = 1.6 V) to keep the output shut off until the internalcircuitry operates properly.

7.4 Device Functional Modes

7.4.1 Normal OperationThe device regulates to the nominal output voltage under the following conditions:

• The input voltage has previously exceeded the UVLO rising voltage and has not decreased below the UVLOfalling threshold.

• The input voltage is greater than the nominal output voltage added to the dropout voltage.• The enable voltage has previously exceeded the enable rising threshold voltage and not decreased below the

enable falling threshold.• The output current is less than the current limit.

7.4.2 Dropout OperationIf the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all otherconditions are met for normal operation, the device operates in dropout mode. In this condition, the outputvoltage is the same the input voltage minus the dropout voltage. The transient performance of the device issignificantly degraded because the pass device is in a triode state and no longer controls the current through theLDO. Line or load transients in dropout may result in large output voltage deviations.

7.4.3 DisabledThe device is disabled under the following conditions:• The input voltage is less than the UVLO falling voltage, or has not yet exceeded the UVLO rising threshold.• The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising

threshold.

When the device is disabled, the active pulldown resistor discharges the output.

Table 1 lists the conditions that lead to the different modes of operation.

Table 1. Device Functional Mode Comparison

OPERATING MODEPARAMETER

VIN VEN IOUT

Normal mode VIN > VOUT(nom) + VDOand VIN > UVLORISE

VEN > VEN(HI) IOUT < ILIM

Dropout mode UVLORISE < VIN < VOUT(nom) + VDO VEN > VEN(HI) IOUT < ILIM

Disabled mode(any true condition disablesthe device)

VIN < UVLOFALL VEN < VEN(LO) —


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TLV717xx Series

GND

EN

IN OUTVIN VOUT

On

Off

CIN COUT

1 FCeramic

m


11




8 Application and Implementation

NOTEInformation in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.

8.1 Application InformationThe TLV717P is a low-dropout regulator (LDO) with low quiescent current that delivers excellent line and loadtransient performance. This LDO regulator offers a foldback current limit. The operating junction temperature ofthis device series is –40°C to 85°C.

8.2 Typical Application

Figure 15. Typical Application Circuit

8.2.1 Design RequirementsTable 2 lists the parameters for this application.

Table 2. Design ParametersPARAMETER DESIGN REQUIREMENTInput voltage 3.8 V

Output voltage 2.8 V ±1%Output current 30 to 150 mA

8.2.2 Detailed Design Procedure

8.2.2.1 Input and Output Capacitor RequirementsTI recommends X5R- and X7R-type ceramic capacitors because they have minimal variation in value andequivalent series resistance (ESR) over temperature. The TLV717P is designed to be stable with an effectivecapacitance of 0.1 µF or larger at the output, though TI recommends a 1-µF ceramic capacitor for typicalapplications. Thus, the device is stable with capacitors of other dielectric types as well, as long as the effectivecapacitance under operating bias voltage and temperature is greater than 0.1 µF. This effective capacitancerefers to the capacitance that the LDO detects under operating bias voltage and temperature conditions; that is,the capacitance after taking both bias voltage and temperature derating into consideration. In addition to allowingthe use of cheaper dielectrics, this capability of being stable with 0.1-µF effective capacitance also enables theuse of smaller footprint capacitors that have higher derating in size- and space-constrained applications. Using a0.1-µF rated capacitor at the LDO output does not ensure stability because the effective capacitance under thespecified operating conditions would be less than 0.1 µF. Maximum ESR should be less than 200 mΩ.

Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-µF to 1-µF, low ESR capacitor across the IN and GND pins of the regulator. This capacitor counteracts reactive inputsources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may benecessary if large, fast, rise-time load transients are anticipated, or if the device is not located close to the powersource. If source impedance is more than 2 Ω, a 0.1-µF input capacitor may be necessary to ensure stability.


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Output Current (mA)

0 150

3000

2500

2000

1500

1000

500

0

Gro

un

d P

in C

urr

en

t (

A)

m

25 50

G008

+85 C°

+25 C°

- °40 C

75 100 125

Frequency (Hz)

10 10M

10

1

0.1

0.01

0

No

ise

Sp

ectr

al D

en

sity (

V/

)m

ÖH

z

100 1k 10k

G014

100k 1M

1.2

2.8

5

12




8.2.2.2 Dropout VoltageThe TLV717P uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropoutvoltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is theRDS(ON) of the PMOS pass element. VDO scales approximately with output current because the PMOS devicebehaves like a resistor in dropout. As with any linear regulator, PSRR and transient response are degraded as(VIN – VOUT) approaches dropout.

8.2.2.3 Transient ResponseAs with any regulator, increasing the size of the output capacitor reduces over- and undershoot magnitude butincreases the duration of the transient response.

8.2.3 Application Curves

Figure 16. Ground Pin Current vs Output Current Figure 17. Output Spectral Noise Density vs Frequency


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COUT

VOUT VIN

GND PLANE

CIN

Represents via used for application specific connections

1

2 3

4


13




9 Power Supply RecommendationsConnect a low-output impedance power supply directly to the IN pin of the TLV717P. Inductive impedancesbetween the input supply and the IN pin can create significant voltage excursions at the IN pin during start-up orload transient events. If inductive impedances are unavoidable, use an input capacitor.

10 Layout

10.1 Layout GuidelinesInput and output capacitors should be placed as close to the device pins as possible. To improve ACperformance (such as PSRR, output noise, and transient response), TI recommends designing the board withseparate ground planes for VIN and VOUT, with the ground plane connected only at the device GND pin. Inaddition, the output capacitor ground connection should be connected directly to the device GND pin. High ESRcapacitors may degrade PSRR performance.

10.2 Layout Example

Figure 18. Recommended Layout Example

10.3 Power DissipationThe ability to remove heat from the die is different for each package type, presenting different considerations inthe printed-circuit board (PCB) layout. The PCB area around the device that is free of other components movesthe heat from the device to ambient air. Performance data for JEDEC-low and high-K boards are given inThermal Information. Using heavier copper increases the effectiveness in removing heat from the device. Theaddition, plated through-holes to heat-dissipating layers also improves heatsink effectiveness.

Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product ofthe output current and the voltage drop across the output pass element, as shown in Equation 1.

PD = (VIN – VOUT) × IOUT (1)


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14




(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit thedevice product folder on www.ti.com.

11 Device and Documentation Support

11.1 Device Support

11.1.1 Development Support

11.1.1.1 Evaluation ModulesAn evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TLV717P.SLVU553 details the design kits and evaluation modules for TLV71733PEVM-072.

The EVM can be requested at the Texas Instruments website through the TLV717P product folder, or purchaseddirectly from the TI eStore.

11.1.2 Device Nomenclature

Table 3. Device Nomenclature (1)

PRODUCT VOUT

TLV717xx(x)Pyyyz

XX(X) is the nominal output voltage. For output voltages with a resolution of 100 mV, twodigits are used in the ordering number; otherwise, three digits are used (for example, 28 =2.8 V; 475 = 4.75 V).P indicates an active output discharge feature. All members of TLV717P family will activelydischarge the output when the device is disabled.YYY is the package designator.Z is the package quantity. R is for 3000 pieces, T is for 250 pieces.

11.2 Documentation Support

11.2.1 Related DocumentationTLV71733PEVM-072 Evaluation Module user guide, SLVU553

11.3 Community ResourceThe following links connect to TI community resources. Linked contents are provided "AS IS" by the respectivecontributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms ofUse.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaborationamong engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and helpsolve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools andcontact information for technical support.

11.4 TrademarksE2E is a trademark of Texas Instruments.All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge CautionThis integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.6 GlossarySLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.


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http://www.ti.com/lit/pdf/SLVU553

http://www.ti.com/tool/TLV71733PEVM-072

http://www.ti.com/product/tlv717p

https://store.ti.com/TLV71733PEVM-072-Evaluation-Module-for-TLV71733P-Single-Output-Low-Noise-Low-Dropout-Regulator-P2746.aspx

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http://www.ti.com/lit/pdf/SLYZ022

15




12 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.


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PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead finish/Ball material

(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

TLV71712PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 UX

TLV71712PDQNR3 ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 UX

TLV71712PDQNT ACTIVE X2SON DQN 4 250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 UX

TLV71713PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 VC

TLV71713PDQNT ACTIVE X2SON DQN 4 250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 VC

TLV71715PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 UY

TLV71715PDQNT ACTIVE X2SON DQN 4 250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 UY

TLV717185PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 VN

TLV717185PDQNT ACTIVE X2SON DQN 4 250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 VN

TLV71718PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 UZ

TLV71718PDQNT ACTIVE X2SON DQN 4 250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 UZ

TLV71721PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 AR

TLV71721PDQNT ACTIVE X2SON DQN 4 250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 AR

TLV71725PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 VA

TLV71725PDQNT ACTIVE X2SON DQN 4 250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 VA

TLV71727PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 AS

TLV71727PDQNT ACTIVE X2SON DQN 4 250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 AS

TLV717285PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM VE

TLV717285PDQNT ACTIVE X2SON DQN 4 250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 VE

TLV71728PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 VD

http://www.ti.com/product/TLV717P?CMP=conv-poasamples#samplebuy






















Addendum-Page 2

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead finish/Ball material

(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

TLV71728PDQNR3 ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VD

TLV71728PDQNT ACTIVE X2SON DQN 4 250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 VD

TLV71729PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 VI

TLV71729PDQNT ACTIVE X2SON DQN 4 250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 VI

TLV71730PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 VF

TLV71730PDQNT ACTIVE X2SON DQN 4 250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 VF

TLV71733PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 VG

TLV71733PDQNT ACTIVE X2SON DQN 4 250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 VG

TLV71736PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 VH

TLV71736PDQNT ACTIVE X2SON DQN 4 250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 VH

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide basedflame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.













Addendum-Page 3

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

TLV71712PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2


TLV71712PDQNR3 X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 2.0 8.0 Q3

TLV71712PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2















PACKAGE MATERIALS INFORMATION

www.ti.com 24-Jul-2020

Pack Materials-Page 1

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant
















TLV71728PDQNR3 X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 2.0 8.0 Q3


















*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TLV71712PDQNR X2SON DQN 4 3000 184.0 184.0 19.0


TLV71712PDQNR3 X2SON DQN 4 3000 184.0 184.0 19.0

TLV71712PDQNT X2SON DQN 4 250 184.0 184.0 19.0




















Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)














TLV71728PDQNR3 X2SON DQN 4 3000 184.0 184.0 19.0


















PACKAGE OUTLINE

DQN0004AX2SON - 0.4 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

4215302/E 12/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

4. Features may not exist. Recommend use of pin 1 marking on top of package for orientation purposes.

5. Shape of exposed side leads may differ.

6. Number and location of exposed tie bars may vary.

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B

A

SEATING PLANE

C

0.08

PIN 1

INDEX AREA

0.1 C A B

0.05 C

PIN 1 ID

(OPTIONAL)

NOTE 4

EXPOSED

THERMAL PAD

1

2

3

4

1

1.05

0.95

1.05

0.95

0.4 MAX

2X 0.65

0.48

+0.12

-0.1

3X

0.30

0.15

0.3

0.2

4X

0.28

0.15

0.05

0.00

(0.11)

NOTE 5

NOTE 6

NOTE 6

5

(0.07) TYP

(0.05) TYP

EXAMPLE BOARD LAYOUT



4215302/E 12/2016

NOTES: (continued)

7. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271) .8. If any vias are implemented, it is recommended that vias under paste be filled, plugged or tented.

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SOLDER MASK

DEFINED

SOLDER MASK DETAIL

0.05 MIN

ALL AROUND

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

LAND PATTERN EXAMPLE

SCALE: 40X

SYMM

SYMM

1

2

3

4

4X (0.21)

4X (0.36)

(0.65)

(0.86)

( 0.48)

SEE DETAIL

4X (0.18)

(0.22) TYP

EXPOSED METAL

CLEARANCE

4X

(0.03)

EXPOSED METAL

5

EXAMPLE STENCIL DESIGN



4215302/E 12/2016

NOTES: (continued)

9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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SOLDER PASTE EXAMPLE

BASED ON 0.075 - 0.1mm THICK STENCIL

EXPOSED PAD

88% PRINTED SOLDER COVERAGE BY AREA

SCALE: 60X

SYMM

SYMM

1

2

3

4

SOLDER MASK

EDGE

4X (0.21)

4X (0.4)

(0.65)

(0.9)

( 0.45)

4X (0.03)

4X (0.235)

4X (0.22)

5

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources.TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2020, Texas Instruments Incorporated

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