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Santa Clara University School of Engineering

Department of Electrical Engineering Tutorial for Xilinx ISE 7.1i WebPACK and Xilinx Spartan 3 Section II Prepared By: Sally Wood, PhD and Shant Kazanjian (Spring 2006) Section II Outline: IV- Hardware Description Language with Xilinx Project Navigator and Xilinx XST V- Implementation and Downloading on Xilinx Spartan 3 VI- Logic and Input/Output Blocks with Xilinx FPGA Editor VII- Xilinx Spartan 3 and Digilent Starter Board

IV- Hardware Description Language with Xilinx Project Navigator and Xilinx XST 1- When creating a new project, remember that in the Project Properties window, you need to specify the ‘Generated Simulation Language’ to the Hardware Description Language (HDL) of your choice, in the following window it is Verilog.

Figure 29. New project properties window showing the HDL language as Verilog

2- After creating the project, go to Project from the menus tool bar → New Source → select Verilog Module

as your source type and name your file. As an example, we will design a full adder module and instantiate it in a 4 bit adder module.

Figure 30. New source file window with a Verilog Module file type

3- When you continue with Next you will encounter a window for defining your Verilog source file inputs

and outputs.

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Figure 31. Defining the Verilog source file inputs and outputs for the full adder

4- The Verilog code for a full adder is shown in the next figure; this code is in a structural level

representation. A full adder is basically an adder with 3 inputs and 2 outputs. The inputs consist of the two 1 bit primary inputs which need to be added as well as the carry in, and the outputs are the 1 bit sum output as well as the carry out.

5- To check if you have any syntax errors in your Verilog code, go to the Process View options window →

Synthesis XST → Check Syntax.

Figure 32. Verilog module of a full adder

6- After creating a Verilog source file for the full adder, we need to create a Verilog source file in the same

manner for the 4 bit adder. In this 4 bit adder we will instantiate 4 full adders. The difference between these two source files is clear in the following figure. When we define the inputs for the 4 bit adder module we need to specify the number of bits for our inputs and outputs, in this case 4 bits, which can be translated as an array from 0 to 3, having 0 as the least significant bit (LSB), and the 3 as the most significant bit (MSB).

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Figure 33. Defining the Verilog source file inputs and outputs of the 4 bit adder

In the 4 bit adder we have three inputs and 3 outputs. The inputs consist of the two 4 bit numbers as well as the carry in, and the outputs consist of the 4 bit sum output as well as the carry out and the overflow output.

Figure 34. Verilog module of a 4 bit adder

7- In order to use the 4 bit adder in our top level schematic, we need to go to the “Process View” options list

and from “Design Utilities”, choose Create Schematic Symbol. With this step you create a symbol for your 4 bit adder so that you can use it in a schematic source file.

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Figure 35. Schematic symbol created from the 4 bit adder Verilog module

BE CAREFUL: Every time you go back and make a change in your HDL file, you need to redo the step of creating a schematic symbol.

NOTE: After you make changes to your HDL file and create a new schematic symbol, when you go back to your schematic file, you will notice that the tool will ask you whether you want to update the changed symbol.

8- Because we have instantiated 4 full adder module in the 4 bit adder code, notice that in the Sources, in the

project options window, you have created a little hierarchy tree, with the 4 bit adder source being the parent of the full adder source.

Figure 36. Hierarchy of the project source files

9- In order to use the created schematic symbol in the top level schematic source file, open the tab where you

can choose Symbols → from Categories choose → from Symbol choose myAdder4. Drag this new symbol and use it in your top level schematic source file. Notice that after you save all these source files you will see a hierarchy like shown above.

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V- Implementation and Downloading on Xilinx Spartan 3: 1- After creating a schematic source file, which has the logic circuit with all the Ibuf’s and Obuf’s and the

corresponding I/O markers, select these buffers, double click on them and you will get the following pop-up window:

Figure 37. Buffer properties window

2- On the above figure notice that we have an attribute called LOC, (which stands for location), but you will

not find that in your window, thus you need to create that new trait → go to new → attribute name: LOC, attribute value: K13, attribute value type: string, as explain in the following figure.

Figure 38. Creating a new attribute, LOC, for a buffer

3- Connect the Xilinx Spartan 3 FPGA board to the computer as well as to the power outlet. BE CAREFUL: When connecting the JTAG connection to its port on the Digilent board, make sure you have the names of the pins on the connection match the ones on the port.

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HINT: From the Process View sub-window right-click on the ‘Generate Programming File’ and you will get a pop-up window like shown below. Under ‘Startup Options’, change the ‘FPGA Start-up Clock’ to ‘JTAG Clock’. This will help you avoid some clock programs after you program your device.

Figure 39. Changing the start up clock to a JTAG clock

4- In order to download your schematic design on the board, you need to undergo the final configuration of

your design → from the Process View options scroll down till the end → choose Configure Device (iMPACT) → You will get a pop-up window called configure device → choose Boundary Scan Mode, shown in the following set of figures.

Figure 40. Configure Device (iMPACT) from the Processes to source sub-window

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Figure 41. Pop-up window appearing while configuring a device,

Figure 42. Window appearing after boundary scan mode selection

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5- You will see two devices → choose the first which is the device you are using xc3s200 → assign new configuration file: which is the .bit file you have for the first device, but for the second just click on the Bypass button, as shown in the following figures.

Figure 43. Choosing the .bit configuration file for the first device

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Figure 44. Choosing Bypass for the second device

6- Select the xc3s200 .bit device → go to operations from the menus bar → program → ok

Figure 45. Program options window for the first device

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Figure 46. Program was downloaded successfully on the Digilent Spartan 3 Board

NOTE: When you get “Programming Failed” try to program again, most of the time it programs successfully the second time you try. If not, make sure the connection is place properly, and also that you have chosen the right .bit file for the first device, and of course that you are using the right device, in our case the xc3s200.

7- Again from the Process View window of options → implement Design → place and route → Place and

Route report (PAR) double click on that and you will get a report file

Figure 47. Place and Route Report (PAR) option from the process view sub-window

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try to locate the device utilization summary → you usually need to find out how many input/output buffers (IOB) and logic block slices you have used, also make sure you check that you have no errors, as seen in the following figure.

Figure 48. Part of the Place and Route report showing the number of IOB’s and Slices used

VI- Logic and Input/Output Blocks with Xilinx FPGA Editor: 1- You need to examine your implementation by going to FPGA Editor (from the start menu → Xilinx ISE

7.1i → accessories or from the process view sub-window options) you will get the following window:

Figure 49. Xilinx FPGA Editor graphical user interface

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2- Go to file → open and browse → go to your project folder and choose the file which has the name of your

schematic that you did and an extension .ncd as shown in the figure below

Figure 50. Opening a design with Xilinx FPGA Editor

3- From the list 1 window change the all components option in the scroll box to routed nets, select one of the

nets and then zoom in, in order to find out the route of the specified net. The specified net would turn red when selected.

Figure 51. Close view of a selected logic slice

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4- If you place the cursor of your mouse on one of the red or blue blocks it will tell you if it is a Slice (logic block) or an IOB (input/output block) with its specific number. Double click on these blocks and you will get a window like the following (this one is the window after selecting a Slice):

Figure 52. Inside a slice, which includes two Look-up tables (LUT) and two flip flops

Notice, in this block, we have two look-up tables (LUT) and two flip flops, if you leave the cursor of the mouse on an LUT or if you click on an LUT, you will get its logic function. LUT set the logic functions, while the flip-flops act as storage elements.

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Figure 53. Close-up view for a set of one LUT and one Flip flop with all their surrounding circuitry

But if you select an IOB and double click, you will get a window like the following figure.

Figure 54. Inside an input/output block

The inside view of a logic slice is completely different from that of a IOB.

HINT: When getting the equation (logic function) of an LUT, the @ sign symbolizes an XOR, and the ~ sign symbolizes an inverse.

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VII- Xilinx Spartan 3 and Digilent Starter Board: The Xilinx Spartan 3 field programmable gate arrays (FPGA) are the most commonly used educational logic device families. The Xilinx Spartan 3 FPGA used in this introductory logic design lab is mounted on the Digilent Starter board, which has many student-friendly features and attributes. The following picture courtesy of Digilent and Xilinx shows the essential parts of this board.

Figure 55. Essential parts on an Digilent Xilinx Spartan 3 Starter Board

The following are helpful resources for further incite: Spartan-3 Starter Kit Board User Guide Xilinx ISE 7 Software Manuals and Help – PDF Collection

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