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To our customers,

Old Company Name in Catalogs and Other Documents

On April 1st, 2010, NEC Electronics Corporation merged with Renesas TechnologyCorporation, and Renesas Electronics Corporation took over all the business of bothcompanies. Therefore, although the old company name remains in this document, it is a validRenesas Electronics document. We appreciate your understanding.

Renesas Electronics website: http://www.renesas.com

April 1st, 2010

Renesas Electronics Corporation

Issued by: Renesas Electronics Corporation (http://www.renesas.com)

Send any inquiries to http://www.renesas.com/inquiry.

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M66291GP/HPASSP (USB2.0 Device Controller)

REJ03F0125-0101ZRev1.01

2004.11.01

1OverviewThe M66291 is a general purpose USB (Universal Serial Bus) device controller compliant with the USB

Specification Revision 2.0 and supports full speed transfer. The USB transceiver circuit is included, and the M66291

meets all transfer types which are defined in the USB specification. The M66291 has FIFO of 3 Kbytes for data

transfer and can set 7 endpoints (maximum). Each endpoint can be set programmable of its transfer condition, so can

correspond to each device class transfer system of USB.

1.1 Features

USB Specification Revision 2.0 compliant Supports Full Speed (12 Mbps) transfer

Built-in USB transceiver circuit Built-in oscillation buffer (Supports 6M/12M/24 MHz of oscillator) and PLL at 48 MHz Supports Vbus direct connection (5 V withstand voltage input), D+ pin pullup output Supports all transfer type which is defined in the USB specification.(Control transfer / Bulk transfer / Interrupt

transfer / Isochronous transfer) Low power consumption operation (Average 15 mA at operation) Robust against signal distortion on USB transfer line due to SIE/DPLL(Digital Phase Lock Loop) of the original

design Easy making enumeration program and timing design because hardware manages the device state / control

transfer state (transition timing) Reduction of CPU load due to continuous transmit/receive mode (the mode for buffering several transaction data

into FIFO) This enables high performance and throughput improvement. Up to 7 endpoints (EP0 to EP6) selectable Data transfer condition selectable for each endpoint (EP1 to EP6)

Compatible to various applications (device class) Data transfer type (Bulk transfer / Isochronous transfer / Interrupt transfer) Transfer direction (IN, OUT) Packet size

Built-in FIFO buffer (3 Kbytes) for endpoints Buffering conditions of FIFO memory settable per endpoint (EP1 to EP6)

FIFO buffer size (up to 1Kbyte)Presence/Absence of double buffer configuration (setting of buffer size x 2)

Four pieces of configurable FIFO portsEndpoint number allocationAccess method switching (CPU, DMAC) Bit width (8-bit / 16-bit)Endian switching

Interrupt queuing function that eliminates the need of complicated factor analysis Connectable to various CPU/DMAC

Bus width(8-bit / 16-bit) Interface voltage(2.7V to 5.5V)Interrupt signal and DMA control signal polarities settable Supports multi-word DMA (burst)

FIFO access cycle of maximum 24 Mbytes/sec

Applications

Support all PC peripheral built-in USB

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Figure 1.1-1 M66291GP Pin Configuration

36

35

34

33

32

31

30

29

28

27

26

25

13

14

15

16

17

18

19

20

21

22

23

24

1 2 3 4 5 6 7 8 9101112

48

47

46

45

44

43

42

41

40

39

38

37

CorePowerSupply

USBDATA(-)

USBDATA(+)

VbusINPUT

TrONOUTPUT

TESTINPUT

DMAACKNOWLEDGE1

DMAREQUEST1

TCINPUT

INTERRUPT1/SOFOUTPUT

I/OPOWERSUPPLY

GND

IOVcc

D11/P3

D10/P2

D9/P1

D8/P0

D7

D6

D5

D4

D3

D2

D12/P4

D13/P5

D14/P6

D15/A0

HWR/BYTE

INT0

RD

LWR

CS

RST

Dreq0

Dack0

HIGH-WRITE STROBE/BUS WIDTH SELECT

INTERRUPT 0

READ STROBE

LOW-WRITE STROBE

CHIP SELECT

RESET

DMA REQUEST 0

DMA ACKNOWLEDGE 0

DATABUS

DATABUS

I/OPOWER

SUPPLY

D1

D0

A6

A5

A4

A3

A2

A1

CoreVcc

GND

Xin

Xout

DATA BUS

CORE POWER SUPPLY

OSCILLATION INPUT

OSCILLATION OUTPUT

ADDRESS BUS

CoreVcc

GNDD

-D+

Vbus

TrON

TEST

Dack1

Dreq1

TC1

INT1/SOF

IOVcc

M66291GP

PINCONFIGURATION(TOPVIEW)

OutlineM66291GP: 48P6Q-

A(LQFP)

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39

38

37

36

35

34

33

32

31

30

29

28

14

15

16

17

18

19

20

21

22

23

24

25

1 2 3 4 5 6 7 8 9 10

11

12

51

50

49

48

47

46

45

44

43

42

41

40

GND

IOVcc

D11/P

3

D10/P

2

D9/P1

D8/P0

D7

D6

D5

D4

D3

D2

NC

D12/P4

D13/P5

D14/P6

D15/A0

HWR/BYTE

INT0

RD

LWR

CS

RST

Dreq0

Dack0

NC

D1

D0

A6

A5

A4

A3

A2

A1

CoreVcc

GND

Xin

Xout

NC

CoreVcc

GNDD

-D+

Vbus

TrON

TEST

Dack1

Dreq1

TC1

INT1/SOF

IOVcc

NC

M66291HP

PIN CONFIGURATION(TOP VIEW)

OutlineM66291HP:52PJV(VQFN)

26

13

27

52

Figure1.1-2 M66291HP Pin Configuration

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1.2 Block Diagram

The M66291 contains an USB-IP block, an I/O block, a bus interface unit (BIU), and a FIFO memory.

Figure 1.2 M66291 Block Diagram

USB-IPI/O Block BusInterface

Unit(BIU)

EndpointController

FIFO Memory Controller

VbusInput Circuit

D+ Pin PullupCircuit

USBTransceiver

Serial InterfaceEngine(SIE)

(Oscillator)XinXout

Bus Interface PinsA1-6D0-7D8-15CSRDLWRHWR

Interrupt PinsINT0INT1/SOF

DMA Control PinsDreq0Dack0Dreq1Dack1TC1

Reset PinsRST

Test PinsTEST

OscillationBuffer

/48MHzPLL

FIFO Memory

CPU Interface Register

TransferController

(USB Power Supply)Vbus

(Pullup Resistance)TrON

(USB Data)D+D-

Interrupt Controller

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1.2.1 USB-IP

The USB-IP block contains a serial interface engine, a transfer controller, an endpoint controller, a FIFO

memory controller, an interrupt controller, and a CPU interface register.

(1) Serial Interface Engine (SIE)

The serial interface engine (SIE) executes low-order protocols processing of USB as follows: Extracts receive data/clock and generates transmit clock Serial - parallel conversion of transmit/receive data NRZI (Non Return Zero Invert) encoding and decoding Bit stuffing and destuffing SYNC (Synchronization pattern) and EOP (End Of Packet) detection USB address and endpoint detection CRC (Cyclic Redundancy Check) generation and checking

(2) Transfer Controller

The transfer controller executes device state transition control and control transfer sequence control.

(3) Endpoint Controller

The endpoint controller executes status control per endpoint.

(4) FIFO Memory Controller

The FIFO memory controller controls the write/read of the transmit/receive data at SIE (USB bus) side and

internal bus (CPU bus) side under state control by the endpoint controller.

(5) Interrupt Controller

The interrupt controller outputs the status signals outputted by transfer controller and endpoint controller to

INT0, INT1/SOF interrupt pins according to the CPU interface register setting.

(6) CPU Interface Register

The CPU interface register block is composed of the registers for mode setting, command setting and status

reading.

1.2.2 Bus Interface Unit (BIU)

The bus interface unit (BIU) is a circuit to conform USB-IP to LSI external bus.

1.2.3 FIFO Memory

The FIFO memory is a FIFO for endpoint transmit/receive. It is possible to set 6 endpoints EP1 to EP6 in

addition to EP0, the endpoint for control transfer.

1.2.4 I/O Block

The I/O block is composed of USB transceiver, oscillation buffer, 48 MHz PLL, Vbus input circuit and D+ pin

pullup control circuit.

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(1) USB Transceiver

The USB transceiver, conforming to the USB Specification Revision 2.0, is composed of a pair of 2 pieces of

drivers D+/D- complying with full speed transfer mode, a pair of 2 pieces of single end receivers and a

differential input receiver. A serial resistance for impedance matching is needed external to the chip.

(2) Oscillation Buffer, 48 MHz PLLThe 48 MHz clock with accuracy 0.25% is needed at the USB-IP block. The M66291 has a built-in oscillation

buffer and a 48 MHz PLL. The PLL is capable of setting the multiplication number depending on the program

and can therefore be connected with an external oscillation of 6, 12 or 24 MHz. Further, it can also be operated

by the external 48 MHz clock without using the PLL function.

(3) Vbus Input Circuit, D+ Pin Pullup Control Circuit

The M66291 is capable of learning the connection status with host/hub by means of Vbus pin, and can inform

the state of preparation at device side to host/hub by turning on/off the 1.5 K D+ pin pullup.

The Vbus input buffer which is 5 V tolerant can be directly connected to the Vbus pin on the USB bus.

The current from TrON pin is supplied by Vbus input. Since the D+/D- pins of USB bus are operated at 0 V to

3.3 V, the TrON pin reduces the voltage to 3.3 V before output.

Since the USB is constantly pulled down by 15 K at host/hub side when connected electrically, a current of 0.2

mA continuously flows into the D+ pin through the pullup resistance.

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1.3 Pin Functions

Item Pin name Input/

Output

Function Pin

Count

D7~D0 Input/

Output

Data Bus

This is a data bus to access the register from the system bus.

8

D14/P6~

D8/P0

Input/

Output

Data Bus / Port Signal

P6 to P0 are used as port signals when selected to 8-bit bus interface.

D14 to D8 are used as data signals when selected to 16-bit bus interface.

7

D15/A0 Input/

Output

D15 Signal / A0 Signal

A0 (LSB) is used as an address signal when selected to 8-bit bus interface.

D15 (MSB) is used as an data signal when selected to 16-bit bus interface.

1

A6~A1 Input Address Bus

This is an address bus to access the register from the system bus.

6

*CS Input Chip Select"L" level enables communication with the M66291.

1

*LWR Input Low-write Strobe

The lower data (D7 to D0) is written to the register at L level.

1

*HWR/*BYTE Input High-write Strobe / Bus Width Select

With the reset signal set to H level, the 8-bit bus interface is selected if this

pin is at L level. Further, if this pin is at H level, the 16-bit bus interface is

selected. When the 16-bit bus interface is selected, the upper data (D15 to

D8) is written to the register at L level.

Fix to L level when set to 8-bit bus interface.

1

Bus

interface

*RD Input Read Strobe

Data are read from registers at "L" level

1

*INT0

(Note 1)

Output Interrupt 0

Interrupts are requested to the system at "L" level.

1Interrupt

interface

*INT1/*SOF

(Note 1)

Output Interrupt 1 / SOF Output

This pin is used as an interrupt 1 or as a SOF output pin to transmit USB SOF

signal according to register setting.

1

DMA

interface

*Dreq0

(Note 1)

Output DMA Request 0

This pin is used to request DMA transfer to endpoint FIFO for DMA channel 0.

1

*Dack0

(Note 1)

Input DMA Acknowledge 0

This pin enables access of FIFO by DMA transfer for DMA channel 0.

1

*Dreq1

(Note 1)

Output DMA Request 1

This pin is used to request DMA transfer to endpoint FIFO for DMA channel 1.

1

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Item Pin Name Input/

Output

Function Pin

Count

*Dack1

(Note1)

Input DMA Acknowledge 1

This pin enables access of FIFO by DMA transfer for DMA channel 1.

1DMA

interface

*TC1 Input Terminal Count 1This pin indicates the final transfer cycle at L level for DMA channel 1.

This is valid only in write cycle. Set to H level when not used.

1

D+ Input/

Output

USB Data (+)

D+ of USB. Connect an external resistance in series.

1

D- Input/

Output

USB Data (-)

D- of USB. Connect an external resistance in series.

1

Vbus Input Vbus Input (with built-in pulldown resistance)

Connect to the Vbus of USB bus or to the 5V power supply.

Connection or shutdown of the Vbus can be detected.

1

USB

interface

TrON Output TrON Output

This pin is connected to the D+ pullup resistance of 1.5 K.

This pin is used to control ON/OFF of the pullup resistance.

1

*RST Input Reset

This pin is used to initialize the values of the internal register or the counter at

"L" level.

1

Xin Input Oscillator

Input

1

Xout Output Oscillator

Output

These pins are used to input/output the signals of internal clock

oscillation circuits. Connect a crystal unit between Xin and Xout

pins.

If an external clock signal is used, connect it to the Xin pin and

leave the Xout pin open.

1

TEST Input TEST Input (with built-in pulldown resistance)

This pin is input for the test. Set to "L" level or keep open.

1

CoreVcc

(Note 2)

Core Power Supply

These pins are used as the power source for internal logic, FIFO memory, PLL

circuit, USB transceiver and oscillation buffer.

2

IOVcc

(Note 3)

I/O Power Supply 2

Others

GND Ground 3

A pin preceded by an asterisk "*" is an active low pin.

(Example: *CS pin is an active low, CS)

Note 1: The polarities of *Dreq, *Dack, *INT, and *SOF pins can be changed by the internal registers.

Note 2: The Xin, Xout, Vbus, D+ and D- pins are all driven by CoreVcc.

Note 3: The pins for bus interface, interrupt, DMA control, reset and test are all driven by IOVcc. See Figure 1.2.

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M66291GP/HP

2Registers

How to Read Register Tables

Bit Numbers : Each register is connected with an internal bus of 16-bit wide, so the bit numbers of the

registers located at odd addresses are b15-b8, and those at even addresses are b7-b0.

State of Register at Reset :

Represents the initial state of each register immediately after reset with hexadecimal numbers.

The "H/W reset" is the reset by an external reset signal; the "S/W reset" is the reset by the

USBE bit of the USB Operation Enable Register.

At Read: ... Read enabled

? ... Read disabled (Read value invalid)

0 ... Read always as 0

1 ... Read always as 1

At Write: ... Write enabled

... Write enable conditionally (includes some conditions at write)

... Write disabled (Dont care 0 and 1 at write)

X Write disabled

Not implemented in the shaded portion.

b15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 b0

Abit Bbit Cbit

H/W reset 0 0 0 0S/W reset 0 0 0 0

USB bus reset 0 0 0 0

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The M66291 register mapping is shown in Figure 2.1 and Figure 2.2, and each register is described below.

Address +1 address +0 address Reset state

b15 b8 b7 b0 H/W S/W USB bus

H00 USB Operation Enable Register H'0000 - -

H02 Remote Wakeup Register H'0000 H'0000 -

H04 Sequence Bit Clear Register H'0000 H'0000 -

H06 (Reserved)

H08 USB_Address Register H'0000 H'0000 H'0000

H0A Isochronous Status Register H'0000 H'0000 -

H0C SOF Control Register H'0000 H'0000 -

H0E Polarity Set Register H'0000 H'0000 -

H10 Interrupt Enable Register 0 H'0000 H'0000 -

H12 Interrupt Enable Register 1 H'0000 H'0000 -

H14 Interrupt Enable Register 2 H'0000 H'0000 -

H16 Interrupt Enable Register 3 H'0000 H'0000 -

H18 Interrupt Status Register 0 H'0000 H'0000 Note

H1A Interrupt Status Register 1 H'0000 H'0000 -

H1C Interrupt Status Register 2 H'0000 H'0000 -

H1E Interrupt Status Register 3 H'0000 H'0000 -

H20 Request Register H'0000 H'0000 -

H22 Value Register H'0000 H'0000 -

H24 Index Register H'0000 H'0000 -

H26 Length Register H'0000 H'0000 -

H28 Control Transfer Control Register H'0000 - -

H2A EP0 Packet Size Register H'0008 - -

H2C Automatic Response Control Register H'0000 - -

H2E (Reserved)

H30 EP0_FIFO Select Register H'0000 - -

H32 EP0_FIFO Control Register H'0800 - -

H34 EP0_FIFO Data Register ???? - -

H36 EP0_FIFO Continuous Transmit Data Length Register H'0000 - -

Note : Refer to each register described below.

Figure 2.1 Register Mapping (1)

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Address +1 address +0 address Reset state

b15 b8 b7 b0 H/W S/W USB bus

H38 (Reserved)

H3A (Reserved)

H3C (Reserved)

H3E (Reserved)

H40 CPU_FIFO Select Register H'0000 - -

H42 CPU_FIFO Control Register H'0800 - -

H44 CPU_FIFO Data Register ???? - -

H46 SIE_FIFO Status Register H'0000 - -

H48 D0_FIFO Select Register H'0000 - -

H4A D0_FIFO Control Register H'0800 - -

H4C D0_FIFO Data Register ???? - -

H4E DMA0_Transaction Count Register H'0000 - -

H50 D1_FIFO Select Register H'0000 - -

H52 D1_FIFO Control Register H'0800 - -

H54 D1_FIFO Data Register ???? - -

H56 DMA1_Transaction Count Register H'0000 - -

H58 FIFO Status Register H'0000 H'0000 -

H5A Port Control Register H'0000 - -

H5C Port Data Register H'0000 - -

H5E Drive Current Adjust Register H'0000 - -

H60 EP1 Configuration Register 0 H'0000 - -

H62 EP1 Configuration Register 1 H'0040 - -

H64 EP2 Configuration Register 0 H'0000 - -

H66 EP2 Configuration Register 1 H'0040 - -

H68 EP3 Configuration Register 0 H'0000 - -

H6A EP3 Configuration Register 1 H'0040 - -

H6C EP4 Configuration Register 0 H'0000 - -

H6E EP4 Configuration Register 1 H'0040 - -

H70 EP5 Configuration Register 0 H'0000 - -

H72 EP5 Configuration Register 1 H'0040 - -

H74 EP6 Configuration Register 0 H'0000 - -

H76 EP6 Configuration Register 1 H'0040 - -

Figure 2.2 Register Mapping (2)

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2.1 USB Operation Enable Register

USB Operation Enable Register (USB_ENABLE)

b15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 b0

XCKE PLLC Xtal SCKE USBPC Tr_on USBE0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

- - - - - - - - - - - - - - - -

- - - - - - - - - - - - - - - -

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(3) Xtal (Clock Select) Bits (b13~b12)

These bits set the multiplication factor of the external clock into PLL.Since it is necessary to supply 48 MHz to the core block, the setting values of these bits are determined by theclock frequency to be input into the PLL.Refer to Figure 2.3.

(4) SCKE (Internal Clock Enable) Bit (b11)This bit sets the clock supply into the core block.Set the PLLC bit to 1 and wait until the oscillation of the PLL stabilizes before setting this bit to 1.Refer to Figure 2.3.

Oscillationbuffer

XCKE bit

PLLExternal clock

PLLC bit

Enable/Disable

SCKE bit

Xtal bits

Multiplyingfactor

Core blockI/O block

Enable/Disable

Figure 2.3 Clock Control(5) USBPC (USB Transceiver Power Control) Bit (b10)

This bit sets the enable/disable of the USB transceiver block of I/O block.Even if this bit is set to 0, it is possible to receive the resume signal during the Suspended state (DVSQ bits= 1xx). It is necessary that the Tr_on bits be set to x1 (during operation of SIE block).

(6) Tr_on (Tr_on Output Control) Bits (b9~b8)

These bits set the TrON signal output from I/O block and the enable/disable of SIE block in core block.

(7) USBE (USB Module Operation Enable) Bit (b0)

This bit sets S/W reset.When this bit is set to 0, the M66291 enters the S/W reset state and the registers are set to their S/W resetstate..

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2.2 Remote Wakeup Register

Remote Wakeup Register (REMOTE_WAKEUP)

b15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 b0

WKUP0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

- - - - - - - - - - - - - - - -

b Bit name Function R W

15~1 Reserved. Set it to 0. 0 0

0 WKUP

Remote Wakeup

Read

0 : Do not output the remote wakeup signal

1 : Output the remote wakeup signal

Write

0 : Invalid (Ignored when written)

1 : Output the remote wakeup signal

(1) WKUP (Remote Wakeup) Bit (b0)

This bit controls the output of the remote wakeup signal (K state output).This bit is valid only when the device state is suspend (DVSQ bits = 1xx). The writing of 1 to this bit isignored when the device state is not suspend.When 1 is written to this bit, the K state is output for 10 ms. The bit is automatically cleared to 0 after Kstate output.The bus idle state continues (this WKUP bit = 1) for 2 ms after the Suspend state isdetected when 1 iswritten to this bit before outputting the K state for 10 ms.The 2 ms and 10 ms time intervals are counted using a clock. Make sure that the counting stops if the clock isnot supplied (Note).

Note : SCKE bit = 0 when XCKE bit = 1 , or XCKE bit = 0.

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2.3 Sequence Bit Clear Register

Sequence Bit Clear Register (SEQUENCE_BIT)

b15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 b0

SQCLR0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

- - - - - - - - - - - - - - - -

b Bit name Function R W

15~7 Reserved. Set it to 0. 0 0

6~0 SQCLR

Sequence Bit Clear

Write

0 : Invalid (Ignored when written)

1 : Clear Sequence bit

b6 corresponds to EP6, ---b1 corresponds to EP1 and b0

corresponds to EP0.

0

(1) SQCLR (Sequence Bit Clear) Bits (b6~b0)

These bits clear the sequence bit (the bit controlled by H/W) and turns the data PID into DATA 0 PID.This bit immediately returns to 0 after writing 1.In the transfers after the sequence bit is cleared, the sequence bit is toggled through H/W control.At S/W reset(USBE bit = 1) and USB bus reset, the sequence bit of each endpoint is not cleared.

Note : Be sure to set the response PID of the endpoint whose sequence bit is desired to be cleared to NAK (EP0_PIDbits = 00/EPi_PID bits = 00) before writing 1 to this bit.

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2.4 USB_Address Register

USB_Address Register (USB_ADDRESS)

b15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 b0

USB_Addr0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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2.5 Isochronous Status Register

Isochronous Status Register (ISOCHRONOUS_STATUS)

b15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 b0

FMOD FRNM0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

- - - - - - - - - - - - - - - -

b Bit name Function R W

15~12 Reserved. Set it to 0. ? 0

11 FMOD

Frame Number Mode

0 : At SOF receive

1 : At Isochronous transfer complete

10~0 FRNM

Frame Number

Stores the frame number

This register is valid only for isochronous transfer. In other words, the register is valid status for the endpoint

that is set EPi_TYP bits to 11.

(1) FMOD (Frame Number Mode) Bit (b11)

This bit sets the storage timing of the frame number to be stored to the FRNM bits.When this bit is set to 0, when the SOF packet is properly received, the frame number of the received SOFpacket gets stored.When this bit is set to 1, when the isochronous packet transfer completes, the frame number of the properlyreceived SOF packet gets stored.

(2) FRNM (Frame Number) Bits (b10~b0)

The frame number is stored in the FRNM with the timing set by the FMOD bit of this register. Here, theSOFR bit is set to 1.

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2.6 SOF Control Register

SOF Control Register (SOF_CNT)

b15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 b0

SOFOE SOFA0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

- - - - - - - - - - - - - - - -

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2.7 Polarity Set Register

Polarity Set Register (POLARITY_CNT)

b15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 b0

VB01 RM01 SF01 DS01 CT01 BE01 NR01 RD01 RDYM INTL INTA0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

- - - - - - - - - - - - - - - -

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(6) BE01 (Buffer Empty/Size Over Error Interrupt Assign) Bit (b10)

This bit selects the pin to output the buffer empty/size over error interrupt signal.

(7) NR01 (Buffer Not Ready Interrupt Assign) Bit (b9)

This bit selects the pin to output the buffer not ready interrupt signal.

(8) RD01 (Buffer Ready Interrupt Assign) Bit (b8)

This bit selects the pin to output the buffer ready interrupt signal.

(9) RDYM (Buffer Ready Mode) Bit (b2)

This bit selects the method of clearing the buffer ready interrupt.When this bit is set to 0, the EPB_RDY bit is cleared to 0 after the CPU side buffer data are all read out orafter the writing of transmit data completes.When this bit is set to 1, the EPB_RDY bit is cleared to 0 by writing 0 to the EPB_RDY bit.For details, refer to EPB_RDY bit.

Note : Refer to 3.2 FIFO Buffer for CPU/SIE side.

(10) INTL (Interrupt Output Sense) Bit (b1)This bit sets the sense mode for interrupt output from INT0 or INT1 pin.When this bit is set to 0, the INT0 or INT1 pin notifies the occurrence of interrupt at the edge set by theINTA bit.During edge sensitive output, when 0 is written to each interrupt factor bit to clear the interrupt, the outputsignal outputs the negate value one time. If the other interrupt factor bits are set to 1, the occurrence ofinterrupt again is notified at the edge. The negate period is equivalent to 32 clocks (approx. 667 ns) of the 48MHz clock.In case the clock is not supplied (Note), the negate period does not occur. Make sure not to miss the interruptwhen Vbus interrupt or resume interrupt occurs.When this bit is set to 1, the INT0 or INT1 pin notifies the occurrence of interrupt at the level set by theINTA bit.During level sensitive output, the negate fails to work unless all interrupt factor bits are cleared even if 0 iswritten to clear the interrupt to the interrupt factor bits.Refer to Figure 2.5 and 3.1 Interrupt Function.

Note : SCKE bit = 0 when XCKE bit = 1 , or XCKE bit = 0.

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Interrupt factor 1("H" active)

Negate period(Approx.667ns)

Factor 1 occur

Factor 1 clearFactor 2 occur Factor 2 clear

Interrupt factor 2("H" active)

Interrupt pin("L" active)

Interrupt factor 1("H" active)

Factor 1 occur

Factor 1 clearFactor 2 occur Factor 2 clear

Interrupt factor 2("H" active)

Interrupt pin("L" active)

Figure 2.5 Interrupt Signal Output Timing(11) INTA (Interrupt Polarity) Bit (b0)

This bit sets the interrupt signal output polarity.When this bit is set to 0, the occurrence of interrupt is notified when;

In case of edge sense (INTL bit = 0) : Change from H to LIn case of level sense (INTL bit = 1) : L level

When this bit is set to 1, the occurrence of interrupt is notified when;In case of edge sense (INTL bit = 0) : Change from L to HIn case of level sense (INTL bit = 1) : H level

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2.8 Interrupt Enable Register 0

Interrupt Enable Register 0 (INT_ENABLE0)

b15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 b0

VBSE RSME SOFE DVSE CTRE BEMPE INTNE INTRE URST SADR SCFG SUSP WDST RDST CMPL SERR0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

- - - - - - - - - - - - - - - -

b Bit name Function R W

15 VBSE

Vbus Interrupt Enable

0 : Disable interrupt

1 : Enable interrupt

(Interrupt occurs when VBUS bit is set to 1)

14 RSME

Resume Interrupt Enable

0 : Disable interrupt

1 : Enable interrupt

(Interrupt occurs when RESM bit is set to "1")

13 SOFE

SOF Detect Interrupt Enable

0 : Disable interrupt

1 : Enable interrupt(Interrupt occurs when SOFR bit is set to "1")

12 DVSE

Device State Transition Interrupt Enable

0 : Disable interrupt

1 : Enable interrupt

(Interrupt occurs when DVST bit is set to "1")

11 CTRE

Control Transfer Transition Interrupt Enable

0 : Disable interrupt

1 : Enable interrupt

(Interrupt is occurs when CTRT bit is set to "1")

10 BEMPE

Buffer Empty/Size Over Error Interrupt Enable

0 : Disable interrupt

1 : Enable interrupt

(Interrupt is occurs when BEMP bit is set to "1")

9 INTNE

Buffer Not Ready Interrupt Enable

0 : Disable interrupt

1 : Enable interrupt(Interrupt occurs when INTN bit is set to "1")

8 INTRE

Buffer Ready Interrupt Enable

0 : Disable interrupt

1 : Enable interrupt

(Interrupt occurs when INTR bit is set to "1")

7 URST

USB Reset Detect

0 : Disable DVST bit set

1 : Enable DVST bit set

6 SADR

SET_ADDRESS Execute

0 : Disable DVST bit set

1 : Enable DVST bit set

5 SCFG

SET_CONFIGURATION Execute

0 : Disable DVST bit set

1 : Enable DVST bit set

4 SUSP

Suspend Detect

0 : Disable DVST bit set

1 : Enable DVST bit set

3 WDST

Control Write Transfer Status Stage

0 : Disable CTRT bit set

1 : Enable CTRT bit set

2 RDST

Control Read Transfer Status Stage

0 : Disable CTRT bit set

1 : Enable CTRT bit set

1 CMPL

Control Transfer Complete

0 : Disable CTRT bit set

1 : Enable CTRT bit set

0 SERR

Control Transfer Sequence Error

0 : Disable CTRT bit set

1 : Enable CTRT bit set

This register sets enable of interrupt and enable/disable of setting DVST and CTRT bits to 1.Also refer to 3.1 Interrupt Function.

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(1) VBSE (Vbus Interrupt Enable) Bit (b15)

This bit sets enable/disable of Vbus interrupt.When this bit is set to 1, the interrupt occurs if VBUS bit is set to 1.This bit is capable of writing/reading even if the clock is not supplied (Note).

Note : At SCKE bit = 0 when XCKE bit = 1 or XCKE bit = 0.

(2) RSME (Resume Interrupt Enable) Bit (b14)

This bit sets enable/disable of resume interrupt.When this bit is set to 1, the interrupt occurs if RESM bit is set to 1.This bit is capable of writing/reading even if the clock is not supplied (Note).

Note : At SCKE bit = 0 when XCKE bit = 1 or XCKE bit = 0.

(3) SOFE (SOF Detect Interrupt Enable) Bit (b13)

This bit sets enable/disable of SOF detect interrupt.When this bit is set to 1, the interrupt occurs if SOFR bit is set to 1.

(4) DVSE (Device State Transition Interrupt Enable) Bit (b12)

This bit sets enable/disable of device state transition interrupt.When this bit is set to 1, the interrupt occurs if DVST bit is set to 1.The Conditions the DVST bit set are depend on the URST, SADR, SCFG or SUSP.

(5) CTRE (Control Transfer Transition Interrupt Enable) Bit (b11)

This bit sets enable/disable of control transfer transition interrupt.When this bit is set to 1, the interrupt occurs if CTRT bit is set to 1.The Conditions the DVST bit set are depend on the WDST, RDST, CMPL or SERR.The complete of setup stage can not set enable/disable to set CTRT bit to 1.

(6) BEMPE (Buffer Empty/Size Over Error Interrupt Enable) Bit (b10)

This bit sets enable/disable of buffer empty/size over error interrupt.When this bit is set to 1, the interrupt occurs if BEMP bit is set to 1.

(7) INTNE (Buffer Not Ready Interrupt Enable) Bit (b9)

This bit sets enable/disable of buffer not ready interrupt.When this bit is set to 1, the interrupt occurs if INTN bit is set to 1.

(8) INTRE (Buffer Ready Interrupt Enable) Bit (b8)

This bit sets enable/disable of buffer ready interrupt.When this bit is set to 1, the interrupt occurs if INTR bit is set to 1.

(9) URST (USB Reset Detect) Bit (b7)

This bit selects whether to set the DVST bit to 1 or not at the USB bus reset detection.The register is initialized by the USB reset detection, irrespective of the value of this bit.

(10) SADR (SET_ADDRESS Execute) Bit (b6)

This bit selects whether to set the DVST bit to 1 or not at the SET_ADDRESS execution.For details, refer to DVST bit.

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(11) SCFG (SET_CONFIGURATION Execute) Bit (b5)

This bit selects whether to set the DVST bit to 1 or not at the SET_ CONFIGURATION execution.For details, refer to DVST bit.

(12) SUSP (Suspend Detect) Bit (b4)

This bit selects whether to set the DVST bit to 1 or not at the suspend detection.

(13) WDST (Control Write Transfer Status Stage) Bit (b3)

This bit selects whether to set the CTRT bit to 1 or not when transited to status stage during control writetransfer.

(14) RDST (Control Read Transfer Status Stage) Bit (b2)

This bit selects whether to set the CTRT bit to 1 or not when transited to status stage during control readtransfer.

(15) CMPL (Control Transfer Complete) Bit (b1)

This bit selects whether to set the CTRT bit to 1 or not when the status stage completes during controltransfer.

(16) SERR (Control Transfer Sequence Error) Bit (b0)

This bit selects whether to set the CTRT bit to 1 or not when the sequence error is detected at controltransfer.

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2.9 Interrupt Enable Register 1

Interrupt Enable Register 1 (INT_ENABLE1)

b15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 b0

EPB_RE0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

- - - - - - - - - - - - - - - -

b Bit name Function R W

15~7 Reserved. Set it to 0. 0 0

6~0 EPB_RE

Buffer Ready Interrupt Enable

0 : Disable INTR bit set

1 : Enable INTR bit set

b6 corresponds to EP6, ---b1 corresponds to EP1 and b0

corresponds to EP0.

(1) EPB_RE (Buffer Ready Interrupt Enable) Bits (b6~b0)

These bits select whether to set the INTR bit to 1 or not when the EPB_RDY bit is set to 1.Also refer to 3.1 Interrupt Function.

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2.10 Interrupt Enable Register 2

Interrupt Enable Register 2 (INT_ENABLE2)

b15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 b0

EPB_NRE0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

- - - - - - - - - - - - - - - -

b Bit name Function R W

15~7 Reserved. Set it to 0. 0 0

6~0 EPB_NRE

Buffer Not Ready Interrupt Enable

0 : Disable INTN bit set

1 : Enable INTN bit set

b6 corresponds to EP6, ---b1 corresponds to EP1 and b0

corresponds to EP0.

(1) EPB_NRE (Buffer Not Ready Interrupt Enable) Bits (b6~b0)

These bits select whether to set the INTN bit to 1 or not when the EPB_NRDY bit is set to 1.Also refer to 3.1 Interrupt Function.

Note : Do not set the corresponding bit of this register to 1 when the endpoint is set to isochronous transfer (set byEPi _TYP bits).

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2.11 Interrupt Enable Register 3

Interrupt Enable Register 3 (INT_ENABLE3)

b15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 b0

EPB_EMPE0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

- - - - - - - - - - - - - - - -

b Bit name Function R W

15~7 Reserved. Set it to 0. 0 0

6~0 EPB_EMPE

Buffer Empty/Size Over Error Interrupt Enable

0 : Disable BEMP bit set

1 : Enable BEMP bit set

b6 corresponds to EP6, ---b1 corresponds to EP1 and b0

corresponds to EP0.

(1) EPB_EMPE (Buffer Empty/Size Over Error Interrupt Enable) Bits (b6~b0)

These bits select whether to set the BEMP bit to 1 or not when the EPB_EMP_OVR bit is set to 1.Also refer to 3.1 Interrupt Function.

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2.12 Interrupt Status Register 0

Interrupt Status Register 0 (INT_STATUS0)

b15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 b0

VBUS RESM SOFR DVST CTRT BEMP INTN INTR Vbus DVSQ VALID CTSQ0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

- - - 1 - - - - 0 0 0 1 - - - -

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b Bit name Function R W

7 Vbus

Vbus Level

Read

0 : "L"

1 : "H"

Write

Invalid (Ignored when written)

6~4 DVSQ

Device State

Read

000 : Powered state

001 : Default state

010 : Address state

011 : Configured state

1xx : Suspended state (Note)

Write

Invalid (Ignored when written)

3 VALID

Setup Packet Detect

Read

0 : No detection

1 : Receiving the setup packet

Write

0 : This VALID bit clear

1 : Invalid (Ignored when written)

2~0 CTSQ

Control Transfer Stage

Read

000 : Idle or setup stage

001 : Control read transfer data stage

010 : Control read transfer status stage

011 : Control write transfer data stage

100 : Control write transfer status stage

101 : Control write no data transfer status stage

110 : Control transfer sequence error

111 : Reserved

Write

Invalid (Ignored when written)

Note : x is a optional value.

The b15 to b8 of this register are interrupt status bits. When the bit of the Interrupt Enable Registercorresponding to these bits are set to 1 (interrupt enable), the interrupt occurs by setting these bits to 1.

(1) VBUS (Vbus Interrupt) Bit (b15)

This bit indicates the change of Vbus input.This bit is set to 1 (Vbus interrupt occurs) when the Vbus input changes (L->H or H->L).This bit is cleared to 0 by writing 0 (interrupt is cleared).This bit is set to 1 and can be read out even if the clock is not supplied (Note). This bit can also be cleared bywriting 0. In case the clock is not supplied, make sure to write 1 after writing 0 (no further interrupt willbe accepted).

Note : SCKE bit = 0 when XCKE bit = 1 , or XCKE bit = 0.

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(2) RESM (Resume Interrupt) Bit (b14)

This bit indicates the change of USB bus state.This bit is set to 1 when the USB bus state is changed from suspended (DVST bits = 1xx) to J->K orJ->SE0 (resume interrupt occurs).This bit is cleared to 0 by writing 0 (interrupt is cleared).This bit is set to 1 and can be read out even if the clock is not supplied (Note). This bit can also be cleared by

writing 0. In case the clock is not supplied, make sure to write 1 after writing 0 (no further interrupt willbe accepted).

Note : At SCKE bit = 0 when XCKE bit = 1 or XCKE bit = 0.

(3) SOFR (SOF Detect Interrupt) Bit (b13)

This bit indicates that the SOF packet is received and the frame number is updated.This bit is set to 1 when the SOF packet is received and the frame number is stored at the timing set by theFMOD bit of the Isochronous Status Register (SOF detect interrupt occurs).This bit is cleared to 0 by writing 0 (interrupt is cleared).

(4) DVST (Device State Transition Interrupt) Bit (b12)

This bit indicates the transition of the device state.

This bit is set to 1 when the transition of device states takes place as follows (device state transitioninterrupt occurs):

(A) USB bus reset detect (Arbitrary state -> Default state):When the SE0 state continues for 2.5 us or more in D+ and D- pins, the USB bus reset is detected,causing this bit to be set to 1.

(B) SET_ADDRESS execute (Default state -> Address state):This bit is set to 1 when the SET_ADDRESS request is detected as (a) and the response is madeby zero-length packet in status stage.

(a)SET_ADDRESS request in case device address value in default state is not 0:In case the wValue in default state is 0, this bit is not set to 1. When this request isreceived, the device address value is set to the USB_Address Register, irrespective of the

setting of this bit.

(C) SET CONFIGURATION execute (Address state -> Configured state):This bit is set to 1 when the requests below are detected and ACK is received after the responseis made through zero-length packet in status stage.

(a) SET_CONFIGURATION request in case configuration value in address state is not 0(b) SET_CONFIGURATION request in case configuration value in configured state is 0

(D)Suspend detect (Powered/Default/Address/Configured state -> Suspended state):The suspended state is detected and this bit is set to1 when the idle state continues for 3 ms ormore in D+ and D- pins.

The Conditions that this bit indicates "1" depend on the URST, SADR, SCFG or SUSP bits.

This bit is cleared to 0 by writing 0 (interrupt is cleared).The present device state can be confirmed by the DVSQ bits.

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(5) CTRT (Control Transfer Stage Transition Interrupt) Bit (b11)

This bit indicates the transition of stage in control transfers.This bit is set to 1 when the stage transition of control transfer takes place as follows (control transfer stagetransition interrupt occurs):Refer to Figure 2.7.

Setup Stage Complete (When transmitting ACK) Control Write Transfer Status Stage Transition (When receiving IN token) Control Read Transfer Status Stage Transition (When receiving OUT token) Control Transfer Complete (When transmitting or receiving ACK) Control Transfer Sequence Error (When error occurs)

The Conditions that this bit indicates "1" depend on the WDST, RDST, CMPL or SERR bits.This bit is cleared to 0 by writing 0 (interrupt is cleared).The present stage can be confirmed by the CTSQ bits.

(6) BEMP (Buffer Empty/Size Over Error Interrupt) Bit (b10)

This bit indicates the occurrence of buffer empty or buffer size over error.This bit is set to 1 when the EPB_EMP_OVR bit is set to 1 (buffer empty/buffer size over error interrupt

occurs).This bit is cleared by setting all the bits of Interrupt Status Register 3 to 0.For details, refer to Interrupt Status Register 3.

(7) INTN (Buffer Not Ready Interrupt) Bit (b9)

This bit indicates the NAK has been sent to the host because of the buffer not ready state.This bit is set to 1 when the EPB_NRDY bit is set to 1 (buffer not ready interrupt occurs).This bit is cleared by setting all the bits of Interrupt Status Register 2 to 0.For details, refer to Interrupt Status Register 2.

(8) INTR (Buffer Ready Interrupt) Bit (b8)

This bit indicates the buffer ready state (that can be read/written).This bit is set to 1 when the EPB_RDY bit is set to 1 (buffer ready interrupt occurs).

This bit is cleared by setting all the bits of Interrupt Status Register 1 to 0.For details, refer to Interrupt Status Register 1.

(9) Vbus (Vbus Level) Bit (b7)

This bit indicates the state of Vbus pin.When this bit changes, the VBUS bit is set to 1.This bit is capable of reading the correct value even if the clock is not supplied (Note).

Note : SCKE bit = 0 when XCKE bit = 1 , or XCKE bit = 0.

(10) DVSQ (Device State) Bits (b6~b4)

These bits indicate the present device states as follows:

000 : Powered State Power ON state001 : Default State USB bus reset detected state010 : Address State SET_ADDRESS request executed state011 : Configured State SET_CONFIGURATION request executed state1xx : Suspended State suspended detected state

Depending on the changes of these device states, the DVST bit and the RESM bit are set to 1 (setenable/disable by the URST, SADR, SCFG or SUSP bits). For details, refer to DVST bit and Figure 2.6.

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Powered

state

(DVSQ bits ="000")

SET_ADDRESS excecution

(W hen SADR bit="1", DVST bit is set to "1")

USB bus reset detection

(W hen URST bit="1", DVST bit is set to "1")

Resume (RESM bit is set to "1")

Default

state

(DVSQ bits="001")

Configured

state(DVSQ bits="011")

Suspended

state

(DVSQ bits="100")

Address

state

(DVSQ bits="010")

Suspended

state(DVSQ bits="111")

Suspended

state

(DVSQ bits="101")

Suspended

state

(DVSQ bits="110")

Suspend detection

(W hen SUSP bit="1", DVST bit is set to "1")

Resume (RESM bit is set to "1")

SET_CONF IGURATION excecution[ConfigurationValue=0]

(W hen SCFG bit="1", DVST bit is set to "1")

Suspend detection

(W hen SUSP bit="1", DVST bit is set to "1")

Resume (RESM bit is set to "1")

Suspend detection

(W hen SUSP bit="1", DVST bit is set to "1")

Suspend detection

(W hen SUSP bit="1", DVST bit is set to "1")

Resume (RESM bit is set to "1")

USB bus reset detection

(W hen URST bit="1", DVST bit is set to "1")

Note : The URST, SAD R, SCFG and SUSP bits (Interrupt Enable Register 0) in the parenthesis set enable/disable to set the DVST bit to "1" for the

corresp onding stage transition. There is no bit to set enable/disable to set the RES M bit to "1".

The stage transition takes place even if these bits are inhibited to set to "1".

SET_CO NFIGUR ATION excecution[ConfigurationValue= 0]

(W hen SCFG bit="1", DVST bit is set to "1")

/

Figure 2.6 Device State Transition(11) VALID (Setup Packet Detect) Bit (b3)

This bit indicates that the setup token has been received.When the setup token is completely received, this bit is set to 1.When this bit is set to 1, the writing to EP0_PID/CCPL bits of EP0_FIFO Control Register is ignored.At the time of receiving the setup token, the interrupt has not occurred (the interrupt occurs only after thetermination of setup stage).This bit is cleared to 0 by writing 0.

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(12) CTSQ (Control Transfer Stage) Bits (b2~b0)

These bits indicate the present stage in the control transfer. Refer to Figure 2.7.000 : Idle or Setup Stage001 : Control Read Transfer Data Stage010 : Control Read Transfer Status Stage011 : Control Write Transfer Data Stage

100 : Control Write Transfer Status Stage101 : Control Write No Data Transfer Status Stage110 : Control Transfer Sequence Error (refer to below)111 : Reserved

The control transfer sequence error is described below. When this error occurs, the EP0_PID bits are set to1x (stall state).

OUT token is received when data is never transferred against the IN token of the data stage. IN token is received at status stage. Data packet other than the zero-length packet is received at status stage.

IN token is received when ACK response is never made against the OUT token of the data

stage.

OUT token is received in status stage.

OUT token is received in status stage.

Data exceeding in size set by the EP0 Packet Size Register is received (the EPB_EMP_OVRbit of the Interrupt Status Register 3 is set to 1).

In case the amount of received data exceeds the wLength value in the request at the data stage of thecontrol write transfer, it is not recognized as the control transfer sequence error.

[CTSQ bits ="1xx"]

Control transfer

sequence error(Note)

ACK

receive

ACK transmit

ACK transmit

ACK transmit

Note : When the SERR bit is set to "1" and the control transfer sequence error causes the CTRT interrupt tooccur, the CTSQ bit values (1xx) are retained until "0" is written to the CTRT bit (interrupt is cleared).Further, even after the completion of the next set up stage, the CTRT interrupt due to the completionof the set up stage is not occurred until "0" is written to the CTRT bit.When the SERR bit is set to "0", if setup token is received, the CTSQ bits changes to "000".

Error detection

: CTRTinterrupt has occurred(1) Setup stage completion(2) Control read transfer

status stage transition(3) Control write transfer

status stage transition(4) Control transfer completion(5) Control transfer

sequence error

[CTSQ bits ="000"]

Setup stage

[CTSQ bits ="011"]

Control write

transfer

data stage

[CTSQ bits ="101"]

Control write

transfer no datastatus stage

ACK

transmit

[CTSQ bits ="010"]

Control read

transfer

status stage

[CTSQ bits="100"]

Control write

transfer

status stage

OUT token

receive

IN token receive

[CTSQ bits ="000"]

Idle stage

ACK

receive

[CTSQ bits ="001"]

Control read

transfer

data stage

Setup token receive

Setup token receive

(1)

Setup token receive

(1)

(1)

(3)

(2)

(5)

(4)

Figure 2.7 Control Transfer Transition

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2.13 Interrupt Status Register 1

Interrupt Status Register 1 (INT_STATUS1)

b15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 b0

EPB_RDY0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

- - - - - - - - - - - - - - - -

b Bit name Function R W

15~7 Reserved. Set it to 0. 0 0

6~0 EPB_RDY

Buffer Ready Interrupt

Read

0 : No occurrence of interrupt

1 : Occurrence of interrupt

Write

Invalid (Ignored when written)

0 : Clear interrupt clear

1 : Invalid (Ignored when written)

b6 corresponds to EP6, ---b1 corresponds to EP1 and b0

corresponds to EP0.

(1) EPB_RDY (Buffer Ready Interrupt) Bits (b6~b0)

The bit corresponding to each endpoint is set to 1 with the buffer at ready state.The ready state refers to the state when CPU or DMAC can read or write the CPU side buffer. When the EPB_REbit is set to 1, if this bit is set to 1, the INTR bit is set to 1, causing the buffer ready interrupt to occur.Setting 1/clearing to 0 to this bit differs according to the endpoint and transfer direction as shown below:

Note : Refer to 3.2 FIFO Buffer for CPU/SIE side.

Endpoint 0 When set to control write transfer (ISEL bit = 0)

The condition for this bit to be set to 1 is as follows: When the IVAL bit of the EP0_FIFO Control Register changes from 0 to 1

The condition for this bit to be cleared to 0 differs according to the RDYM bit: RDYM bit = 0 : When the IVAL bit of the EP0_FIFO Control Register changes from

1 to0 RDYM bit = 1 : Writes 0 to this bit

When set to control read transfer (ISEL bit = 1)This bit is not set to 1 (Refer to EPB_EMP_OVR bit).

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Endpoint 1~6

When set to OUT buffer (EPi_DIR bit = 0)The condition for this bit to be set to 1 is as follows:

When the IVAL bit of the endpoint changes from 0 to 1

When the buffer data including the received short packet (including the zero-lengthpacket) are all read out

The condition for this bit to be cleared to 0 differs according to the RDYM bit (Note): RDYM bit = 0 : When the IVAL bit of the endpoint changes from 1 to 0 RDYM bit = 1 : Writes 0 to this bit

Note : When the INTM bit at the endpoint specified by the DMA_EP bit is set to 0, the IVAL bit isretained to 1. Thus, it is necessary to write 1 to the BCLR bit and to clear the IVAL bit to0 when RDYM bit is set to 0. Even when the RDYM bit is set to 1, this bit can be clearedby writing 0. It is necessary to write 1 to the BCLR bit and to clear the IVAL bit.

When set to IN buffer (EPi_DIR bit = 1)The condition for this bit to be set to 1 is as follows:

When the IVAL bit of the endpoint changes from 1 to 0 Or when EPi_DER bit is changed from 0 to 1

This bit is not be set to 1.

The condition for this bit to be cleared to 0 differs according to the RDYM bits: RDYM bit = 0 : When the IVAL bit of the endpoint changes from 0 to 1 RDYM bit = 1 : Writes 0 to this bit

Note : The IVAL bit is located per endpoint. For details, refer to 3.2.4 IVAL Bit and EPB_RDY Bit.

OUT token Data packet ACK packet

USB bus SYNC PID Addr Endp CRC EOP SYNC PID Data CRC EOP SYNC PID EOP

Interrupt output Occurrence of buffer ready interrupt

because the buffer could be read

Figure 2.8 Examples of Buffer Ready Interrupt Occurrence Timing (OUT transfer)

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2.14 Interrupt Status Register 2

Interrupt Status Register 2 (INT_STATUS2)

b15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 b0

EPB_NRDY0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

- - - - - - - - - - - - - - - -

b Bit name Function R W

15~7 Reserved. Set it to 0. 0 0

6~0 EPB_NRDY

Buffer Not Ready Interrupt

Read

0 : No occurrence of interrupt

1 : Occurrence of interrupt

Write

0 : Clear interrupt

1 : Invalid (Ignored when written)

b6 corresponds to EP6, ---b1 corresponds to EP1 and b0corresponds to EP0.

(1) EPB_NRDY (Buffer Not Ready Interrupt) Bits (b6~b0)

The bit corresponding to each endpoint is set to 1 when IN token/OUT token is received with the buffer atnot ready state.The not ready state refers to the state when EP0_PID bits and EPi_PID bits are set to BUF/STALL responseand means that the buffer could not be received and transmitted.When this bit is set to 1, if the EP0_PID and EPi_PID bits are set to BUF, NAK response is executed, and ifthey are set to STALL, STALL response is executed.When the EPB_NRE bit is set to 1, if this bit is set to 1, the INTN bit is set to 1, causing the buffer notready interrupt to occur.This bit is cleared by writing 0.

Note: In case the endpoint is set to isochronous transfer (set by EPi_TYP bits), the corresponding bit of this registermay be set to 1. Hence, do not set the corresponding bit of the Interrupt Enable Register 2 to 1.

NAK/STALL

OUT token Data packet packet

USB bus SYNC PID Addr Endp CRC EOP SYNC PID Data CRC EOP SYNC PID EOP

Interrupt output Occurrence of buffer not ready interrupt

because the buffer could not be received

Figure 2.9 Examples of Buffer Not Ready Interrupt Occurrence Timing (OUT transfer)NAK/STALL

IN token packet

USB bus SYNC PID Addr Endp CRC EOP SYNC PID EOP

Interrupt output Occurrence of buffer not ready interrupt

because the buffer could not be transmitted

Figure 2.10 Examples of Buffer Not Ready Interrupt Occurrence Timing (IN transfer)

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2.15 Interrupt Status Register 3

Interrupt Status Register 3 (INT_STATUS3)

b15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 b0

EPB_EMP_OVR0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

- - - - - - - - - - - - - - - -

b Bit name Function R W

15~7 Reserved. Set it to 0. 0 0

6~0 EPB_EMP_OVR

Buffer Empty/Size Over Interrupt

Read

0 : No occurrence of interrupt

1 : Occurrence of interrupt

Write

0 : Clear interrupt

1 : Invalid (Ignored when written)

b6 corresponds to EP6, ---b1 corresponds to EP1 and b0corresponds to EP0.

(1) EPB_EMP_OVR (Buffer Empty/Size Over Interrupt) Bits (b6~b0)

These bits indicate that the received data size exceeds the maximum packet size or that the buffers of theendpoints 0 to 6 are empty.

Endpoint 0

When set to control write transfer (ISEL bit = 0)The condition for this bit to be set to 1 is as follows:

Receives packet data with size exceeding the one set by the EP0 Packet Size Register(Size-over detection).

In this case, the EP0_PID bits are set to STALL response.Further the CTRT bit sets to 1 if the SERR bit is set to 1.This bit is set to 1 when size-over is detected, irrespective of the EP0_PID bit setting.

When set to control read transfer (ISEL bit = 1)The condition for this bit to be set to 1 is as follows:

When the IVAL bit of the EP0_FIFO Control Register changes from 1 to 0. When transmit data exist in the buffer for EP0_FIFO and 1 is written to the BCLR bit.

Endpoint 1~6When set to OUT buffer (EPi_DIR bit = 0)

The condition for this bit to be set to 1 is as follows: Receives packet data with size exceeding the one set by the EPi_MXPS bits

(Size-over detection).The EPi_PID bits are set to STALL response.This bit isnt set to 1 at isochronous transfer.

This bit is set to 1 when size-over is detected, irrespective of the EP0_PID bit setting.

When set to IN buffer (EPi_DIR bit = 1)The condition for this bit to be set to 1 is as follows:

When the data of SIE side buffer are all transmitted with the data not written to the CPUside buffer (Buffer empty).

The conditions for this bit to be cleared to 0 in all bits are as follows: Writes 0 to this bit.

Note: Refer to 3.2 FIFO Buffer for CPU/SIE side.

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2.16 Request Register

Request Register (REQUEST_TYPE)

b15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 b0

bRequest bmRequestType0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

- - - - - - - - - - - - - - - -

b Bit name Function R W

15~8 bRequest

Request

Read

Request received in the setup stage

Write

Invalid (Ignored when written)

7~0 bmRequestType

Request Type

Read

Request type received in the setup stage

Write

Invalid (Ignored when written)

(1) bRequest (Request) Bits (b15~b8)

These bits store the bRequest of the device request received in the setup stage of the control transfer.

(2) bmRequestType (Request Type) Bits (b7~b0)

These bits store the bmRequestType of the device request received in the setup stage of the control transfer.

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2.17 Value Register

Value Register (REQUEST_VALUE)

b15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 b0

wValue0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

- - - - - - - - - - - - - - - -

b Bit name Function R W

15~0 wValue

Value

Read

Parameter of device request received in the setup stage

Write

Invalid (Ignored when written)

(1) wValue (Value) Bits (b15~b0)

These bits store the wValue of the device request received at the setup stage of the control transfer.

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2.18 Index Register

Index Register (REQUEST_INDEX)

b15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 b0

wIndex0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

- - - - - - - - - - - - - - - -

b Bit name Function R W

15~0 wIndex

Index

Read

Parameter of device request received in the setup stage

Write

Invalid (Ignored when written)

(1) wIndex (Index) Bits (b15~b0)

These bits store wIndex of the device request received in the setup stage of the control transfer.

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2.19 Length Register

Length Register (REQUEST_LENGTH)

b15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 b0

wlength0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

- - - - - - - - - - - - - - - -

b Bit name Function R W

15~0 wlength

Length

Read

Parameter of device request received in the setup stage

Write

Invalid (Ignored when written)

(1) wlength (Length) Bits (b15~b0)

These bits store the wlength of the device request received at the setup stage of the control transfer.

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2.20 Control Transfer Control Register

Control Transfer Control Register (CONTROL_TRANSFER)

b15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 b0

CTRR Ctr_Rd_Buf_Nmb CTRW Ctr_Wr_Buf_Nmb0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

- - - - - - - - - - - - - - - -

- - - - - - - - - - - - - - - -

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(3) CTRW (Control Write Transfer Continuous Receive Mode) Bit (b7)

This bit sets the receive mode at data stage of the control write transfer.In case of unit receive mode, the receive completes after receiving one packet under the condition as follows:

Receives the data equivalent to the size set by the EP0 Packet Size Register. Receives a short packet.

In case of continuous receive mode, the receipt completes after receiving several packets under the condition

as follows: Receives automatically the data equivalent to the size set by the EP0 Packet Size Register severaltimes and receives the data equivalent to 256 bytes.

Receives the short packet.

The setting conditions of the IVAL bit of the EP0_FIFO Control Register change due to this bit.

(4) Ctr_Wr_Buf_Nmb (Control Write Buffer Start Number) Bits (b5~b0)

These bits set the beginning? block number of the buffer to be used in control write transfer. The block numberis a number for control by dividing the FIFO buffer into 64 byte sections (Note 1).When the mode is set to unit receive (CTRW bit = 0), the blocks set by these bits only are used and, from thefollowing block, it is possible to set to the buffer of a different endpoint.When the mode is set to continuous receive (CTRW bit = 1), the buffer equivalent to 256 bytes is used from

the block numbers set by these bits (Note 2).Note 1: The M66291 is equipped with 3 Kbytes FIFO buffer and has blocks from H0 to H2F.Note 2: Make sure that several endpoints do not get overlapped in the same buffer area.

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2.21 EP0 Packet Size Register

EP0 Packet Size Register (EP0_PACKET_SIZE)

b15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 b0

EP0_MXPS0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0

- - - - - - - - - - - - - - - -

- - - - - - - - - - - - - - - -

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2.22 Automatic Response Control Register

Automatic Response Control Register (AUTO_RESPONSE_CONTROL)

b15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 b0

ASCN ASAD0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

- - - - - - - - - - - - - - - -

- - - - - - - - - - - - - - - -

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2.23 EP0_FIFO Select Register

EP0_FIFO Select Register (EP0_FIFO_SELECT)

b15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 b0

RCNT Octl BSWP ISEL0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

- - - - - - - - - - - - - - - -

- - - - - - - - - - - - - - - -

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2.24 EP0_FIFO Control Register

EP0_FIFO Control Register (EP0_FIFO_CONTROL)

b15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 b0

EP0_PID IVAL BCLR E0req CCPL ODLN0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0

- - - - - - - - - - - - - - - -

- - - - - - - - - - - - - - - -

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(1) EP0_PID (Response PID) Bits (b15~b14)

These bits set the PID for response to the host at data/status stage of the control transfer.At setup stage, the ACK response is executed irrespective of these bits.Writing these bits are ignored when the VALID bit is equal to1.

When these bits are set to 00

Data stage : NAK response Status stage : NAK response

When these bits are set to 01

Data stage : ACK response after receiving the data if the SIE side buffer can be ready toreceive

: NAK response if the SIE side buffer is not ready to receiveIn case the SIE side buffer is not ready to receive, the EPB_NRD bit isset to 1 when OUT token is received.

Status stage : Depends on CCPL bit

Data stage : Transmits the data if the SIE side buffer is not ready to transmit

: NAK response if the SIE side buffer is not ready to transmitIn case the SIE side buffer is not ready to transmit, the EPB_NRD bit isset to 1 when IN token is received.

Status stage : Depends on CCPL bit

When these bits are set to 1x Data stage : STALL response

In case the SIE side buffer is not ready to receive/transmit, theEPB_NRD bit is set to 1 when OUT token is received.

Status stage : STALL response

The NAK response is not executed even if these bits are set to 00 when the data is being received at datastage. The settings of these bits are reflected from the next transaction.Similarly, the transmission is not interrupted even if these bits are set to 00 when the data is being

transmitted at data stage.Further, these bits are automatically set to the values below when the following states occur:

When setup token is received "00" (NAK)

When the request set to automatic response (SET_ADDRESS or SET_CONFIGURATION) is received "01" (BUF)

The CCPL bit also is automatically set to 1 and transmits the zero-length packet at the succeedingstatus stage (IN transaction).

When sequence error occurs (CTSQ bits are set to 110) "1x" (STALL)

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(2) IVAL (IN Buffer Set/OUT Buffer Status) Bit (b13)

This bit indicates valid value when the E0req bit of this register is set to 0.

When set to control write transfer (ISEL bit = 0)When this bit is set to 1, the buffer is at CPU side and can be read.

This bit is set to 1 at completion of receiving data.

The conditions of receive completion depend on the CTRW bit.When this bit is set to 1, the EPB_RDY bit is set to 1 (buffer ready interrupt occurs).

This bit is cleared to 0 due to one of the reasons as follows: Reads out all the data received in the CPU side buffer. Writes 1 to the BCLR bit.

Note: Refer to 3.2 FIFO Buffer for CPU/SIE side.

When set to control read transfer (ISEL bit = 1)When this bit is set to 0, the buffer is at CPU side and can be written.

This bit is cleared to 0 due to one of the reasons as follows:

Transmits completely SIE side buffer. Writes 1 to the BCLR bit.

The transmit completion is changed by the CTRR bit.When this bit is set to 0 if the EPB_EMPE bit is set to 1, the EPB_EMP_OVR bit is set to 1 (bufferempty/size over error interrupt occurs).

This bit is set to 1 due to one of the reasons as follows: Completely writes the transmit data to CPU side buffer. Writes 1 to this bit.

When 1 is written to this bit, the write is forcibly completed. When some written data existsin the buffer, that data is transmitted as the short packet. Here, if the buffer is empty orcleared, the zero-length packet is transmitted. The buffer can be cleared using the BCLR bit.

Further, the zero-length packet can be transmitted by writing 1 simultaneously to this bitand to the BCLR bit. In this case the buffer is cleared by setting 1 to BCLR bit, and this bitis cleared to 0 after the zero-length packet is transmitted.

The write completion also is changed by the CTRR bit.

Note: Refer to 3.2 FIFO Buffer for CPU/SIE side.

(3) BCLR (Buffer Clear) Bit (b12)

This bit clears the data written to the CPU side buffer.

When set to control write transfer (ISEL bit = 0)When the IVAL bit is set to 1, the following operations are executed by writing 1 to this bit:

Clears CPU side buffer. Clears the IVAL bit of this register. Clears the ODLN bits of this register.

When set to control read transfer (ISEL bit = 1)When the IVAL bit is set to 0, the following operations are executed by writing 1 to this bit:

Clears CPU side buffer.Further, the zero-length packet can be transmitted by writing 1 simultaneously to this bit and to theIVAL bit. For details, refer to IVAL bit.

When the IVAL bit is set to 1, the following operations are executed by writing 1 to this bit: Clears SIE side buffer (Unlike the other endpoints, the SIE side buffer can also be cleared by

this bit). Clears the IVAL bit of this register.

Note: When the IVAL bit is set to 1, make sure to set the EP0_PID bits to 00 before executing the aforesaid

operations.

This bit automatically returns to 0 after the buffer is cleared.

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Note: Refer to 3.2 FIFO Buffer for CPU/SIE side.Note: In case the transmit data exists in the buffer for EP0_FIFO, the buffer empty interrupt occurs in the concerned

endpoint when 1 is written to the BCLR bit.

(4) E0req (EP0_FIFO Ready) Bit (b11)

When this bit is equal to 1, this bit indicates the states as follows: EP0_FIFO Data Register can not be accessed. The IVAL bit value of this register is invalid. The ODLN bit values of this register are invalid.

Make sure that this bit is equal to 0 before accessing the aforesaid registers/bits.

(5) CCPL (Control Transfer Control) Bit (b10)

This bit controls the status stage of the control transfer.When this bit is set to 1, the operations below are executed at status stage of the control transfer and notifiesthe normal completion of the control transfer:

When set to control write transfer (ISEL bit = 0) Transmits the zero-length packet after receiving IN token if the EP0_PID bits are set to 01.

When set to control read transfer (ISEL bit = 1) ACK response to the host after receiving the zero-length packet following OUT token if the

EP0_PID bits are set to 01.

When this bit is set to 0, NAK response is executed to the host after receiving the IN token/OUT token atstatus stage of the control transfer.This bit is automatically cleared to 0 by receiving the setup token.

(6) ODLN (Control Write Receive Data Length) Bits (b8~b0)

These bits are valid for control write transfer and indicate the data number (byte count) received from theCPU side buffer.Further, these bits are set to execute countdown when the EP0_FIFO Data Register is read out. Thisoperation changes according to the RCNT bit. For details, refer to RCNT bit.These bits indicate the valid value when the E0req bit of this register is equal to 0.

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2.25 EP0_FIFO Data Register

EP0_FIFO Data Register (EP0_FIFO_DATA)

b15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 b0

EP0_FIFO? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?

- - - - - - - - - - - - - - - -

- - - - - - - - - - - - - - - -

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2.26 EP0 Continuous Transmit Data Length Register

EP0 Continuous Transmit Data Length Register (EP0_SEND_LEN)

b15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 b0

SDLN0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

- - - - - - - - - - - - - - - -

- - - - - - - - - - - - - - - -

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2.27 CPU_FIFO Select Register

CPU_FIFO Select Register (CPU_FIFO_SELECT)

b15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 b0

RCNT RWND BSWP Octl CPU_EP0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

- - - - - - - - - - - - - - - -

- - - - - - - - - - - - - - - -

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(2) RWND (Buffer Rewind) Bit (b12)

This bit rewinds (initializes) the buffer pointer.

When set to OUT buffer (EPi_DIR bit = 0)When the IVAL bit of the CPU_FIFO Control Register is set to 1, the buffer reading pointer can beinitialized by writing 1 to this bit. This enables reading of the receive data from the beginning.

When set to IN buffer (EPi_DIR bit = 1)When the IVAL bit of the CPU_FIFO Control Register is set to 0, the buffer writing pointer can beinitialized by writing 1 to this bit. This enables resetting of the transmit data from the beginning.The operation is equivalent to the case when 1 is set to the BCLR bit if set to IN buffer.

(3) BSWP (Byte Swap Mode) Bit (b7)

This bit sets the endian of the CPU_FIFO Data Register.When this bit is set to 0, the CPU_FIFO Data Register gets such as little endian.When this bit is set to 1, the CPU_FIFO Data Register gets such as big endian.

b15~b8 b7~b0

Little Endian odd number address even number address

Big Endian even number address odd number address

Note: Do not set this bit to 1 when the mode is set to 8-bit (set by the Octl bit or *HWR/*BYTE pin).

(4) Octl (Register 8-Bit Mode) Bit (b6)

This bit sets the access mode of the CPU_FIFO Data Register.When this bit is set to 0, the CPU_FIFO Data Register is set to 16-bit mode, and all bits of the CPU_FIFOData Register are valid.When this bit is set to 1, the CPU_FIFO Data Register is set to 8-bit mode, and the upper-order 8 bits of theCPU_FIFO Data Register (b15 to b8) are invalid.When set to OUT buffer (EPi_DIR bit = 0), change this bit before receiving the data. When set to IN buffer(EPi_DIR bit = 1), if the Creq bit is equal to 1, do not change this bit.This bit becomes invalid (fixed to 8-bit mode) when the mode is set to 8-bit by *HWR/*BYTE pin.In such case, this bit is read 0.

Note: The access width of the CPU_FIFO Data Register is controlled by the logical sum of this bit and the EPi_Octlbits of the EPi Configuration Register 1 specified by the CPU_EP bits. Hence, the mode is set to 8-bit if 1 isset to either this bit or to the EPi_Octl bits of the EPi Configuration Register 1. Make sure that both bits must beset to 0 to change to 16-bit mode.

(5) CPU_EP (CPU Access Endpoint Designate) Bits (b3~b0)

These bits select the endpoint accessed by CPU.Make sure that the endpoint selection does not get overlapped with the selection by the DMA_EP bits.When making a change in these bits to select the other the endpoint, make sure that the source endpoint andthe destination endpoint to be changed are not under the access by the CPU or during receiving/transmittingof SIE (under access to FIFO buffer).

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2.28 CPU_FIFO Control Register

CPU_FIFO Control Register (CPU_FIFO_CONTROL)

b15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 b0

IDLY IVAL BCLR Creq CPU_DTLN0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0

- - - - - - - - - - - - - - - -

- - - - - - - - - - - - - - - -

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(1) IDLY (Isochronous Transmit Delay Set) Bit (b14)

In isochronous transfer, transmission can be started by writing 1 to this bit or to the IVAL bit after writingthe transmit data to the buffer (Note).When 1 is written to this bit, the data is transmitted by receiving the IN token after confirming the receivedSOF packet. After the data transmit starts, this is cleared to 0 (Refer to Figure 2.11).When 1 is written to the IVAL bit of this register, the data is transmitted by receiving the next IN token

(Refer to Figure 2.12).

Note: Set the transmit data size + 1 byte or more to the EPi_MXPS bits. When set to transmit data size, the IVAL bit isset to 1 when the writing to the buffer completes. Hence, this function is not applicable when set to 1023bytes, the maximum value of the EPi_MXPS bits.

Flame #m

SO F

Flame #(m+1)

IN

IDLY="1" set

SOF IN

Transmit start

Figure 2.11 Transmit start timing at IDLY bit = 1Flame #m

SOF IN

IV AL="1 " s et T rans mit s tart

Figure 2.12 Transmit start timing at IVAL bit = 1(2) IVAL (IN Buffer Set/OUT Buffer Status) Bit (b13)

This bit indicates valid value when the Creq bit of this register is equal to 0.This bit sets/clears the EPB_RDY bit to 1 (Refer to EPB_RDY bit).

When set to OUT buffer (EPi_DIR bit = 0)When this bit is set to 1, the receive data in the CPU side buffer is ready to be read.

This bit is set to 1 due to one of the reasons as follows:When set to single buffer mode (EPi_DBLB bit = 0)

Completes receiving (SIE side buffer). Writes 1 to the TGL bit.

When set to double buffer mode (EPi_DBLB bit = 1) Completes receiving of SIE side buffer and reading of CPU side buffer. Writes 1 to the TGL bit.

The receive completion is changed by the EPi_RWMD bit.

This bit is cleared to 0 due to one of the reasons as follows: Reads out all the receive data in the CPU side buffer. Writes 1 to the BCLR bit. Writes 1 to the ACLR bit.

Note: Refer to 3.2 FIFO Buffer for CPU/SIE side.

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When set to IN buffer (EPi_DIR bit = 1)When this bit is set to 0, the CPU side buffer is ready to write the transmit data.

This bit is cleared to 0 due to one of the reasons as follows:When set to single buffer mode (EPi_DBLB bit = 0)

Completes transmitting of SIE side buffer. Writes 1 to the SCLR bit.

Writes 1 to the ACLR bit.When set to double buffer mode (EPi_DBLB bit = 1) Completes transmitting of SIE side buffer and writing of CPU side buffer. Writes 1 to the SCLR bit. Writes 1 to the ACLR bit. Writes 1 to the BCLR bit.

The transmit completion is changed by the EPi_RWMD bit.

This bit is set to 1 due to one of the reasons as follows: Completes writing the transmit data to CPU side buffer. Writes 1 to this bit.

When 1 is written to this bit, the write operation is forcibly completed. When some written

data exists in the buffer, that data is solely transmitted as the short packet. Here, if thebuffer is empty or cleared, the zero-length packet is transmitted. The buffer can be clearedusing the BCLR bit. Further, the zero-length packet can be transmitted by writing 1simultaneously to this bit and to the BCLR bit. In this case the buffer is cleared by setting 1to BCLR bit, and this bit is cleared to 0 after the zero-length packet is transmitted.

The write completion also is changed by the EPi_RWMD bit.

(3) BCLR (Buffer Clear) Bit (b12)

This bit clears the data written to the CPU side buffer.

When se