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RCIM PresentationRCIM Presentation
Introduction to Asynchronous Circuits Introduction to Asynchronous Circuits and Systemsand Systems
Kristofer PertaKristofer Perta
April 02 / 2004April 02 / 2004
University of Windsor – Computer and Electrical Engineering Dept.University of Windsor – Computer and Electrical Engineering Dept.
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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR
RCIM Seminar – Kris Perta
Presentation OutlinePresentation Outline
Section 1 - Section 1 - IntroductionIntroduction
Section 2 - Section 2 - Asynchronous Circuits and SystemsAsynchronous Circuits and Systems
Section 3 - Section 3 - Designing Asynchronous SystemsDesigning Asynchronous Systems
Section 4 - Section 4 - ReferencesReferences
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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR
RCIM Seminar – Kris Perta
Section 1 - IntroductionSection 1 - Introduction
1.1.1 - 1.1.1 - Brief IntroductionBrief Introduction
1.2.1 - 1.2.1 - Asynchronous Circuits and Systems (ACAS)Asynchronous Circuits and Systems (ACAS)
1.2.2 - 1.2.2 - VLSI Design Issues and ACAS AdvantagesVLSI Design Issues and ACAS Advantages
1.2.3 - 1.2.3 - Recent Developments in ACAS Recent Developments in ACAS
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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR
RCIM Seminar – Kris Perta
1.1.1 - Brief Introduction1.1.1 - Brief Introduction
To investigate asynchronous building blocks and To investigate asynchronous building blocks and protocols.protocols.
Figure 1 - World’s first Figure 1 - World’s first
Asynchronous MicroprocessorAsynchronous Microprocessor
developed by Caltech developed by Caltech
in 1989 in 1989
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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR
RCIM Seminar – Kris Perta
1.2.1 - Asynchronous Circuits and Systems (ACAS)1.2.1 - Asynchronous Circuits and Systems (ACAS)
q d
cl
CurrentState
NextState
Clock
OutputInputCombinational
Logic
Figure 2 – Synchronous Figure 2 – Synchronous
Circuit Circuit
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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR
RCIM Seminar – Kris Perta
1.2.1 - Asynchronous Circuits and Systems (ACAS)1.2.1 - Asynchronous Circuits and Systems (ACAS)
Figure 3 – Asynchronous Figure 3 – Asynchronous
Circuit Circuit
Control ControlR
egis
ter
Reg
iste
r
Control
Reg
iste
r
Ack
Req
Data
Ack
Req
Data
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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR
RCIM Seminar – Kris Perta
1.2.2 - VLSI Design Issues and ACAS Advantages 1.2.2 - VLSI Design Issues and ACAS Advantages
VLSI Design IssuesVLSI Design Issues
Lowering power Lowering power consumptionconsumption
Addressing clock skew Addressing clock skew issuesissues
Decreasing noiseDecreasing noise
Increasing performanceIncreasing performance
ETC,ETC.......ETC,ETC.......
ACAS AdvantagesACAS Advantages
Elimination of Clock Skew Elimination of Clock Skew
Average Case PerformanceAverage Case Performance
Adaptivity to Processing and Adaptivity to Processing and Environmental Variations Environmental Variations
Component Modularity and Component Modularity and Reuse Reuse
Lower System Power Lower System Power Requirements Requirements
Reduced NoiseReduced Noise
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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR
RCIM Seminar – Kris Perta
1.2.3 - Recent Developments in ACAS 1.2.3 - Recent Developments in ACAS
Use of asynchronous circuits in the UltraSPARC IIIi Use of asynchronous circuits in the UltraSPARC IIIi synchronous processor at Sun Microsystems synchronous processor at Sun Microsystems
Brackenbury et al. use of asynchronous techniques Brackenbury et al. use of asynchronous techniques with VLSI implementations of communication with VLSI implementations of communication systems, specifically the Viterbi decoder systems, specifically the Viterbi decoder
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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR
RCIM Seminar – Kris Perta
Section 2 - Asynchronous Circuits and SystemsSection 2 - Asynchronous Circuits and Systems
2.1.1 - 2.1.1 - IntroductionIntroduction
2.2.1 - 2.2.1 - Bundled Data or Single Rail ProtocolsBundled Data or Single Rail Protocols
2.2.2 - 2.2.2 - 4 Phase Bundled Data Protocol4 Phase Bundled Data Protocol
2.2.3 - 2.2.3 - 2 Phase Bundled Data Protocol2 Phase Bundled Data Protocol
2.3.1 - 2.3.1 - Dual Rail Protocols or 1-of-2 ProtocolDual Rail Protocols or 1-of-2 Protocol
2.3.2 - 2.3.2 - 4 Phase Dual Rail or 1-of-2 RTZ Protocol4 Phase Dual Rail or 1-of-2 RTZ Protocol
2.3.3 - 2.3.3 - 2 Phase Dual Rail or 1-of-2 NRTZ Protocol2 Phase Dual Rail or 1-of-2 NRTZ Protocol
2.4.1 - 2.4.1 - Discussion On Protocol ChoiceDiscussion On Protocol Choice
2.5.1 - 2.5.1 - The Muller C-ElementThe Muller C-Element
2.5.2 -2.5.2 - The Muller Pipeline The Muller Pipeline
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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR
RCIM Seminar – Kris Perta
2.1.1 - Introduction2.1.1 - Introduction
Bundled Data(BD)
OR
Single Rail(SR)
2 PhaseOr
Non Return To Zero(NRTZ)
4 PhaseOr
Return To Zero(RTZ)
DualRail(DR)
OR
1 - o f- 2
2 PhaseOr
Non Return To Zero(NRTZ)
4 PhaseOr
Return To Zero(RTZ)
Figure 4 – ProtocolsFigure 4 – Protocols
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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR
RCIM Seminar – Kris Perta
2.2.1 - Bundled Data or Single Rail Protocols2.2.1 - Bundled Data or Single Rail Protocols
Bundled Data (BD) and Single Rail (SR) refers to the Bundled Data (BD) and Single Rail (SR) refers to the separate single (SR) request and acknowledge wires separate single (SR) request and acknowledge wires that are bundled (BD) together with the data signalsthat are bundled (BD) together with the data signals
Figure 5 – Bundle Data Figure 5 – Bundle Data
ChannelChannel
Req
Ack
Data
n
Sender Receiver
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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR
RCIM Seminar – Kris Perta
2.2.2 - 4 Phase Bundled Data Protocol 2.2.2 - 4 Phase Bundled Data Protocol
Data
Ack
Req
Figure 6 – 4-Phase BundledFigure 6 – 4-Phase Bundled
Data ProtocolData Protocol
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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR
RCIM Seminar – Kris Perta
2.2.3 - 2 Phase Bundled Data Protocol2.2.3 - 2 Phase Bundled Data Protocol
Data
Ack
Req
Figure 8 – 2-Phase BundledFigure 8 – 2-Phase BundledData ProtocolData Protocol
Figure 7 – TransitionFigure 7 – TransitionSignalling ParadigmSignalling Paradigm
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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR
RCIM Seminar – Kris Perta
2.3.1 - Dual Rail Protocols or 1-of-2 Protocol 2.3.1 - Dual Rail Protocols or 1-of-2 Protocol
Dual Rail (DR) refers to the protocol’s use of 2 (DR) Dual Rail (DR) refers to the protocol’s use of 2 (DR) wires to encode 1 bit of data information (1-of-2) wires to encode 1 bit of data information (1-of-2)
Ack
Req, Data
2n
Sender Receiver
Figure 9 – 4 Phase Dual Rail Figure 9 – 4 Phase Dual Rail ChannelChannel
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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR
RCIM Seminar – Kris Perta
2.3.2 - 4 Phase Dual Rail or 1-of-2 RTZ Protocol 2.3.2 - 4 Phase Dual Rail or 1-of-2 RTZ Protocol
Figure 10 - 4-Phase Dual RailFigure 10 - 4-Phase Dual RailProtocolProtocol
Empty Valid Empty Valid
Data {d.t, d.f}
Ack
Table 1 - 1 bit Channel Table 1 - 1 bit Channel Encoding ChartEncoding Chart
1111Not UsedNot Used
0011Valid “1”Valid “1”
1100Valid “0”Valid “0”
0000EmptyEmpty
d.fd.fd.td.tFor n=1For n=1
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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR
RCIM Seminar – Kris Perta
2.3.3 - 2 Phase Dual Rail or 1-of-2 NRTZ Protocol 2.3.3 - 2 Phase Dual Rail or 1-of-2 NRTZ Protocol
Ack
(d1.t, d1.f)
Sender Receiver
(d2.t, d2.f)
d2.t
d2.f
Ack
d1.t
d1.f
Cycle
Figure 11 - 2-Phase Figure 11 - 2-Phase Dual Rail ChannelDual Rail Channel
Figure 12 - 2-Phase Figure 12 - 2-Phase Dual Rail ProtocolDual Rail Protocol
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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR
RCIM Seminar – Kris Perta
2.4.1 - Discussion On Protocol Choice2.4.1 - Discussion On Protocol Choice
D. W. Lloyd et al. have presented a comparison on D. W. Lloyd et al. have presented a comparison on asynchronous design styles asynchronous design styles
Area(wires/bit)
Energy(transitions/bit)
2PBDP 1 1/2 (average)2PDRP 2 14PDRP 2 11-of-4 (RTZ) 2 11-of-4 (NRTZ) 2 1/2 (average)
Table 2 – CoTable 2 – Comparisonmparisonof Protocolsof Protocols
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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR
RCIM Seminar – Kris Perta
2.5.1 - The Muller C-Element2.5.1 - The Muller C-Element
David Muller invented the Muller C-Element in 1959David Muller invented the Muller C-Element in 1959
The Muller pipeline is the backbone for handshaking The Muller pipeline is the backbone for handshaking circuitrycircuitry
CX
YZ Z
X
Y
Figure 13 – Figure 13 – The C-Element and ORThe C-Element and ORElement schematic, respectively Element schematic, respectively
Table 3 - C- Element Table 3 - C- Element Truth Table Truth Table
C-Element Truth TableC-Element Truth Table
Retain previous z valueRetain previous z value0011
1111
Retain previous z valueRetain previous z value1100
000000
ZZYYXX
OR-Element Truth TableOR-Element Truth Table
110011
111111
111100
000000
ZZYYXX
Table 4 - OR Element Table 4 - OR Element Truth TableTruth Table
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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR
RCIM Seminar – Kris Perta
2.5.2 - The Muller Pipeline2.5.2 - The Muller Pipeline
CX
YZ
IF X and Y differ in stateTHEN copy X for Z
ELSE hold previous state
Figure 14 – Figure 14 – Behaviour of C-Element Behaviour of C-Element with Inverterwith Inverter
Figure 15 – Figure 15 – The Muller The Muller PipelinePipeline
A
C C
B
Req ReqAck Ack
3
Ack(in) Ack
1
2 4
Req(in) Req(out)ReqReq ReqAck Ack
Ack (out)
C C
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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR
RCIM Seminar – Kris Perta
Section 3 - Designing Asynchronous SystemsSection 3 - Designing Asynchronous Systems
3.1.1 - 3.1.1 - Possible Design IssuesPossible Design Issues
3.2.1 - 3.2.1 - Balsa (Asynchronous Hardware Language)Balsa (Asynchronous Hardware Language)
3.2.2 - 3.2.2 - Balsa Design FlowBalsa Design Flow
3.2.33.2.3 -- Balsa Buffer Example Balsa Buffer Example
3.3.13.3.1 - - ConclusionConclusion
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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR
RCIM Seminar – Kris Perta
3.1.1 - Possible Design Issues3.1.1 - Possible Design Issues
Asynchronous circuits, at a hardware level, are complex Asynchronous circuits, at a hardware level, are complex creatures that have not been addressed by the industry creatures that have not been addressed by the industry standard Electronic Design and Automation (EDA) tools and standard Electronic Design and Automation (EDA) tools and companies. companies.
““EDA tools are lacking”, explains Ian Sutherland, vice EDA tools are lacking”, explains Ian Sutherland, vice president and fellow at Sun Microsystems Laboratories. EDA president and fellow at Sun Microsystems Laboratories. EDA tools are intended for synchronous system design.tools are intended for synchronous system design.
VHDL and Verilog, industry standard hardware description VHDL and Verilog, industry standard hardware description languages, lack the needed “concurrency and platform for languages, lack the needed “concurrency and platform for handshaking channels” that are required by asynchronous handshaking channels” that are required by asynchronous systems. systems.
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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR
RCIM Seminar – Kris Perta
3.2.1 - BALSA (Asynchronous Hardware Language)3.2.1 - BALSA (Asynchronous Hardware Language)
A recent free tool from the University of Manchester, one of the A recent free tool from the University of Manchester, one of the academic leaders in asynchronous design, is academic leaders in asynchronous design, is 'BALSA''BALSA'. .
Balsa is both a “framework for synthesis of asynchronous Balsa is both a “framework for synthesis of asynchronous hardware systems and a language for describing such hardware systems and a language for describing such systems”. systems”.
Balsa used the adopted approach of proprietary languages like Balsa used the adopted approach of proprietary languages like Tangram of “syntax-directed compilation into communication Tangram of “syntax-directed compilation into communication handshaking components”. handshaking components”.
This means that there is direct “one-to-one” mapping between This means that there is direct “one-to-one” mapping between language and direct handshaking circuits produced.language and direct handshaking circuits produced.
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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR
RCIM Seminar – Kris Perta
3.2.2 - BALSA Design Flow3.2.2 - BALSA Design Flow
Figure 16 – Asynchronous Digital Figure 16 – Asynchronous Digital
Design FlowDesign Flow
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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR
RCIM Seminar – Kris Perta
3.2.3 - Balsa Buffer Example3.2.3 - Balsa Buffer Example
import [balsa.types.basic] import [balsa.types.basic]
procedure bufferloop (input i : bit; output o : bit) procedure bufferloop (input i : bit; output o : bit)
is is
variable x : bitvariable x : bit
begin begin
loop loop
i -> x -- Input communication i -> x -- Input communication
; -- Sequence operator; -- Sequence operator
o <- x -- Output communication o <- x -- Output communication
end end
endend
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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR
RCIM Seminar – Kris Perta
3.2.3 - Balsa Buffer Example3.2.3 - Balsa Buffer Example
Figure 17 – Handshake Circuit Figure 17 – Handshake Circuit For a Single Place BufferFor a Single Place Buffer
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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR
RCIM Seminar – Kris Perta
3.2.3 - Balsa Buffer Example3.2.3 - Balsa Buffer Example
Figure 18 – Generated HandshakeFigure 18 – Generated Handshake
Circuit For a Single Place BufferCircuit For a Single Place Buffer
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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR
RCIM Seminar – Kris Perta
3.3.1 - Conclusion3.3.1 - Conclusion
Asynchronous design is not a direct mapping of a Synchronous Asynchronous design is not a direct mapping of a Synchronous Design, this depends on the type of design one is doing Design, this depends on the type of design one is doing (analog layout or digital design flow) (analog layout or digital design flow)
Asynchronous design does have the possibility of being a Asynchronous design does have the possibility of being a feasible alternative to the 'norm', which is synchronous feasible alternative to the 'norm', which is synchronous
The combination of asynchronous design with synchronous The combination of asynchronous design with synchronous design is a slow, yet emerging field of studydesign is a slow, yet emerging field of study
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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR
RCIM Seminar – Kris Perta
Section 4 - ReferencesSection 4 - References
[1][1] http://www.async.caltech.edu/cam.htmlhttp://www.async.caltech.edu/cam.html
[2][2] C.H. Van Berkel, M.B. Josephs, and S.M. Nowick. “Scanning theTechnology: C.H. Van Berkel, M.B. Josephs, and S.M. Nowick. “Scanning theTechnology: Applications of Asynchronous Circuits”, Proceedings ofthe IEEE, Volume 87, Issue 2, Applications of Asynchronous Circuits”, Proceedings ofthe IEEE, Volume 87, Issue 2, Feb. 1999, pages 223-233 Feb. 1999, pages 223-233
[3][3] Edited by Jens Sparsø, Steve Furber. “Principles of Asynchronous Circuit Design – A Edited by Jens Sparsø, Steve Furber. “Principles of Asynchronous Circuit Design – A System Perspective”, Kluwer Academic Publishers, 2001.System Perspective”, Kluwer Academic Publishers, 2001.
[4][4] http://www.sciam.com/article.cfm?articleID=00013F47-37CF-1D2A-http://www.sciam.com/article.cfm?articleID=00013F47-37CF-1D2A-97CA809EC588EEDF97CA809EC588EEDF
[5][5] L. E. M. Brackenbury, M. Cumpstey, S.B. Furber, P.A. Riocreuz, “Applying Asynchronous L. E. M. Brackenbury, M. Cumpstey, S.B. Furber, P.A. Riocreuz, “Applying Asynchronous Techniques to a Viterbi Decoder Design”, IEEE, 2001.Techniques to a Viterbi Decoder Design”, IEEE, 2001.
[6][6] P.A. Riocreux, L.E.M. Brackenbury, M. Cumpstey, S.B. Furber ,”Low-Power Self-Timed P.A. Riocreux, L.E.M. Brackenbury, M. Cumpstey, S.B. Furber ,”Low-Power Self-Timed Viterbi Decoder”, Seventh International Symposium on Asynchronous Circuits and Viterbi Decoder”, Seventh International Symposium on Asynchronous Circuits and Systems, March 2001Systems, March 2001
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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR
RCIM Seminar – Kris Perta
Section 4 - ReferencesSection 4 - References
[7][7] K. E. Tepe, “Iterative Decoding Techniques for Correlated Rayleigh Fading and Diversity K. E. Tepe, “Iterative Decoding Techniques for Correlated Rayleigh Fading and Diversity Channels”, Communication, Information and Voice Processing Report Series, Report TR-Channels”, Communication, Information and Voice Processing Report Series, Report TR-2001-1, University of Lund - Information Technology Department and Rensselaer 2001-1, University of Lund - Information Technology Department and Rensselaer Polytechnic Institute - Electrical, Computer and System Engineering Department Polytechnic Institute - Electrical, Computer and System Engineering Department February 2001.February 2001.
[8][8] I. Sutherland, “Micropipelines: Turing Award Lecture”, Communications of the ACM, June I. Sutherland, “Micropipelines: Turing Award Lecture”, Communications of the ACM, June 1989. Vol 32, #6, pp. 720-738 1989. Vol 32, #6, pp. 720-738
[9][9] D. Muller and W. Bartky, “A Theory of Asynchronous Circuits”, Proceedings of an D. Muller and W. Bartky, “A Theory of Asynchronous Circuits”, Proceedings of an International Symposium on the Theory of Switching, p.p. 204-243, April 1959International Symposium on the Theory of Switching, p.p. 204-243, April 1959
[10][10] R. B. Wells, ”Applied Coding and Information Theory for Engineers”, Prentice Hall, R. B. Wells, ”Applied Coding and Information Theory for Engineers”, Prentice Hall, 1999 1999
[11] S. Shahzad Shah, S. Yaqub, F.l Suleman, "Self-Correcting Codes Conquer Noise, Part [11] S. Shahzad Shah, S. Yaqub, F.l Suleman, "Self-Correcting Codes Conquer Noise, Part One: Viterbi Codecs", EDN Magazine, 2001 http://www.reed- One: Viterbi Codecs", EDN Magazine, 2001 http://www.reed- electronics.com/ednmag/contents/images/75255.pdfelectronics.com/ednmag/contents/images/75255.pdf
[12][12] R. Goering. “Keynoter Sees Asynchronous Future For Digital Designs”, EE Times, R. Goering. “Keynoter Sees Asynchronous Future For Digital Designs”, EE Times, December 4, 2002. http://www.eetimes.com/story/OEG20021204S0018 December 4, 2002. http://www.eetimes.com/story/OEG20021204S0018