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21st, January / 2016FD-SOI and RF-SOI Forum in Tokyo
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Wafer Supplier Aspects of
FD-SOI and RF-SOI
SOI Engineering Section, SOI Production Department, Isobe PlantShin-Etsu Handotai Co., Ltd.
21st, January / 2016FD-SOI and RF-SOI Forum in Tokyo
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SOI technology is attractive!SOI technology is attractive!
� FD-SOI devices for SOC application
� RF-SOI devices for RF application
Cloud TechnologyMobile Technology
high speed, long battery life
worldwide use ( 2G, 3G, 4GLTE,5G)
Internet of Things (M2M)huge data trafficbig data center
Digital Communication World is Expanding Drastically
21st, January / 2016FD-SOI and RF-SOI Forum in Tokyo
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FD-SOI
RF-SOI (High Res / Trap Rich )
SOI ( MEMS )
GaAs PAs
( Operating at f >2GHz )
Si
RF Transceiver
A-CPU
C-CPU
Power Management
Memory
2.5G
PA
3G/4GPA
& LNA
3G/4GLNA
Audio
Battery
Sensor
Display
SW
SW
SW
SW
Ant.
Tuning
SW
LNA
LNA
GPS Ant.
PA
5GHz
Key
Camera
WiFi / BT
/ (NFC)
GPS
FM
TV
2G / 3G
/ 4G (LTE)
Diversity
(3G / LTE)
WiFi Ant.
FM Ant.
TV Ant.
Cellular Ant.
SW
Diversity Ant.PA
5GHz Tx
5GHz Rx
2.4GHz Tx
2.4GHz Rx
VHF(1)
UHF
VHF(2)
Ant.
Tuning
SW
LNA
SOI Wafers in a Mobile Handset
21st, January / 2016FD-SOI and RF-SOI Forum in Tokyo
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SOI -FinFETFD-SOI
SOI thk +/- 0.5nm
2002
Thin-SOI production start
PD SOI
SOI thk +/- 3.5nm
RF-SOI
Handle : HR, w/poly
SOI
BOX thk >1000nm
Epi on SOI
SOI thk > 1000nm
Logic Application RF Application
Photonics Application
CIS / MEMS
Recent Advanced SOI
21st, January / 2016FD-SOI and RF-SOI Forum in Tokyo
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From CZ to SOIFrom CZ to SOI
SOI Technology for FD-SOI and RF-SOI
HQ / High Resistivity
Crystal Growth process
HQ / High Resistivity Poly-Si layer process
HQ / Thin-SOI process
SEH Total Solution of Wafer Supply
HQ / PW wafer process
21st, January / 2016FD-SOI and RF-SOI Forum in Tokyo
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Handle wafer
12nm SOI
25nm BOXBOX ( 25nm)
SOI (12nm)
Handle wafer
SOI Thickness Map
Average SOI thickness Range(Max-Min) in a wafer All points
0%
20%
40%
60%
80%
100%
≦ 11.6nm
≦ 11.7nm
≦ 11.8nm
≦ 11.9nm
≦ 12.0nm
≦ 12.1nm
≦ 12.2nm
≦ 12.3nm
≦ 12.4nm
Averaged SOI thickness in a wafer
Frequency
0%
20%
40%
60%
80%
100%
Cumulative
0%
10%
20%
30%
40%
50%≦ 0.4nm
≦ 0.5nm
≦ 0.6nm
≦ 0.7nm
≦ 0.8nm
≦ 0.9nm
≦ 1.0nm
1.0nm >
SOI thickness range(Max-Min) in a wafer
Frequency
0%
20%
40%
60%
80%
100%
Cumulative
0%
10%
20%
30%
40%
50%
≦ 11.5nm
≦ 11.6nm
≦ 11.7nm
≦ 11.8nm
≦ 11.9nm
≦ 12.0nm
≦ 12.1nm
≦ 12.2nm
≦ 12.3nm
≦ 12.4nm
≦ 12.5nm
≦ 12.6nm
SOI thickness
Frequency
0%
20%
40%
60%
80%
100%
Cumulative
Ave. : 12.0nm
Sigma: 0.06nm
Ave. : 0.59nm
Sigma: 0.11nmAve. : 12.0nm
Sigma: 0.15nm
Range: 0.63nm
SOI Thickness Uniformity of FD-SOI
21st, January / 2016FD-SOI and RF-SOI Forum in Tokyo
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0%
10%
20%
30%
40%
50%
60%
< 0.1nm
< 0.2nm
< 0.3nm
< 0.4nm
< 0.5nm
< 0.6nm
< 0.7nm
< 0.8nm
< 0.9nm
< 1.0nm
< 1.1nm
< 1.2nm
< 1.3nm
< 1.4nm
< 1.5nm
< 1.6nm
< 1.7nm
< 1.8nm
< 1.9nm
< 2.0nm
Range in a wafer [nm]
Frequency
Implantation
Bonding
Splitting
Smoothing anneal
&
Oxidation
Handle wafer
Donor wafer
Oxidation
Optimization of oxidation condition
Range:1.12nm Range:0.11nm
Optimization of oxidation condition
SOI
thickness
uniformity
Optimization of implantation & Splitting condition
After optimization
Improvement of SOI Thickness for FD-SOI
21st, January / 2016FD-SOI and RF-SOI Forum in Tokyo
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AFM roughness is very close to ideal region. (RMS<0.1nm)
BOX ( 25nm)
SOI (12nm)
Handle wafer
Roughness = local thickness deviation
After Smoothing anneal
30um x 30um measurement
RMS: 0.11nm
Rmax: 1.1nm
Handle wafer
Implantation
Donor wafer
Bonding
Splitting
Smoothing anneal&
Oxidation
Oxidation
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
Annealing Time
Ro
ug
hn
ess
[n
m]
Surface Roughness
21st, January / 2016FD-SOI and RF-SOI Forum in Tokyo
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Thin SOI (50 – 200nm)
Thick BOX
(0.4 - 2 um)
HandleWafer
High Resistivity
1) Stable Resistivity suppress the thermal donor formation
2) Superior RF Characteristics suppress PSC (parasitic surface conduction)
� Trap Rich SOI technology ( SOI with poly-Si layer )
Interstitial Oxygen become a donor by low temperature heat treatment.
� High quality CZ crystal (high resistivity, extra low impurity, extra low Oi) was developed.
SOI Wafer for RF Application
21st, January / 2016FD-SOI and RF-SOI Forum in Tokyo
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Harmonics Measurement
< Measured Harmonics in SEH >
AL electrode pattern
( CPW transmission line )
f
Power
f0=1GHz
f
Power
f0=1GHz
f
Power
f02f0
3f0nf0
f
Power
f02f0
3f0nf0
Handle Si substrate
SiO2 (BOX)
Input Output
Measuring
the Harmonics Level
RF Probe
（Port 1）RF Probe
（Port 2）
< System >Scanning
the input powerWithout Trap Rich Layer
With Trap Rich Layer
CPW
Harmonics Generator
G
G
S
( = On-wafer Power Measurement)
Handle Si substrate
SiO2 (BOX)Trap-rich layer
AL
Handle Si substrate
SiO2 (BOX)Trap-rich layer
AL
Handle Si substrate
SiO2 (BOX)
AL
Handle Si substrate
SiO2 (BOX)
AL
-140-130-120-110-100
-90-80-70-60-50-40-30-20-10
0
0 5 10 15 20 25 30 35
Pin （ｄBm）
Harm
onics （
ｄB
m）
30dB
Down
2nd Harmonics
Harmonics
Upper Limitation
Without
Trap Rich Layer
With
Trap Rich Layer
: Harmonics Upper Limitationx : Harmonics Upper Limitationx
21st, January / 2016FD-SOI and RF-SOI Forum in Tokyo
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0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
-100 -80 -60 -40 -20 0 20 40 60 80 100
Poly-Si layer Thickness(um)
Position (mm)
Distribution
(X-irection)
13 points
Distribution (X-direction)
-130-120-110-100
-90-80-70-60-50-40-30-20-10
0
250 252 254 256 258 260 262 264
Left side X-address Right side
Harm
onics(dBm) 2f0
3f0
Upper
Limitation
Measured 2nd Harmonics ( 2f0 )
-130
-120
-110
-100
-90
-80
-70
-60
-50
0 5 10 15 20 25 30 35
Pin or Pout （（（（dBm））））
Harm
onics (dBm)
Calculated
2f0 Ave.=
-104.5dBm
Harmonics
Upper Limitation
Measured
25 PointsMeasurement
Map
25 Points
Thickness Uniformity of Poly-Si Layer RF Characteristics Uniformity within a Wafer
Po
ly-S
i la
ye
r th
ick
ne
ss
21st, January / 2016FD-SOI and RF-SOI Forum in Tokyo
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