What Are the Benefits of Area Constraints Xilinx

8/11/2019 What Are the Benefits of Area Constraints Xilinx

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What are the Benefits of AreaConstraints?


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Create effective Area Constraints using PlanAhead tool

Identify Floorplanning Methodologies

Avoid the most common design and synthesis mistakes

during floorplanningGain timing closure with the PlanAhead tool

Place the dedicated hardware resources

Objectives


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Definition of Floorplanning (Area Constraints)

In the past, the term Floorplanning meant to make placementcons t ra in t s on CLB logic (assign it to specific locations) The term floor planning in the ASIC world still means to place (assign)

gates in a specific location on an array

Floorplanning is NOT necessary in an FPGA but can help to improve

timing

Xilinx recommends the use of area constraints, rather than the useof placement constraints

However, this does require some skill

F loorp lann ing is now commonly referred to as placing Areaconstraints

So whenever you see Floorplanning we mean Area Constraints


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Reasons to Floorplan with Area Constraints

Floorplanning is considered when the design hasnot met timing or does not meet timing consistently

Floorplanning condenses and contains critical logicto improve performance

Reduce routing congestion

Isolate non-critical logic Create a data flow-based floorplan

Use unique Pblock capabilities in thePlanAhead tool

Improve module-level performance and area

Improve implementation run time and consistency withPartitions


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Design and Synthesis Recommendations

Set up your synthesis tool to preserve the hierarchyin the netlist

Flattened netlists may be optimal from a synthesisperspective, but they make it very difficult to reliablyfloorplan and constrain placement

Structure the RTL logic so that critical timing pathsare confined to individual modules

Critical paths that span large numbers of hierarchicalmodules can be difficult to floorplan

Register the outputs of all the modules to help limit

the number of modules involved in a critical pathReplicate the drivers of nets that will be separatedon the die

Synthesis may need an attribute to preserve equivalentlogic


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Intermingled critical paths can be difficult to floorplan Consider dividing large critical blocks into smaller and separate

hierarchical blocks

If the design is expected to change often, consider an

incremental approach to synthesis In an incremental approach, individual blocks can be synthesized

separately or the synthesis attributes (SYN_HIER=HARD) can be usedto preserve the hierarchy

Hierarchy preservation helps an incremental flow but may hurt

performance because global optimizations across hierarchy are disabled


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Consider using the synthesis option to rebuild the hierarchy For XST, use netlist_hierarchy = rebuilt

If using the PlanAhead tool for synthesis, the PlanAhead tool defaultsynthesis strategy includes this option

Long paths in single large hierarchical block can makefloorplanning difficult

Divide large hierarchical blocks in the RTL


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Re-Use Flow Methodology

Can help a design that meets timing only some of the time The idea is to re-use some of the block RAM and DSP slice placements

from a successful implementation

Synthesize the design

Run implementation many times with only timing constraints andpin assignmentsChoose the result that has met timing and had the fastestimplementation time

Fix the placement of the block RAMs and DSP slices Either by manually placing them or using the Find command With a little experience you may want to manually place them

Re-implement as neede d


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Hierarchical Methodology

Synthesize the designRun implementation with only timing constraints and pin assignments

If it fails to meet timing (many paths fail across many components) Make the area constraints based on the highest levels of your design hierarchy

Possibly constrain the entire design

Ask yourself these questions What are the timing failures?

What are the critical hierarchical blocks?

Are changes to the floorplan or critical logic going to be sufficient to meet

timing? Does anything else need to be floorplanned?

Can just the critical hierarchies be floorplanned?

Where should my logic be placed?


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Placement of Dedicated Resources

Placing dedicated hardware is a terrific strategy The implementation tools do not always do the best job

Consider placing block RAMs and DSP slices

This works well when you make area constraints Placement of dedicated resources guides the

implementation tools to move CLB logic closer to the desired location Place area constraints near the I/O pins and

dedicated hardware you plan to use

BlockRAM

BlockRAM


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Where are the Dedicated Hardware Resources?

Virtex-6 FPGAs Spartan-6 FPGAs

150KLogic Cell

Device

760KLogic Cell

Device

Common Resources

3.3 Volt Compatible I/O

Hardened Memory Controllers

LUT-6 CLB

DSP Slices

Block RAM

HSS Transceivers*

Parallel I/OFIFO Logic

System Monitor

Tri-Mode EMAC

PCIe Interface

High-performance Clocking


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Assigning LOC Constraints

Most logic objects can be manuallyassigned to a specific site

Click the Create Site Const raintMode toolbar button (to place)

Note that placed logic has a blue barLogic is easily found with the Findcommand and then dragged to beplaced

Cursor indicates legal placement sites

Right-click allows you to un-place


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Assigning BEL (Basic Elements) Constraints

Click the Create BEL Cons t rain tMode toolbar button

Drag a LUT or FF primitive from theFind menu or Netlist view onto a

specific slice Primitives with LOC constraints are

displayed in the Netlist view with bluestriped icons

Click the As sign Ins tance Modetoolbar button to return tofloorplanning mode


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LOC Constraint Applications

To clear LOC constraints Select Tools > Clear Placement Many options to selectively clear LOCs Separate controls for I/O ports Importing an implementation result leaves the logic

unfixed

Importing LOCs from a UCF file is considered manuallyassigned and remains placed

Right-click a placed object to Fix Instances (LOC) I/O interfaces or cores, for example

Lock down non-slice-based logic (block RAMS,or DSP, for example)

Maximize module performance and consistency

Export constraints with File > Export Constraints


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Summary

Area constraint guidelines Use the timing report to identify logic to floorplan

Leverage the implementation results to guide placement of areaconstraints

Placement of dedicated resources can guide theimplementation tools

Be sure to make an area constraint with the associated logic andassign it near the dedicated hardware to improve performance

Placement improves implementation consistency between eachiteration


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More Information

To learn more, visit the PlanAhead tool web site www.xilinx.com/planahead Articles, documentation, white papers, and training enrollment

User Guide

PlanAhead Software Tutorial, Design Analysis and Floorplanning forPerformace , UG676

Floorplanning Methodology Guide, UG633

View the PlanAhead tool video demonstrations

Quick Tour of the PlanAhead Design and Analysis Tool I/O pin planning with PinAhead Technology Improve Design Performance with the PlanAhead Design and Analysis tool


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Where Can I Learn More?

Xilinx Education Services courses www.xilinx.com/training

Xilinx tools and architecture courses Hardware description language courses

Basic FPGA architecture, Basic HDL Coding Techniques, and other freeVideos!

How to make Area Constraints with PlanAhead tool Video!
http://www.support.xilinx.com/products&serviceshttp://www.support.xilinx.com/products&services


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What Are the Benefits of Area Constraints Xilinx