Working With Spartan Board- Xilinx

7/31/2019 Working With Spartan Board- Xilinx

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FPGA Physical Description

1. VGA (HD-15) Monitor Port2. 9-pin (DB-9)

3. Power Connector4. A1 Expansion Port

5. A2 Expansion Port6. B1 Expansion Port

7. PS/2 Port8. Seven Segment Displays

9. Switches (8)10. Buttons (4)

11. LEDs (8)12. Power LED

13. Spartan 3 FPGA Core14. Program LED (Lit when the FPGA is programmed)

15. JTAG Port (used to program the FPGA)

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Programming Xilinx Board (Spartan 3) Tutorial Using

ISE 8.1i

IntroductionThis tutorial shows you how to program Spartan 3 FPGA board using Xilinx ISE

8.1i. As an example, a half adder circuit will be implemented on the Spartan 3 board.

The tutorial begins by showing you how to create a new project and how to describe thedigital circuit in VHDL. After the circuits functionality has been verified, it is then

downloaded to the Spartan 3 board for implementation. You are encouraged to try outthe examples before embarking on any exercise.

Creating a new Project and Source

Start the Xilinx ISE 8.1i project navigator by double clicking the Xilinx ISE 8.1i icon onyour desktop.

Xilinx ISE 8.1i.lnk

Click on File and select New Project


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Select a project location and type the name you would like to call your projectHalfAdder:

ClickNext

Select the device family, device, package, and speed grade as shown below:

ClickNext


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ClickNew Source

Select VHDL Module in the New Source Wizard window:

ClickNext


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Specify the inputs and outputs of your design (HalfAdder). This is used to generate atemplate for your VHDL code.

ClickNext

ClickFinish if you are satisfied your specifications shown in the summary page


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ClickNext

ClickNext


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Verify the information on the Project Summary window:

ClickFinish.

Double-click on HalfAdder-Behavioral(HalfAdder.vhd) tab in the Sources pane.


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Include an enable input in your entity and it should be 1 bit wide.Complete the architectural part of your VHDL code.


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Specify the pins you would like the inputs and outputs to be connected to.

Double-click on Assign Package Pins in the Process pane in the left of the window.

Note: You may be asked to save your VHDL code. Your design will be checked for

syntax error. If you have any error, make sure you fix them before proceeding.

ClickYes.


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ClickYes.

The Pace editor is loaded.

You can select Package View tab at the bottom of the right pane. The package viewgives a better view of the physical FPGA package).


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Type in the desired pin names for each signal in the Design Object List at the left in

the Loc column

ClickFile and Save.

ClickFile and Exit.Note: The following dialog may appear when saving the file:

Click on Dont show this dialog again.

ClickOk.


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View the UCF file by double-clicking Edit Constraints (Text) in the project Navigatorwindow.


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Programming the BoardIn the Project Navigator window, double-click on HalfAdder-Behavioral (HalfAdder)tab in the Sources pane.


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Right-click on Generate Programming File in the Processes pane.

Select Properties.

In the Process Properties windows, Select Startup Options tab.

Change FPGA Start-UP Clock to JTAG Clock


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ClickApply.

ClickOk.

In the Processes window, click on the + sign by Generate programming file.Double-click on Configure Device (iMPACT). This opens the iMPACT tool and a

wizard for creating a new configuration.


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ClickFinish.


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Assign New Configuration File window opens. Select the name of your select the.bit file (HalfAdder.bit).

ClickOpen.

clickBypass.


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You will now be at the main iMPACT window:

Right-click on the FPGA (xc3s200).

select Program.


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Make sure that Verify is not checked.

ClickApply.ClickOk.

The FPGA is now being programmed as shown:

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Working With Spartan Board- Xilinx