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Introduction to the ARM Instruction Set
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Agenda
Data Processing Instructions Branch InstructionsLoad-Store InstructionsSoftware Interrupt InstructionsProgram Status Register InstructionsLoading ConstantsARMv5E ExtensionsConditional ExecutionSummary
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ARM Instruction SetMnemonics ARM ISA DescriptionADC v1 add two 32 bit values & carryADD v1 add two 32 bit valuesAND v1 logical bitwise AND of two 32 bit
valuesB v1 branch relative +/- 32MBBIC v1 logical bit clear of two 32 bit
valuesBKPT v5 breakpoint instructionsBL v1 relative branch with linkBLX v5 branch with link and exchangeBX v4T branch with exchangeCDP CDP2 v2 v5 coprocessor data processing
operationCLZ v5 count leading zeroesCMN v1 compare negative two 32-bit
valuesCMP v1 compare two 32 bit valuesEOR v1 logical EOR of two 32 bit valuesLDC LDC2 v2 v5 load to coprocessor single or
multiple32 – bit valuesLDC LDC2 v2 v5 load to coprocessor single or
multiple32 – bit valuesLDM v1 load multiple 32 – bit words from
memory to ARM registers
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ARM Instruction Set - Contd
Mnemonics ARM ISA DescriptionLDR v1 v4 v5E load a single value from a virtual
address in memoryMCR MCR2 MCRR
v1 v4 v5E move to coprocessor from an ARM register to registers
MLA v2 multiply & accumulate 32 bit values MOV v1 move a 32 bit value into a register
MRC MRC2 MRRC
v1 v4 v5E move to ARM register or registers from a coprocessor
MRS v3 move to ARM register from a statusregister (cpsr or spsr)
MSR v3 move to a status register (cpsr or spsr)from an ARM register
MUL v2 multiply two 32 bit values MVN v1 move the logical NOT of 32 bit
value into a register ORR v1 Logical bitwise OR of two 32 bit
valuesPLD v5E preload hint instruction
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ARM Instruction Set - Contd
Mnemonics ARM ISA DescriptionQADD v5E signed saturated 32 bit add QDADD v5E signed saturated double and 32
bit add QDSUB v5E signed saturated double and 32 bit sub. QSUB v5E signed saturated 32 bit subtract
RSB v1 reverse subtract of two 32 bit valuesRSC v1 reverse subtract with carry of two 32 bit integers
SBC v1 subtract with carry of two 32 bit valuesSMLAxy v5E signed multiply accumulate instruction ((16 x 16) + 32 = 32 – bit) SMLAL v3M signed multiply accumulate long ((32 x 32) + 64 = 64 – bit)
SMLALxy v5E signed multiply accumulate long ((32 x 16) + 64 = 64 – bit)
SMLAWy v5E signed multiply accumulate instruction ((32 x 16) >> 16 +32 = 32 – bit)
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ARM Instruction Set - Contd
Mnemonics ARM ISA DescriptionSMULL v3M signed multiply long (32x32 = 64
– bit) SMULxy v5E signed multiply instructions (16 x 16 = 32 – bit)
SMULWy v5E signed multiply instructions (32 x 16) >> 16 = 32 – bit)
STC STC2 v2 v5 store to memory single or multiple 32 bit values from coprocessor
STM v1 store multiple 32 bit registers to memorySTR v1 v4 v5E store register to a virtual address in memory
SUB v1 subtract two 32 bit values SWI v1 software interruptSWP v2a swap a word/byte in memory with
a register, without interruption TEQ v1 test for equality of two 32 bit
values
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ARM Instruction Set - Contd
Mnemonics ARM ISA DescriptionTST v1 test for bits in a 32 bit value UMLAL v3M unsigned multiply accumulate
long (32 x 32) + 64 = 64 – bit) UMULL v3M unsigned multiply long (32 x 32 = 64 – bit)
Different ARM architecture revisions support different instructionsARM instructions process data held in registers and only access memory with load and store instructionsARM instructions commonly take two or three operands
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Data Processing Instructions
Manipulate data within registers Move Instructions Arithmetic Instructions Logical Instructions Comparison Instructions Multiply Instructions
Most data processing instructions can process one of their operands using the barrel shifterS suffix updates the flags in the cpsr
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Move Instructions
<instruction>{<cond>}{S} Rd, NUseful for setting values and transferring data between registersN can be a register or an immediate value preceded by #
MOV Move a 32 bit value into a register Rd = N
MVN Move the NOT of the 32 bit value into a register
Rd = ~N
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Barrel Shifter
Arithmetic Logic Unit
Rm
Result N
Rd
Rn
No p
re-p
roce
ssin
g
Pre
-pro
cess
ing
Barrel ShifterShift the 32 bit binary pattern in one of the source registers left or right by a specific number of positions before it enters the ALU
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Logical shift left by one
1 0 00
0 0 01
Bit2
Bit0
1 0 0nzcv
0 0 0nzCv
Bit31
= 0x80000004
= 0x00000008
31
Condition Bags
Condition Bags
Condition flagsUpdated when
S is present
PRE r5 = 5 r7 = 8
MOV r7,r5,LSL #1 ; POSTr5 = 5 r7 = 10
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Barrel Shifter OperationsMne. ShiftDescription Result Shift amount
yLSL logical shift leftxLSLy x << y #0-31 or RsLSR logical shift
rightxLSRy (unsigned)x >> y #1-32 or Rs
ASR arith. right shiftxASRy (signed)x >> y #1-32 or RsROR rotate right xROR
y((unsigned)x >> y) | (x <<(32 – y))
#1-32 or Rs
RRX rotate right extended
xRRXy (c flag << 31) | ((unsigned)x >>1)
none
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ARM Shift Operations
031
00000
LSL #5
031
00000
LSR #5
031
11111 1
ASR #5 , negative operand
031
00000 0
ASR #5 , positive operand
0 1
031
ROR #5
031
RRX
C
C C
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Barrel Shift Operation Syntax for Data Processing Instructions
N Shift Operations SyntaxImmediate #immediate
Register Rm
Logical Shift Left by Immediate Rm, LSL #shift_imm
Logical Shift Left by Register Rm, LSL Rs
Logical Shift Right by Immediate Rm, LSR #shift_imm
Logical Shift Right by Register Rm, LSR Rs
Arithmetic Shift Right by Immediate Rm, ASR #shift_imm
Arithmetic Shift Right by Register Rm, ASR Rs
Rotate right by immediate Rm, ROR #shift_imm
Rotate right by register Rm, ROR Rs
Rotate right with extend Rm, RRX
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Arithmetic Instructions<instruction>{<cond>}{S} Rd, Rn, N
ADC
Add two 32 bit values and carry Rd = Rn + N + carry
ADD
Add two 32 bit values Rd = Rn + N
RSB
Reverse subtract of two 32 bit values Rd = N – Rn
RSC
Reverse subtract with carry of two 32 bit values
Rd = N – Rn -!(carry flag)
SBC
Subtract with carry of two 32 bit values Rd = Rn -N–!(carry flag)
SUB
Subtract two 32 bit values Rd = Rn -N
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Arithmetic Instructions
RSB can be used to negate numbers
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Logical Instructions
<instruction>{<cond>}{S} Rd, Rn, N
AND logical bitwise AND of two 32 bit values Rd = Rn & N
ORR logical bitwise OR of two 32 bit values Rd = Rn | N
EOR logical exclusive OR of two 32 bit values
Rd = Rn ^ N
BIC Logical bit clear (AND NOT) Rd = Rn & ~ N
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Logical Instructions
BIC is useful when clearing status bits and is frequently used to change interrupts masks in the cpsrThe logical instructions update the cpsr flags only if the S suffix is present
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Compare Instructions
<instruction>{<cond>} Rn, N
CMN compare negated Flag set as a result of Rn + N
CMP compare Flag set as a result of Rn - N
TEQ test for equality of two 32 bit values
Flag set as a result of Rn ^ N
TST test bits of a 32 bit values Flag set as a result of Rn & N
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Compare Instructions
They update the cpsr flag according to the result but do not affect other registersCMP is effectively a subtract instruction with result discardedTST is logical AND operationTEQ is logical EOR
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Multiply Instructions
MLA multiply & accumulate Rd = (Rm * Rs) + Rn
MUL multiply Rd = Rm * Rs
MLA{<cond>}{S} Rd, Rm, Rs, RnMUL{<cond>}{S} Rd, Rm, Rs
instruction>{<cond>}{S} RdLo, RdHi, Rm, Rs
SMLAL signed multiply accumulate long
[RdHi,RdLo]=[RdHi,RdLo] + (Rm * Rs)
SMULL signed multiply long [RdHi,RdLo]=(Rm * Rs)
UMLAL unsigned multiply accumulate long
[RdHi,RdLo]=[RdHi,RdLo] + (Rm * Rs)
UMULL unsigned multiply long [RdHi,RdLo]=Rm * Rs
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Branch Instructions
Changes the flow of execution or is used to call a routineForces the pc is point to a new addressB{<cond>} labelBL{<cond>} labelBX{<cond>} RmBLX{<cond>} label | Rm
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Branch Instructions
B branch pc = label
BL branch with link
pc = labellr = address of the next inst. After BL
BX branch exchange
pc = Rm & 0xfffffffe, T = Rm & 1
BLX branch exchange with link
pc=label, T = 1pc = Rm & 0xfffffffe, T = Rm & 1lr = address of the next inst. After BL
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Branch InstructionsThe branch with link, or BL, instruction is similar the B instruction but overwrites the link register with a return addressTo return from a subroutine, the link register should be copied to the pc
BL subroutine ; branch to subroutineCMP r1, #5 ; compare r1 with 5MOVEQ r1, #0 ; if (r1 == 5) then r1 = 0
subroutine….….MOV pc, lr ; return by moving pc = lr
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Load Store Instructions
Transfer data between memory and processor registersSingle – register transferMultiple – register transferSwap
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Single Register Transfer
Moving a single data item in and out of a registerData types supported are signed and unsigned words (32 bit), half words (16 bit) and bytes<LDR|STR> {<cond>}{B} Rd,addressing<LDR> {<cond>}SB|H|SH Rd,addressing<STR> {<cond>}H Rd,addressing
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Single Register TransferLDR load word into a register Rd <-mem32[address]
STR save byte or word from a register
Rd ->mem32[address]
LDRB load byte into a register Rd <-mem8[address]
STRB save byte from a register Rd ->mem8[address]
LDRH load half word into a register Rd <-mem16[address]
STRH save half word from a register Rd ->mem16[address]
LDRSB load signed byte into a register Rd <-SignExtend(mem8[address])
LDRSH load signed half word into a register
Rd <-SignExtend(mem16[address])
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Single Register Load Store Addressing Modes
The ARM instruction set provides different modes for addressing memorypreindex with writebackpreindexpostindex
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Index MethodsIndex
MethodData Base
Address Register
Example
preindex with writeback
mem[base+offset] base+offset
LDR r0, [r1, #4]!
preindex mem[base+offset] not updated
LDR r0, [r1, #4]
postindex mem[base] base+offset
LDR r0, [r1], #4
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Index MethodsPreindex with writeback calculates an address from a base register plus address offset and then updates that address base register with the new address.Preindex offset is same as the preindex with writeback but does not update the address base register. Postindex only updates the address base register after the address is used
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Single Register Load Store Addressing word or unsigned byteAddressing Mode & Index Method
Addressing Syntax
Preindex with immediate offset [Rn, #+/-offset_12]
Preindex writeback with scaled register offset[Rn, +/-Rm, shift #shift_imm]!
Preindex with register offset [Rn, +/-Rm]Preindex with scaled register offset [Rn, +/-Rm, shift
#shift_imm]Preindex writeback with immediate offset
[Rn, +/-offset_12]!Preindex writeback with register offset [Rn, +/-Rm]!
Immediate postindexed [Rn], +/-offset_12Register postindex [Rn], +/-RmScaled register postindex [Rn], +/-Rm, shift
#shift_imm
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Eg. of LDR instructions using different addressing modes
Instruction r0= r1+=Preindexwith writeback
LDR r0,[r1,#0x4]! mem32[r1+0x4] 0x4
Preindex
Postindex
LDR r0,[r1,r2]! mem32[r1+r2] r2LDR r0,[r1,r2,LSR#0x4]!
mem32[r1+(r2 LSR 0x4)]
r2 LSR 0x4LDR r0,[r1,#0x4] mem32[r1+0x4] not updatedLDR r0,[r1,r2] mem32[r1+r2] not updatedLDR r0,[r1,-r2,LSR#0x4]
mem32[r1-(r2 LSR 0x4)]
not updatedLDR r0,[r1],#0x4 mem32[r1] 0x4LDR r0,[r1],r2 mem32[r1] r2LDR r0,[r1],r2,LSR#0x4
mem32[r1] R2 LSR 0x4
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Variations of STRH instructions
Instruction Result r1+=Preindexwith writeback
STRH r0,[r1,#0x4]! mem16[r1+0x4] =r0
0x4
Preindex
Postindex
STRH r0,[r1,r2]! mem16[r1+r2] =r0 r2STRH r0,[r1,#0x4]! mem16[r1+0x4]
=r0not updated
STRH r0,[r1,r2] mem16[r1+r2] =r0 not updated
STRH r0,[r1],#0x4 mem16[r1] =r0 0x4STRH r0,[r1],r2 mem16[r1] =r0 r2
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Multiple Register TransferLoad–store multiple instructions can transfer multiple registers between memory and the processor in a single instruction.Moving blocks of data around memory and saving and restoring context stacks<LDM|STM>{<cond>}<addressing mode> Rn{!},<registers>{^}
LDM
load multiple registers
{Rd}*N <- mem32[start address + 4*N] optional Rn updated
STM save multiple registers
{Rd}*N -> mem32[start address + 4*N] optional Rn updated
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Addressing Mode for Load Store Multiple Instructions
Add:Mode
Description
Start Address
End Address
Rn!
IA increment after
Rn Rn +4*N-4 Rn+4*N
IB increment before
Rn + 4 Rn + 4*N Rn+4*N
DA decrement after
Rn–4*N + 4 Rn Rn+4*N
DB decrement before
Rn – 4*N Rn - 4 Rn+4*N
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Example 3.17Pre-condition of LDMIA Instruction
Post-condition of LDMIA Instruction
0x000080200x0000801C0x000080180x000080140x000080100x0000800C
0x000000050x000000040x000000030x000000020x000000010x00000000
r3=0x00000000r2=0x00000000r1=0x00000000r0=0x0000801
0
Address PointerDataMemory
Address
0x00008020
0x0000801C
0x00008018
0x00008014
0x00008010
0x0000800C
0x00000005
0x00000004
0x00000003
0x00000002
0x00000001
0x00000000
r3=0x00000003
r2=0x00000002
r1=0x00000001
r0=0x0000801C
Address PointerDataMemory
Address
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Example 3.17Pre-condition of LDMIB Instruction
Post-condition of LDMIB Instruction
0x000080200x0000801C0x000080180x000080140x000080100x0000800C
0x000000050x000000040x000000030x000000020x000000010x00000000
r3=0x00000000r2=0x00000000r1=0x00000000r0=0x0000801
0
Address PointerDataMemory
Address
0x00008020
0x0000801C
0x00008018
0x00008014
0x00008010
0x0000800C
0x00000005
0x00000004
0x00000003
0x00000002
0x00000001
0x00000000
r3=0x00000004
r2=0x00000003
r1=0x00000002
r0=0x0000801C
Address PointerDataMemory
Address
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Load Store Multiple pairs when base update used
Store Multiple Load Multiple
STMIA LDMDB
STMIB LDMDA
STMDA LDMIB
STMDB LDMIA
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Stack Operations
ARM architecture uses the load store multiple instructions to carry out stack operationsAscending –stack grows towards higher memory addressDescending –stack grows towards lower memory addressFull – sp points to the last item on the stackEmpty - sp points after the last item on the stack
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Addressing Methods for Stack Operations
Add:Mod
e
Description
Pop =LDM
Push =STM
FA full ascending LDMFA LDMDA STMFA STMIB
FD full descending
LDMFD
LDMIA STMFD STMDB
EA empty ascending
LDMEA LDMDB STMEA STMIA
ED empty descending
LDMED LDMIB STMED STMDA
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Stack Operations
ARM Thumb Procedure Call Standard (ATPCS) defines how routines are called and how registers are allocated. In ATPCS stacks are defined as being full descending stacks. LDMFD and STMFD instructions provide the pop and push functions.
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STMFD – full stack push operation
0x00008018
0x00008014
0x00008010
0x0000800C
0x00000001
0x00000002
Empty
Empty
sp
PRE DataAddress
0x00008018
0x00008014
0x00008010
0x0000800C
0x00000001
0x00000002
0x00000003
0x00000002sp
POST DataAddress
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STMED – empty stack push operation
0x00008018
0x00008014
0x00008010
0x0000800C
0x00000001
0x00000002
Empty
Empty
sp
PRE DataAddress
0x00008008 Empty
0x00008018
0x00008014
0x00008010
0x0000800C
0x00000001
0x00000002
0x00000003
0x00000002
sp
POST DataAddress
0x00008008 Empty
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SWAP Instruction
Swaps the contents of memory with the contents of a registerAtomic operation– it reads and writes a location in the same bus operation,preventing any other instruction from reading or writing to that location until it completes.
SWP{B}{<cond>} Rd, Rm, [Rn]
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SWAP Instruction
SWP swap a word between memory and a register
tmp=mem32[Rn]mem32[Rn]=RmRd=tmp
SWPB
swap a byte between memory and a register
tmp=mem8[Rn]mem8[Rn]=RmRd=tmp
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Software Interrupt Instruction
Causes a software interrupt exceptionProvides a mechanism to call OS routinesSWI{<cond>} SWI_numberSWI software
interrupt
lr_svc=address of instruction following the SWIspsr_svc=cpsrpc=vectors+0x8cpsr mode =SVCcpsr I = 1 (mask IRQ interrupts)
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Program Status Register Instructions
2 instructions to directly control a psrMRS - transfers the contents of cpsr or spsr into a registerMSR - transfers the contents of register into cpsr or spsr
N Z C V I F T Mode
31 30 29 28 7 6 5 4 0
Condition Flags
Processor Mode
Interrupt Masks
Thumb State
Function
BitFields
Flags[24:31] Status[16:23] Extension[8:15] Control[0:7]
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Program Status Register Instructions
MRS{<cond>} Rd,<cpsr|spsr>MSR{<cond>} <cpsr|spsr>_<fields>,RmMSR{<cond>} <cpsr|spsr>_<fields>,#immediate
MRS copy psr to a gpr Rd = psr
MSR move gpr to a psr psr[field] = Rm
MSR move an immediate value to a psr
psr[field] = immediate
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Coprocessor Instructions
Are used to extend the instruction setAdditional computation capabilityUsed to control the memory subsystemUsed only cores with a coprocessorCDP{<cond>} cp,opcode1,Cd,Cn{,opcode2}<MRC|MCR>{<cond>} cp, opcode1, Rd, Cn, Cm{, opcode2}<LDC|STC>{<cond>} cp, Cd, addressing
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Coprocessor Instructions
cp field represents the coprocessor number between p0 and p15opcode fields describe the operation to take place on the coprocessorCn, Cm and Cd describe registers within the coprocessorCP15 – system control purposesMRC p15, 0, r10, c0, c0, 0
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Coprocessor Instructions
CDP coprocessor data processing -perform an operation in a coprocessor
MRC MCR
coprocessor register transfer –move data to/from coprocessor registers
LDC STC
coprocessor memory transfers –load and store blocks of memory to/from a coprocessor
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Loading Constants
LDR Rd, =constantADR Rd, labelLDR Load constant
pseudoinstruction
Rd = 32 bit constant
ADR Load address pseudoinstruction
Rd = 32 bit relative address
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Loading Constants
Pseudo instruction Actual instruction
LDR r0, =0xff MOV r0, #0xff
LDR r0, =0x55555555 LDR r0, [pc,#offset_12]
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Loading 32-bit Constants
To allow larger constants to be loaded, the assembler offers a pseudo-instruction: LDR Rd,=const
This will either: Produce a MOV or MVN instruction to generate
the value (if possible) or Generate a LDR instruction with a PC-relative
address to read the constant from a literal pool (constant data area embedded in the code)
As this mechanism will always generate the best instruction for a given case, it is the recommended way of loading constant
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ARMv5E Extensions
Provide many new instructionsProvides greater flexibility and efficiency when manipulating 16 bit values
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ARMv5E Extensions
Instruction DescriptionCLZ {<cond>} Rd, Rm count leading zeroes
QADD {<cond>} Rd, Rm, Rn signed saturated 32 bit add
QDADD {<cond>} Rd, Rm, Rn signed saturated double 32 bit add
QDSUB {<cond>} Rd, Rm, Rn signed saturated double 32 bit subtract
QSUB {<cond>} Rd, Rm, Rn signed saturated 32 bit subtract
SMLAxy {<cond>} Rd, Rm, Rs, Rn signed multiply accumulate 32 bit
SMLALxy {<cond>} RdLo, RdHi, Rm, Rs signed multiply accumulate 64 bit
SMLAWy {<cond>} Rd, Rm, Rs, Rn signed multiply accumulate 32 bit
SMULxy {<cond>} Rd, Rm, Rs signed multiply
SMULWy {<cond>} Rd, Rm, Rs signed multiply
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Count Leading Zeroes Instruction
CLZCounts the number of zeroes between the MSB and the first bit set to 1 R1=0x00000010 CLZ R0,R1 R0 = 6
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Saturated ArithmeticOnce the highest number is exceeded the results remain at the maximum value of 0x7fffffffThis avoids the requirement for any additional code to check for possible overflows
QADD Rd=Rn + RmQDADD Rd=Rn +
(Rm*2)QSUB Rd=Rn - RmQDSUB Rd=Rn - (Rm*2)
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ARMv5.E Multiply Instructions
InstructionSigned Multiply [Accumulate]
Signed Result
Q Flag updated Calculation
SMLAxy (16-bit*16-bit)+32-bit 32-bit yes Rd=(Rm.x*Rs.y)+RnSMLALxy (16-bit*16-bit)+64-bit 64-bit - [RdHi,RdLo]+=
Rm.x*Rs.y
SMLAWxy ((32-bit*16-bit) >>16) +32-bit
32-bit yes Rd=((Rm*Rs.y) >>16) +Rn
SMULxy (16-bit*16-bit) 32-bit - Rd=Rm.x*Rs.y
SMULWy ((32-bit*16-bit) >>16)32-bit - Rd=(Rm*Rs.y) >>16
x and y select which 16 bits of a 32 bit register are used for the first and second operands
T for the top 16 bits and B for the bottom 16 bits
SMLATB r4, r1, r2, r3 r4 = (r1.T * r2.B) + r3
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Conditional Execution
The instruction only executes if the condition code flags pass a given condition or testIncrease performance & code density2 letter mnemonic (eg: AL)Conditional execution depends on Condition field Condition flags
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Summary
All ARM instructions are 32 bit in lengthArithmetic, logical, comparison & move instructions can all use the inline barrel shifter3 types of load store instruction – single register, multiple register, swapSWI & Program Status RegisterARMv5E –CLZ, saturation, improved multiply instructionsConditional execution