Fall 2006
Lillevik 333f06-l17 1University of Portland School of Engineering
EE 333
Computer OrganizationLecture 17
Controller designMicroprogramming overview
Fall 2006
Lillevik 333f06-l17 2University of Portland School of Engineering
EE 333
MIPS controller
InputsIR(31:25)
Outputs
Outputs
From Lecture 12
Fall 2006
Lillevik 333f06-l17 3University of Portland School of Engineering
EE 333
FSM architecture
Present
State
NS
Decoder
Output
Decoder
Inputs Outputs
Combo logic
ROM
MUX
Combo logic
ROM
MUX
Decoder
Flip Flops
Fall 2006
Lillevik 333f06-l17 4University of Portland School of Engineering
EE 333
Ten one-bit outputs
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Lillevik 333f06-l17 5University of Portland School of Engineering
EE 333
Three two-bit outputs
Fall 2006
Lillevik 333f06-l17 6University of Portland School of Engineering
EE 333
State diagram overview
All instructions require IF, ID (2 clk’s)
2 Clk
1-3 Clk
Fall 2006
Lillevik 333f06-l17 7University of Portland School of Engineering
EE 333
Full FSM state diagram
Inputs:Op
Outputs: 13 signals
States: 10
Fall 2006
Lillevik 333f06-l17 8University of Portland School of Engineering
EE 333
MDP16 controller
InputsIR(15:0)
Outputs
Fall 2006
Lillevik 333f06-l17 9University of Portland School of Engineering
EE 333
Controller architecture
PS flip-flops
NSD
ROM
Output
Decoder
Inputs Outputs
ROM contains microprogram
Fall 2006
Lillevik 333f06-l17 10University of Portland School of Engineering
EE 333
Controller overview
• Inputs: IR[0:15], EQ
• Outputs: ~15 signals
• Present state: 32-bits
• NSD or ROM: 256x32
Fall 2006
Lillevik 333f06-l17 11University of Portland School of Engineering
EE 333
MDP16 controllerPS
NSD
Inputs
Outputs
Fall 2006
Lillevik 333f06-l17 12University of Portland School of Engineering
EE 333
Controller outputs
Name Asserted Not AssertedPCinc PC is incremented by 1 NA
PCwr PC written with input number NA
EPC PC written to EPC address NA
IorD ALU addresses memory PC addresses memory
MEMwr Memory is written Memory is read
IRwr IR written with input number NA
MDRwr MDR written with input number NA
SPCwr SPC written with input number NA
PCsrc PC written with branch address PC written with jump address
Fall 2006
Lillevik 333f06-l17 13University of Portland School of Engineering
EE 333
Controller outputs, continued.
Name Value MeaningALUa
First ALU source
0
1
PC
R0
ALUb [0:1]
Second ALU source
00
01
10
11
R1
IR [0:5] sign extended
IR [0:5] zero extended
Zero
REGsrc
Source for REG writes
0
1
ALU
MDR
Fall 2006
Lillevik 333f06-l17 14University of Portland School of Engineering
EE 333
Controller outputs, continued.
Name Value MeaningREGrd [0:1]
Register reads
00
01
10
11
R1 = $0, R0 = $0
R1 = $0, R0 = $1
R1 = $1, R0 = $0
R1 = $1, R0 = $1
REGwr [0:1]
Register written
00
01
10
11
NA, none
$0
$1
$1, $0
Fall 2006
Lillevik 333f06-l17 15University of Portland School of Engineering
EE 333
Controller outputs, continued.
Name Value MeaningFunct [0:3]
Pgm control of ALU operation
0
1
2
3
4 - 7
8
9
A - F
Add
Sub
And
Or
Reserved (Default to Add)
Shift left logical
Shift right logical
Reserved (Default to Add)
Fall 2006
Lillevik 333f06-l17 16University of Portland School of Engineering
EE 333
Controller internals
Name Asserted Not AssertedBranch Branch Pgm to opcode address Use Pgm for next address
Rwr Write value into REG array NA
PCwrcond PC written with input number ONLY if EQ is asserted
NA
Fall 2006
Lillevik 333f06-l17 17University of Portland School of Engineering
EE 333
Which output is asserted?
Action Signal(s)
Increment the PC PCinc
Write to the IR IRwr
Write the branch address into the PC
PCsrc=1
PCwr
MDR data written to both $0 and $1
REGsrc=1
REGwr=11
Force the ALU to add Func=0000
Fall 2006
Lillevik 333f06-l17 18University of Portland School of Engineering
EE 333
Microprogramming overview
• Review instructions, understand goals
• Determine state diagram
• Microprogram individual instructions– List tokens on one line– Repeat for remaining clocks
• Merge all instructions
• Test, test, test
Fall 2006
Lillevik 333f06-l17 19University of Portland School of Engineering
EE 333
Microprogramming steps
ROM contents defined by assembler
ROMSource
FileAssembler
Object
File
.upg .txt B2LogicMicroAsm
Fall 2006
Lillevik 333f06-l17 20University of Portland School of Engineering
EE 333
MicroAsm
• Java application: MicroAsm.class, SavitchIn.class• Microinstruction: free format, no fixed fields
• Requires input file: text-only, file.upg
• Creates output file: file.txt• Errors: command line file name, file I/O,
unrecognizable token
• Execution: BlueJ or DOS command line
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Lillevik 333f06-l17 21University of Portland School of Engineering
EE 333
BlueJ execution
Must pass input file name to main method
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Lillevik 333f06-l17 22University of Portland School of Engineering
EE 333
Output file defines control ROM
Address Data
Fall 2006
Lillevik 333f06-l17 23University of Portland School of Engineering
EE 333
MDP16 op codes
Op code Instr Clocks
0 nop 2
1 R-fmt 4
2 sll 4
3 srl 4
4 lw 5
5 sw 4
Fall 2006
Lillevik 333f06-l17 24University of Portland School of Engineering
EE 333
MDP16 op codes, continued.
Op code Instr Clocks
6 beq 3
7 j 3
A addi 4
B subi 4
C andi 4
D ori 4
Fall 2006
Lillevik 333f06-l17 25University of Portland School of Engineering
EE 333
How many microinstructions?
Op code Instr Instr
0 nop
1 R-fmt
2 sll
3 srl
4 lw
5 sw
Fall 2006
Lillevik 333f06-l17 26University of Portland School of Engineering
EE 333
How many microinstructions?
Op code Instr Instr
6 beq
7 j
A addi
B subi
C andi
D ori
Fall 2006
Lillevik 333f06-l17 27University of Portland School of Engineering
EE 333
Partial MDP16 state diagram
A
G
C
D
E
F
H
B
JI
Lw or SwR-fmt Beq Jump
Reset
Lw Sw
Fall 2006
Lillevik 333f06-l17 28University of Portland School of Engineering
EE 333
MDP16 state diagram
ID
sllno
p
R-fmt
sw
srl lw
addi
beq j ori
subi
andi
IFReset
1- 3
add
itio
nal c
lock
s
2 clocks
Fall 2006
Lillevik 333f06-l17 29University of Portland School of Engineering
EE 333
Fall 2006
Lillevik 333f06-l17 30University of Portland School of Engineering
EE 333
Which output is asserted?
Action Signal(s)
Increment the PC PCinc
Write to the IR IRwr
Write the branch address into the PC
PCwr
PCsrc
MDR data written to both $0 and $1
REGsrc
REGwr [0:1] = 11
Force the ALU to add Funct [0:3] = 0000
Fall 2006
Lillevik 333f06-l17 31University of Portland School of Engineering
EE 333
How many microinstructions?
Op code Instr Instr
0 nop 2
1 R-fmt 4
2 sll 4
3 srl 4
4 lw 5
5 sw 4
Fall 2006
Lillevik 333f06-l17 32University of Portland School of Engineering
EE 333
How many microinstructions?
Op code Instr Instr
6 beq 3
7 j 3
A addi 4
B subi 4
C andi 4
D ori 4