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VLSI DESIGN
MOS TRANSISTOR
1
The MOS Transistor
How old is the idea?
The first experimental observation of the surface and its impact on the electric current was disclosed in the paper “The action of light on Selenium” by W. G. Adams and R. E. Day in the Proceeding of Royal Society in 1876.
2
Field effect control device proposed by J. Lilienfield
1928
3
The surface controlled transistor has a very bad driftproblem. We have been fooling with this problem for along time and have no hope of an early solution. In fact,I am not sure I have a strong hope of an eventual solution.
Gordon MooreFairchild Progress Report, February 15, 1962
Although the MOS devices are still at the research stagebecause of fabrication problems and incomplete physicalunderstanding, their impact on microelectronics is expected to be significant.
George Warfield, RCAElectron Device Meeting, October, 1962
About MOSFET
4
RCA Announcement of MOS transistor (February 11, 1963)
5
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MOS Field-Effect Transistors (MOSFETs)
Compared to BJTs, MOSFETs can be made quite small (i.e., requiring a small area on the silicon IC chip).
Their manufacturing process is relatively simple.
Their operation requires comparatively little power.
Ways to implement digital and analog functions utilizing MOSFETs almost exclusively (i.e., with very few or no resistors). Possible to pack large numbers of MOSFETs (>200 million!) on a single IC chip to implement very sophisticated, very-Iarge-scale- integrated (VLSI) circuits such as those for memory and micro- processors.
Analog circuits such as amplifiers and filters are also implemented in MOS Technology.
6
Physical structure of the enhancement-type NMOS transistor
7
3D Perspective
8
L = 0.1 to 3 m cross-section. Typically, W = 0.2 to 100 m, and the thickness of the oxide layer (tox) is in the range of 2 to 50 nm.
9
Creating a Channel for Current Flow
N-channel MOSFET is formed in a p-type substrate: Channel created by inverting the substrate surface from p type to n type. Hence the induced channel is also called an inversion layer.
Gate voltage at which a sufficient number of mobile electrons accumulate---- Threshold voltage Vt
10
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Applying a Small VDS . .
VDS causes a current lD to flow through source and drain.Conductance of the channel is proportional to the excess gate voltage VGS above Vt
11
The iD–vDS characteristics of the MOSFET when the voltage applied between drain and source, vDS, is kept small. The device operates as a linear resistor whose value is controlled by vGS.
12
Operation as VDS Is Increased
Channel depth depends on this voltageChannel is no longer of uniform depth;Channel will take the tapered form shown:Deepest at the source end and shallowest at the drain end. As VDS is increased, the channel becomes more tapered . and its resistance increases correspondingly
13
14
Derivation of the iD-VDS Relationship .
15
Cox =
ox/tox = 3.9 o =3.9 x 8.854 x 10-12 = 3.45 x 10-11F/ m
ox
dq = -Cox(W dx)[vGS – v(x) - V t ]
E(x) =
dx_ dv(x)
Electrtric field E(x) causes the electron charge dq to drift toward the drain with a velocity dx/dt
dxdt = -n E(x) = n
dx dv(x)
i = dq/dt = dqdx
dxdt
i = - nCox W [ VGS – v(x) – Vt ] dv(x)
dx
16
iDdx = nCoxW [VGS- Vt- v(x)] dv(x)
Integrating both sides of this equation from x= 0 to x=L and, correspondingly, for v(0) = 0 and v(L)=vDS
iDdx = nCoxW [VGS- Vt- v(x)] dv(x) L
0 DSv
0
iD = (nCox) [ (VGS- Vt)VDS – 1/2 V2DS
L
W
At the beginning of the saturation region substituting VDS = VGS - V t ,
2
2
1tGSoxnD Vv
L
WCi
17
nCox is a constant determined by the process technology used to fabricate the n-channel MOSFET. It is known as the process transconductance parameter.
Denoted k'n and has the dimensions of A/V2
k'n = nCox
(Triode region)
(Saturation region)
Aspect Ratio of the MOSFET
Different notations: Kn, K'n n; C"ox Tox ; VT0,VTN,VTP;
18
Consider a process technology for which Lmin =0.4 m, tox = 8 nm, n = 450 cm2/V- s, and Vt = 0.7 V. (a) Find Cox and k'n .(b) For a MOSFET with W /L = 8 m/0.8 m, calculate the values of VGS and VDSmin needed to operate the transistor in the saturation region with a dc current ID = 100 A. (c) For the device in (b), find the value of VGS reguired to cause the device to operate as a l000- resistor for very small VDS .
19
(b) For operation in the saturation region,
(c) For the MOSFET in the triode region with VDS very small,
20
21
Fabricated on an n-type substratep + regions for the drain and source Has holes as charge carriers VGS and VDS are negative and the threshold voltage Vt . is negative
It is important to be familiar with the PMOS transistor for two reasons:
1.PMOS devices are still available for discrete-circuit design
2. Both PMOS and NMOS transistors are utilized in complementary . MOS or CMOS circuits, which is currently the dominant MOS . . ………technology.
The p-Channel MOSFET
22
Cross-section of a CMOS integrated circuit
Note that the PMOS transistor is formed in a separate n-type region, known as an n well. Another arrangement is also possible in which an n-type body is used and the n device is formed in a p well. Not shown are the connections made to the p-type body and to the n well; the latter functions as the body terminal for the p-channel device.
23
Operating the MOS Transistor in the Subthreshold Region .
It has been found that for values of VGS smaller than but close to Vt a small drain current flows. In this subthreshold region of operationDrain current is exponentially related to VGS.
There are special, but a growing number of applications thatmake use of subthreshold operation.
24
Circuit symbol for the n-channel enhancement-type MOSFET
25
CURRENT-VOLTAGE CHARACTERIST!CS
n-channel enhancement-mode MOSFET operates in the triode region when VGS is greater than Vt and the drain voltage is lower than the gate voltage by at least Vt volts.
26
In the triode region
Near the origin
The boundary between the triode region and the saturation region is characterized by VDS = VGS- Vt (Boundary)
Subst.
27
Vov=VGS-Vt
Gate-to-source overdrive
To operate the MOSFET in the saturation region,
VGS V t (Induced channel)
Pinched off at the drain Raising VDS
G-to-D Volt. below V t ,
VGD < = V t (Pinched-off channel)
In terms of VDS :
VDS = > VGS - Vt (Pinched-off channel)
28
The iD–vGS characteristic for an enhancement-type NMOS transistor in saturation
29
Large-signal equivalent-circuit model of an n-channel MOSFET operating in the saturation region
30
The relative levels of the terminal voltages of the enhancement NMOS transistor for operation in the triode
region and in the saturation region.
31
Finite Output Resistance in Saturation
DS
G+5V
Vt = 0.5V
0V 0.1V 2.0V3.0V
4.5V
Ideal : Once the channel is pinched off at the drain end, further increases in VDS have no effect on the channel's shape.
32
DS
G+5V
Vt = 0.5V
0V6.0V
4.5V
Practice : Increasing VDS beyond VDSsat does affect the channel. Channel pinch-off point is moved slightly away from the drain, toward the source. The voltage across the channel remains constant at VGS - Vt = VDSsat. Additional voltage applied to the drain appears as a voltage drop across the narrow depletion region between the end of the channel and the drain region. This voltage accelerates the electrons that reach the drain end of the channel. The channel length is in effect reduced, from L to L – ΔL.
Phenomenon known as channel-length modulation . iD is inversely proportional to the channel length. iD increases with VDS 33
34
ΔL = ' vDS
' is a process-technology parameter with the dimensions of m/V
35
The MOSFET parameter VA depends on the process technology and, for a given process, is proportional to the channel length L.
Effect of VDS on iD in the saturation region
36
Drain current without channel-length modulation
37
Large-signal equivalent circuit model of the n-channel MOSFET
Large-signal equivalent circuit model of the n-channel MOSFET in saturation, incorporating the output resistance ro. The output resistance models the linear dependence of iD on vDS
38
p-Channel MOSFET
39
Characteristics of the p-Channel MOSFET
(a) Circuit symbol for the p-channel enhancement-type MOSFET. (b) Modified symbol with an arrowhead on the source lead. (c) Simplified circuit symbol for the case where the source is connected to the body. (d) The MOSFET with voltages applied and the directions of current flow indicated. Note that vGS and vDS are negative and iD flows out of the drain terminal.
40
VGS < = Vt (Induced channel)
VSG = |Vt|
VDs > = VGS - Vt (Continuous channel)
Drain voltage must be higher than the gate voltage by at least |Vt|
0.25 to 0.5n
To operate in saturation, VDS < = VGS - Vt (Pinched-off channel)
Drain voltage must be lower than (gate voltage + I Vtl)
Negative. 41
The relative levels of the terminal voltages of the enhancement-type PMOS transistor for operation in the triode region and in the saturation region.
42
The Role of the Substrate - The Body Effect
Source terminal connected to the substrate (or body) terminal B, No ProblemIn ICs, the substrate is usually common to many MOS transistors.
Substrate connected to the most negative power supply . in an NMOS circuit (most positive in a PMOS circuit).
To maintain th
e cutoff conditio
n for
all the substra
te-to-channel ju
nctions
Resulting reverse-bias voltage between source and body . (VSB) wIll have an effect on device operation.
43
The reverse bias voltage will widen the depletion region .This in turn reduces the channel depth. To return the channel to its former state, VGS has to be increased. The effect of VSB on the channel can be represented as a change in the threshold voltage Vt . Increasing the reverse substrate bias voltage VSB results in an increase in Vt .
Fabrication-process parameter
Vto Threshold voltage for VSB = 0
f Physical parameter with (2 f ) typically 0.6 V
44
q Electron charge (1.6 x 10-19 C)
NA Doping concentration of the p-type substrate
s Permittivity of silicon (11.70 = 11.7 x 8.854 x 10-14 = 1.04 X 10-12 F/cm)
The parameter has the dimension of V and is typically 0.4 V½
p-Channel DevicesVSB by I VSBI
NA by ND ,
2f is typically 0.75 V
is typically -0.5 V½ (Negative)
45
46
Review
Polysilicon GateSiO2
Insulator
n+ n+
p substrate
channel
Source Drain
n transistor
G
S
D
SB
LW
G
S
D
substrate connectedto GND
p+ p+
n substrate
channel
Source Drain
p transistor
G
S
D
SB
Polysilicon GateSiO2
Insulator L
W
G
substrate connectedto VDD
Transistor Structure
47
N Transistor Operation - Cutoff
Vgs << Vt : Transistor OFF Majority carrier in channel (holes) No current from source to drain
source drain
VS=0 VGS=0 VDS=0
channel Some Values for Vtn:Book (0.5µm) : 0.7VAMI (1.5µm): 0.61V
Review……
48
N Transistor Operation - Subthreshold
0 < Vgs < Vt : Depletion region Electric field repels majority carriers (holes) Depletion region forms - no carriers in channel No current flows (except for leakage current)
source drain
VS=0 0<VGS<VT VDS=0
depletion region
Review……
49
N Transistor Operation - ON
Vgs > Vt , VDS=0: Transistor ON Electric field attracts minority carriers (electrons) Inversion region forms in channel Depletion region insulates channel from substrate Current can now flow from drain to source!
VS=0 VGS>VT VDS=0
inversion layer - channel
source drain
Review……
50
N Transistor Operation - Linear Vgs > Vt , VDS < VGS - Vt : Linear (Active) mode
Combined electric fields shift channel and depletion region Current flow dependent on VGS, VDS
VDS<VGS-VTVS=0 VGS>VT
source drain
Review……
51
N Transistor Operation - Saturation
Vgs > Vt , VDS >VGS -Vt : Saturated mode Channel “pinched off” Current still flows due to electron drift Current flow dependent on VGS
VDS>VGS-VTVS=0 VGS>VT
source drain
pinch-off point
Review……
52
P Transistor Operation Opposite of N-Transistor Vgs >> Vt : Transistor OFF
Majority carrier in channel (electrons) No current from source to drain
0 > Vgs > Vt : Depletion region Electric field repels majority carriers (electrons) Depletion region forms - no carriers in channel No current flows (except for leakage current)
Vgs < Vt , VDS=0: Transistor ON Electric field attracts minority carriers (holes) Inversion region forms in channel Depletion layer insulates channel from substrate Current can now flow from source to drain!
Review……
53
P Transistor Modes of Operation
Vgs < Vt , VDS > VGS - VT : Linear (Active) mode Combined electric fields shift channel and depletion region Current flow dependent on VGS, VDS
Vgs < Vt , VDS < VGS - VT : Saturation mode Channel “pinched off” Current still flows due to hole drift Current flow dependent on VGS
Some Values for Vtp:Book (0.5µm) : -0.8VAMI (1.5µm): -1.02V
Review……
54
I-V Characteristics of MOS Transistors
VDS
ID
VGS=1.5V
VGS=2.5V
VGS=5V
VDS
ID
VGS=-1.5V
VGS=-2.5V
VGS=-5V
linear saturation
linearsaturation
n transistor p transistor
55
Transistors as Switches We can view MOS transistors as electrically controlled
switches Voltage at gate controls path from source to drain
g
s
d
g = 0
s
d
g = 1
s
d
g
s
d
s
d
s
d
nMOS
pMOS
OFF ON
ON OFF
56
CMOS Inverter
A Y
0
1
VDD
A Y
GNDA Y
57
CMOS Inverter
A Y
0
1 0
VDD
A=1 Y=0
GND
ON
OFF
A Y
58
CMOS Inverter
A Y
0 1
1 0
VDD
A=0 Y=1
GND
OFF
ON
A Y
59
CMOS Fabrication
CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press On each step, different materials are deposited or
etched Easiest to understand by viewing both top and cross-
section of wafer in a simplified manufacturing process
60
Inverter Cross-section Typically use p-type substrate for nMOS transistors Requires n-well for body of pMOS transistors
n+
p substrate
p+
n well
A
YGND VDD
n+ p+
SiO2
n+ diffusion
p+ diffusion
polysilicon
metal1
nMOS transistor pMOS transistor
61
Well and Substrate Taps Substrate must be tied to GND and n-well to VDD Metal to lightly-doped semiconductor forms poor
connection called Shottky Diode Use heavily doped well and substrate contacts / taps
n+
p substrate
p+
n well
A
YGND VDD
n+p+
substrate tap well tap
n+ p+
62
Inverter Mask Set Transistors and wires are defined by masks Cross-section taken along dashed line
GND VDD
Y
A
substrate tap well tapnMOS transistor pMOS transistor
0: Introduction Slide 63
Detailed Mask Views
Six masks n-well Polysilicon n+ diffusion p+ diffusion Contact Metal
Metal
Polysilicon
Contact
n+ Diffusion
p+ Diffusion
n well
64
Fabrication Steps Start with blank wafer Build inverter from the bottom up First step will be to form the n-well
Cover wafer with protective layer of SiO2 (oxide) Remove layer where n-well should be built Implant or diffuse n dopants into exposed wafer Strip off SiO2
p substrate
65
Oxidation
Grow SiO2 on top of Si wafer 900 – 1200 C with H2O or O2 in oxidation furnace
p substrate
SiO2
66
Photoresist
Spin on photoresist Photoresist is a light-sensitive organic polymer Softens where exposed to light
p substrate
SiO2
Photoresist
67
Lithography Expose photoresist through n-well mask Strip off exposed photoresist
p substrate
SiO2
Photoresist
0: Introduction Slide 68
Etch
Etch oxide with hydrofluoric acid (HF) Seeps through skin and eats bone; nasty stuff!!!
Only attacks oxide where resist has been exposed
p substrate
SiO2
Photoresist
69
Strip Photoresist Strip off remaining photoresist
Use mixture of acids called piranah etch Necessary so resist doesn’t melt in next step
p substrate
SiO2
70
n-well n-well is formed with diffusion or ion implantation Diffusion
Place wafer in furnace with arsenic gas Heat until As atoms diffuse into exposed Si
Ion Implantation Blast wafer with beam of As ions Ions blocked by SiO2, only enter exposed Si
n well
SiO2
71
Strip Oxide
Strip off the remaining oxide using HF Back to bare wafer with n-well Subsequent steps involve similar series of steps
p substraten well
Polysilicon Deposit very thin layer of gate oxide
< 20 Å (6-7 atomic layers) Chemical Vapor Deposition (CVD) of silicon layer
Place wafer in furnace with Silane gas (SiH4) Forms many small crystals called polysilicon Heavily doped to be good conductor
Thin gate oxidePolysilicon
p substraten well
73
Polysilicon Patterning Use same lithography process to pattern polysilicon
Polysilicon
p substrate
Thin gate oxidePolysilicon
n well
74
Self-Aligned Process
Use oxide and masking to expose where n+ dopants should be diffused or implanted
N-diffusion forms nMOS source, drain, and n-well contact
p substraten well
75
N-diffusion Pattern oxide and form n+ regions Self-aligned process where gate blocks diffusion Polysilicon is better than metal for self-aligned gates
because it doesn’t melt during later processing
p substraten well
n+ Diffusion
76
N-diffusion cont… Historically dopants were diffused Usually ion implantation today But regions are still called diffusion
n wellp substrate
n+n+ n+
77
N-diffusion cont.
Strip off oxide to complete patterning step
n wellp substrate
n+n+ n+
78
P-Diffusion
Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact
p+ Diffusion
p substraten well
n+n+ n+p+p+p+
79
Contacts Now we need to wire together the devices Cover chip with thick field oxide Etch oxide where contact cuts are needed
p substrate
Thick field oxide
n well
n+n+ n+p+p+p+
Contact
80
Metalization Sputter on aluminum over whole wafer Pattern to remove excess metal, leaving wires
p substrate
Metal
Thick field oxide
n well
n+n+ n+p+p+p+
Metal
81
Layout
Chips are specified with set of masks Minimum dimensions of masks determine transistor size
(and hence speed, cost, and power) Feature size f = distance between source and drain
Set by minimum width of polysilicon Feature size improves 30% every 3 years or so Normalize for feature size when describing design rules Express rules in terms of = f/2
E.g. = 0.3 m in 0.6 m process
82
Simplified Design Rules Conservative rules to get you started
83
Inverter Layout Transistor dimensions specified as Width / Length
Minimum size is 4 / 2, sometimes called 1 unit In f = 0.6 m process, this is 1.2 m wide, 0.6 mm
long
84
Summary
MOS Transistors are stack of gate, oxide, silicon Can be viewed as electrically controlled switches Build logic gates out of switches Draw masks to specify layout of transistors Now you know everything necessary to start designing
schematics and layout for a simple chip!
85
LOCOS Fabrication Process
86
LOCOS DefinedLOCOS = LOCal Oxidation of Silicon
Defines a set of fabrication technologies wherethe wafer is masked to cover all active regions
thick field oxide (FOX) is grown in all non-active regions
Used for electrical isolation of CMOS devices
Relatively simple to understand so often used to introduce/describe CMOS fabrication flows
Not commonly used in modern fabricationother techniques, such as Shallow Trench Isolation (STI) are currently more common than LOCOS
87
LOCOS –step 1Form N-Well regions Grow oxide Deposit photoresist
Layout view
Cross section view
p-type substrate
NWELL mask
NWELL mask
oxide
photoresist
88
LOCOS –step 1Form N-Well regions Grow oxide Deposit photoresist Pattern photoresist
NWELL Mask expose only n-well
areas
Layout view
Cross section view
p-type substrate
NWELL mask
NWELL mask
oxide
photoresist
89
LOCOS –step 1Form N-Well regions Grow oxide Deposit photoresist Pattern photoresist NWELL Mask expose only n-well
areas Etch oxide Remove photresist
Layout view
Cross section view
p-type substrate
oxide
90
LOCOS –step 1Form N-Well regions Grow oxide Deposit photoresist Pattern photoresist
NWELL Mask expose only n-well
areas Etch oxide Remove photoresist Diffuse n-type dopants
through oxide mask layer
Layout view
Cross section view
p-type substrate
n-well
91
LOCOS –step 2Form Active Regions Deposit SiN over wafer Deposit photoresist over
SiN layer
ACTIVE mask
ACTIVE mask
SiN photoresist
p-type substrate
n-well
92
LOCOS –step 2
ACTIVE mask
ACTIVE mask
SiN photoresist
Form Active Regions Deposit SiN over wafer Deposit photoresist over
SiN layer Pattern photoresist
*ACTIVE MASK p-type substrate
n-well
93
LOCOS –step 2
ACTIVE mask
SiN photoresist
Form Active Regions Deposit SiN over wafer Deposit photoresist over
SiN layer Pattern photoresist
*ACTIVE MASK Etch SiN in exposed
areas leaves SiN mask which
blocks oxide growth
p-type substrate
n-well
94
LOCOS –step 2
ACTIVE mask
p-type substrate
n-well
Form Active Regions Deposit SiN over wafer Deposit photoresist over
SiN layer Pattern photoresist
*ACTIVE MASK Etch SiN in exposed
areas leaves SiN mask which
blocks oxide growth Remove photoresist Grow Field Oxide (FOX)
thermal oxidation
FOX
95
LOCOS –step 2
ACTIVE mask
p-type substrate
n-well
Form Active Regions Deposit SiN over wafer Deposit photoresist over
SiN layer Pattern photoresist
*ACTIVE MASK Etch SiN in exposed
areas leaves SiN mask which
blocks oxide growth Remove photoresist Grow Field Oxide (FOX)
thermal oxidation Remove SiN
FOX
96
LOCOS –step 3Form Gate (Poly layer) Grow thin Gate Oxide
over entire wafer negligible effect on
FOX regionsgate oxide
97
LOCOS –step 3Form Gate (Poly layer) Grow thin Gate Oxide
over entire wafer negligible effect on
FOX regions Deposit Polysilicon Deposit Photoresist
gate oxide
POLY mask
POLY mask
polysilicon
98
LOCOS –step 3Form Gate (Poly layer) Grow thin Gate Oxide
over entire wafer negligible effect on
FOX regions Deposit Polysilicon Deposit Photoresist Pattern Photoresist
*POLY MASK Etch Poly in exposed
areas Etch/remove Oxide
gate protected by poly
gate oxide
POLY mask
POLY mask
99
LOCOS –step 3Form Gate (Poly layer) Grow thin Gate Oxide
over entire wafer negligible effect on
FOX regions Deposit Polysilicon Deposit Photoresist Pattern Photoresist
*POLY MASK Etch Poly in exposed
areas Etch/remove Oxide
gate protected by poly
gate oxide
100
LOCOS –step 4Form pmos S/D Cover with photoresist
PSELECT mask
PSELECT mask
101
LOCOS –step 4Form pmos S/D Cover with photoresist Pattern photoresist
*PSELECT MASK
POLY mask
PSELECT mask
102
LOCOS –step 4Form pmos S/D Cover with photoresist Pattern photoresist
*PSELECT MASK Implant p-type dopants Remove photoresist
p+ dopant
POLY mask
p+ dopant
103
LOCOS –step 5Form nmos S/D Cover with photoresist
POLY mask
NSELECT mask
p+
p+
p+
n
104
LOCOS –step 5Form nmos S/D Cover with photoresist Pattern photoresist
*NSELECT MASK
POLY mask
NSELECT mask
p+
p+
p+
n
105
LOCOS –step 5Form nmos S/D Cover with photoresist Pattern photoresist
*NSELECT MASK Implant n-type dopants Remove photoresist
n+ dopant
POLY mask
n+ dopant
p+
p+
p+
n
n+
n+
n+
106
LOCOS –step 6Form Contacts Deposit oxide Deposit photoresist
CONTACT mask
p+
p+
p+
n
n+
n+
n+
CONTACT mask
107
LOCOS –step 6Form Contacts Deposit oxide Deposit photoresist Pattern photoresist
*CONTACT Mask One mask for both
active and poly contact shown
CONTACT mask
p+
p+
p+
n
n+
n+
n+
CONTACT mask
108
LOCOS –step 6Form Contacts Deposit oxide Deposit photoresist Pattern photoresist
*CONTACT Mask One mask for both
active and poly contact shown
Etch oxide
p+
p+
p+
n
n+
n+
n+
109
LOCOS –step 6Form Contacts Deposit oxide Deposit photoresist Pattern photoresist
*CONTACT Mask One mask for both
active and poly contact shown
Etch oxide Remove photoresist Deposit metal1
immediately after opening contacts so no native oxide grows in contacts
Planerize make top level
p+
p+
p+
n
n+
n+
n+
110
LOCOS –step 7Form Metal 1 Traces Deposit photoresist
p+
p+
p+
n
n+
n+
n+
METAL1 mask
METAL1 mask
111
LOCOS –step 7Form Metal 1 Traces Deposit photoresist Pattern photoresist
*METAL1 Maskp+
p+
p+
n
n+
n+
n+
METAL1 mask
METAL1 mask
112
LOCOS –step 7Form Metal 1 Traces Deposit photoresist Pattern photoresist
*METAL1 Mask Etch metal
p+
p+
p+
n
n+
n+
n+
metal over poly outside of cross section
113
LOCOS –step 7Form Metal 1 Traces Deposit photoresist Pattern photoresist
*METAL1 Mask Etch metal Remove photoresist
p+
p+
p+
n
n+
n+
n+
114
LOCOS –step 8
Form Vias to Metal1 Deposit oxide Planerize oxide Deposit photoresist
p+
p+
p+
n
n+
n+
n+
VIA mask
VIA mask
115
LOCOS –step 8Form Vias to Metal1 Deposit oxide Planerize Deposit photoresist Pattern photoresist
*VIA Mask
p+
p+
p+
n
n+
n+
n+
VIA mask
VIA mask
116
LOCOS –step 8Form Vias to Metal1 Deposit oxide Planerize Deposit photoresist Pattern photoresist
*VIA Mask Etch oxide Remove photoresist
p+
p+
p+
n
n+
n+
n+
117
LOCOS –step 8Form Vias to Metal1 Deposit oxide Planerize Deposit photoresist Pattern photoresist
*VIA Mask Etch oxide Remove photoresist Deposit Metal2
p+
p+
p+
n
n+
n+
n+
118
LOCOS –step 9Form Metal2 Traces Deposit photoresist
p+
p+
p+
n
n+
n+
n+
METAL2 mask
METAL2 mask
119
LOCOS –step 9Form Metal2 Traces Deposit photoresist Pattern photoresist
*METAL2 Maskp+
p+
p+
n
n+
n+
n+
METAL2 mask
METAL2 mask
Page 120
LOCOS –step 9Form Metal2 Traces Deposit photoresist Pattern photoresist *METAL2 Mask Etch metal
p+
p+
p+
n
n+
n+
n+
121
Latch-up
CMOS ICs have parasitic silicon-controlled rectifiers (SCRs).
When powered up, SCRs can turn on, creating low-resistance path from power to ground. Current can destroy chip.
Early CMOS problem. Can be solved with proper circuit/layout structures.
122
Parasitic SCR
Circuit I-V behavior
123
Parasitic Transistors Parasitic bipolar transistors form at N/P junctions Latchup - when parasitic transistors turn on Preventing latchup:
Add substrate contacts (“tub ties”) to reduce Rs, Rw OR
Use Silicon-on-Insulator
n+ n+
p substrate
p+ p+
n well
Vdd
Rs
Rw
Gnd
124
Controlling Latchup - Substrate Contacts Purpose: connect well/substrate to power supply Alternative term: tub tie Recommendations (source: Weste & Eshraghian)
Conservative: 1 substrate contact for every supply connection
Less conservative: 1 substrate contact for every 5-10 transistors
High-current circuits: use guard rings
n+ n+
p substrate
p+ p+
n well
Vdd
Rs
Rw
Gnd
n+p+SubstrateContact
SubstrateContact
125
Solution to latch-up
Use tub ties to connect tub to power rail. Use enough to create low-voltage connection.
126
Scaling of CMOSAdvances in device manufacturing technology allow for a steady reduction of the minimum feature size such as the minimum transistor channel length realizable on a chip.
Evolution of (average) minimum channel length of MOS transistors over time.
127
Scaling of CMOS…. Scaling refers to the systematic reduction of transistor
dimensions from one generation to the next.
It reduces the parasitic capacitances and also the carrier transit times in the devices.
Improves the circuit speed.
It narrows the performance gap between CMOS and logic gates based on bipolar transistors.
Reduction of the transistor dimensions improves the packing density of CMOS.
128
Full Scaling of CMOS “Full Scaling,” involves scaling all dimensions and voltages by
the same factor, 1/s, where s is greater than one.
Scaling factor of 1/2 is used (s = 2 ), then the packing density in transistors per square centimeter will be doubled.
The goal is to keep the electrical field patterns in the scaled device identical to those in the original device.
Keeping the electrical fields constant ensures the physical integrity of the device and avoids breakdown or other secondary effects.
This scaling leads to greater device density (Area), higher performance (Intrinsic Delay), and reduced power consumption (P).
129
Full Scaling of CMOS
130
Fixed-Voltage Scaling
In reality, full scaling is not a feasible option:
1. To keep new devices compatible with existing components, voltages cannot be scaled arbitrarily.
2. Having to provide for multiple supply voltages adds considerably to the cost of a system.
As a result, voltages have not been scaled down along with feature sizes, and designers adhere to well-defined standards for supply voltages and signal levels.
131
Scaling scenarios for short-channel devices
132
CMOS INVERTER
CMOS Inverter
Polysilicon
In
Out
V DD
GND
PMOS
2
Metal 1
NMOS
OutIn
VDD
PMOS
NMOS
Contacts
N Well
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CMOS INVERTER
A CMOS inverter uses one NMOS and one PMOS transistor.
A simplified model of the inverter for a high input level. The output is forced to zero through the on-resistance of the NMOS transistor.
Simplified model of theinverter for a low input level. The output is pulled to VDD through the on-resistance of the PMOS transistor.
135
DC Response
DC Response: Vout vs. Vin for a gate Ex: Inverter
When Vin = 0 -> Vout = VDD When Vin = VDD -> Vout = 0 In between, Vout depends on
transistor size and current
By KCL, must settle such thatIdsn = |Idsp|
We could solve equations But graphical solution gives more insight
Idsn
Idsp Vout
VDD
Vin
CMOS Inverter -
136
Transistor Operation Current depends on region of transistor behavior For what Vin and Vout are NMOS and PMOS in
Cutoff? Linear? Saturation?
VDS
ID
VGS=1.5V
VGS=2.5V
VGS=5V
linear saturation
n transistor
137
NMOS Operation
Cutoff Linear Saturated
Vgsn < VtnVin < Vtn
Vgsn > VtnVin > VtnVdsn < Vgsn – VtnVout < Vin - Vtn
Vgsn > VtnVin > VtnVdsn > Vgsn – VtnVout > Vin - Vtn
Idsn
Idsp Vout
VDD
Vin
Vgsn = Vin
Vdsn = Vout
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PMOS Operation
Cutoff Linear Saturated
Vgsp < VtpVin < VDD + Vtp
Vgsp < VtpVin < VDD + VtpVdsp > Vgsp – VtpVout > Vin – Vtp
Vgsp < VtpVin < VDD + VtpVdsp < Vgsp – VtpVout < Vin - Vtp
Idsn
Idsp Vout
VDD
Vin
Vgsp = Vin - VDD
Vdsp = Vout - VDD
Vtp < 0
139
I-V Characteristics Make PMOS is wider than NMOS such that n = p
Vgsn5
Vgsn4
Vgsn3
Vgsn2
Vgsn1
Vgsp5
Vgsp4
Vgsp3
Vgsp2
Vgsp1
VDD
-VDD
Vdsn
-Vdsp
-Idsp
Idsn
0
140
Current vs. Vout, Vin
Vin5
Vin4
Vin3
Vin2Vin1
Vin0
Vin1
Vin2
Vin3Vin4
Idsn, |Idsp|
VoutVDD
0
1
2
3
4
141
Load Line Analysis
Vin5
Vin4
Vin3
Vin2Vin1
Vin0
Vin1
Vin2
Vin3Vin4
Idsn, |Idsp|
VoutVDD
For a given Vin: Plot Idsn, Idsp vs. Vout Vout must be where |currents| are equal in magnitude
Idsn
Idsp Vout
VDD
Vin
0
1
2
3
4
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Load Line Analysis Vin = 0 Vin = 0.8VDD Vin =
0.4VDD Vin =
0.6VDD Vin =
0.2VDD Vin =
VDD
CMOS Inverter Load Characteristics
IDn
Vout
Vin = 2.5
Vin = 2
Vin = 1.5
Vin = 0
Vin = 0.5
Vin = 1
NMOS
Vin = 0
Vin = 0.5
Vin = 1Vin = 1.5
Vin = 2
Vin = 2.5
Vin = 1Vin = 1.5
PMOS
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DC Transfer Curve Transcribe points onto Vin vs. Vout plot
Vin5
Vin4
Vin3
Vin2
Vin1
Vin0
Vin1
Vin2
Vin3
Vin4
VoutVDD
CVout
0
Vin
VDD
VDD
A B
DE
Vtn VDD/2 VDD+Vtp
Vin0 Vin1 Vin2
Vin3Vin4 Vin5
Click to edit the outline text format Second
Outline Level Third Outline
LevelFourth Outline Level Fifth Outline Level
Sixth Outline Level
Seventh Outline Level
Eighth Outline Level
Ninth Outline LevelClick to edit Master text styles Second level
Third level Fourth level
» Fifth level
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Operating Regions Revisit transistor operating regions
CVout
0
Vin
VDD
VDD
A B
DE
Vtn VDD/2 VDD+Vtp
Region NMOS PMOS
A Cutoff Linear
B Saturation Linear
C Saturation Saturation
D Linear Saturation
E Linear Cutoff
Vout
VDD
Vin
146
CMOS voltage transfer characteristics
KR = Kn/Kp
Symmetrical design (Kp = Kn)
If Kp Kn, then the transition shifts away from VDD/2.
147
CMOS voltage transfer characteristics
148
Calculate the critical points of the resulting voltage transfer curve. For this we need the i- v relationships of QN and QP .
CMOS voltage transfer characteristics
For QN
For QP
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CMOS voltage transfer characteristics…..
CMOS inverter is usually designed to have Vtn = lVtpl = Vt and
kn’(WIL)n = k’p(WIL)p
p is 0.3 to 0.5 times n. Kn and Kp should be equal.
The width of the p-channel device is made two to three times that of the n-channel device.
The two devices are designed to have equal lengths, with widths related by (Wp / Wn) = (p / n)
This will result in k’n(W / L)n = k’p(W / L)p (KN = KP) and the inverter will have a symmetric transfer characteristic and equal current-driving capability in both directions (pull-up and pull-down).
150
CMOS voltage transfer characteristics…..
VIH — Minimum permitted logic-1or "high" level at the input.
VIL — Maximum permitted logic-0 or "low" level at the input.
Above are formally defined as the two points on the transfer curve at which the incremental gain is unity. (i.e. the slope is =1 V/ V).
151
To determine VIH : QN is in the triode region QP is in salutation (KN = KP)
CMOS voltage transfer characteristics…..
Equating iDN and iDP and assume matched devices (KN = KP)
Differentiating both sides relative to vI
Substitute vI = VIH and dvO/dvI = -1 to obtain
152
CMOS voltage transfer characteristics…..
VIL can be determined in a manner similar to that used to find VIH. Alternatively, we can use the symmetry relationship.
Hence we get,
153
The noise margins can now be determined as follows:
CMOS voltage transfer characteristics…..
The symmetry of the voltage transfer characteristic results in equal noise margins. If QN and QP are not matched, the voltage transfer characteristic will no longer be symmetric.
154
CMOS Inverter — Dynamic Operation Speed of operation of a digital system (e.g., a
computer) is determined by the propagation delay of the logic gates used to construct the system.
Inverter is the basic logic gate of any digital IC technology, the propagation delay of the inverter is a fundamental parameter in characterizing the technology.
Switching operation of the CMOS inverter should be analyzed to determine its propagation delay.
155
CMOS Inverter — Dynamic Operation……
Input – Output waveform
C = Internal capacitances of the MOSFETs QN and QP, + Capacitance of the interconnect wire between the inverter output node and the input(s) of the other logic gates the inverter is driving and the total input capacitance of these load (or fan-out) gates.
Inverter is driven by an ideal pulse
156
CMOS Inverter — Dynamic Operation……
Trajectory of the operating point as the input goes high and C discharges through QN.
Equivalent circuit during the capacitor discharge.
QN Saturation — C discharges — Current of QN remains constant until Vo = VDD - Vt (point F).
This portion of the discharge interval tPHL1
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CMOS Inverter — Dynamic Operation……
HL indicates the high-to-low output transition
Beyond point P, transistor QN operates in the triode region
Subst. for iDN and rearrange,
158
CMOS Inverter — Dynamic Operation…… To find the component of the delay time tPHL during which Vo
decreases from (VDD - Vt) to the 50% point, vo = VDDI2, we integrate both sides of above equation. Denoting this component of delay time tPHL2 we find that:
Adding tPHL1 and tPHL2 we get
For Vt 0.2VDD,Similarly analyze of the turn-off process. Expression for tPLH identical to this.(k’n( W / L)n replaced with k’p(W / L)p. Propagation delay tp = Average of tPHL and tPLH.
159
Stick DiagramStick Diagram is a simple sketch of the layout that can easily be changed/modified/redrawn with minimal effort.
Shows only active, poly, metal, contact, and n-well layers
Each layer is color coded (typically use colored pencils or pens)
Active, poly, metal traces are drawn with lines (not rectangles)
Contacts are marked with an X —Typically only need to show contacts between metal and active.
N-well are indicated by a rectangle around PMOS transistors — Typically using dashed lines
160
Sticks Diagram……
1
3
In
Out
VDD
GND
Stick diagram of inverter
Dimensionless layout entities Only topology is important Final layout generated by “compaction” program
OutIn
VDD
PMOS
NMOS
161
Stick Diagram NAND
Circuit Layer Design
Stick Diagram
Metal supply rails – blue n and p Active – green
Poly gates – red
Metal connections – supply, outputs
Contacts – black X
162
Stick Diagram NOR