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We propose a parametrized memory template for applications with parallel 'for' loops. The template's parameters reflect important trade-offs made during system design. The template is incorporated in our high level synthesis (HLS) compiler, where the template's parameters are adjusted to the application. The template fits parallel 'for' loops with no loop dependencies and sequential bodies. We found two alternative template implementations using our compiler. In the future, we will develop templates for other types of 'for' loops. These will be added to the compiler and it will identify the template that works best for the application it is compiling. Once a template is selected, the compiler will use design space exploration to select the best combination of template parameters for the targeted hardware and application.
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A parallel for loop memory templatefor a high level synthesis compiler
Euromicro Conference on Digital System Design
Lille, France02/09/2010
Craig MooreWim Meeus, Harald Devos, and Dirk Stroobandt
30/06/2010 Craig Moore, DSD 02/09/2010 2
Outline
● High Level Synthesis● Hardware Development● External Memory● Burst memory transfers● Parallel For Loops● Memory Template Overview● Small Example● Future Work● Conclusions
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High Level Synthesis (HLS)Missing Pieces
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HLS Missing Pieces
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HLS Missing Pieces
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Memory Templatesas Tools
● HDL Programmers have:● Toolkit of memory designs● Use the right tool for the job● Manually adapt their designs
● HLS Compilers should:● Have a toolkit of templates● Adapt the template to the app● Evaluate each template● Suggest the best template
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1) Read values from memory2) Process each value3) Store output in memory
Basic Steps for any Algorithm
for (int i = start; i < end; i++){ b[i] = func(a[i]);}
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Implement on Hardware
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External Memoryfor FPGAs
● A bottle neck● Sequential in nature● Number of values
returned each cycle depends on bus width.
● Each memory request requires a handshake
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Adapting to the Bottleneck
● Stream values from memory
● Pre-fetch values● Read/Write more than
one value each clock cycle
● Store values locally to mask latency
● Reduce number of requests
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Burst Transfers
● Burst of consecutive memory operations
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Read Transfer Start Address: 3
Transfer: 4
Burst Transfers
● Burst of consecutive memory operations
0
1
4
2
5
3
6
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Read Transfer Start Address: 3
Transfer: 4
Burst Transfers
● Burst of consecutive memory operations
0
1
4
2
5
3
6
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Read Transfer Start Address: 3
Transfer: 4
Burst Transfers
● Burst of consecutive memory operations
0
1
4
2
5
3
6
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Read Transfer Start Address: 3
Transfer: 4
Burst Transfers
● Burst of consecutive memory operations
0
1
4
2
5
3
6
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Read Transfer Start Address: 3
Transfer: 4
Burst Transfers
● Burst of consecutive memory operations
0
1
4
2
5
3
6
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Write Transfer Start Address: 2
Transfer: 5
Burst Transfers
● Burst of consecutive memory operations
0
1
4
2
5
3
6
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Write Transfer Start Address: 2
Transfer: 5
Burst Transfers
● Burst of consecutive memory operations
0
1
4
2
5
3
6
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Write Transfer Start Address: 2
Transfer: 5
Burst Transfers
● Burst of consecutive memory operations
0
1
4
2
5
3
6
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Write Transfer Start Address: 2
Transfer: 5
Burst Transfers
● Burst of consecutive memory operations
0
1
4
2
5
3
6
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Write Transfer Start Address: 2
Transfer: 5
Burst Transfers
● Burst of consecutive memory operations
0
1
4
2
5
3
6
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Write Transfer Start Address: 2
Transfer: 5
Burst Transfers
● Burst of consecutive memory operations
0
1
4
2
5
3
6
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Parallel for Loop
● Each iteration is run in parallel● No loop dependencies
● Loop Transformations to remove them
for i = 1 to 4{ a(i) = a(i) + 1 b(i) = a(i – 1) + a(i + 1)}
Example with Dependencies
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Template Overview
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Template Overview
Requests read bursts and controls execution of data paths, waits foroutput buffer if it is full
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Template Overview
Non-pipelined loop bodies executing in parallel.
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Manual Design
With enough values, performs write bursts.
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Manual Design
Starts and stops execution
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Manual Design
Controls access to memory, grants permission based on request (output buffer priority)
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Manual Design
Controls access to memory, grants permission based on request (output buffer priority)
Starts and stops execution With enough values, performs write bursts.
Non-pipelined loop bodies executing in parallel.
Requests read bursts and controls execution of data paths, waits foroutput buffer if it is full
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Byte-Enable Signal
● Multiple values for each memory transaction● Tells which bytes to replace and preserve
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Byte-Enable Signal
● Multiple values for each memory transaction● Tells which bytes to replace and preserve
Ignore
Enable
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Byte-Enable Signal
● Multiple values for each memory transaction● Tells which bytes to replace and preserve
Ignore
Enable
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Byte-Enable Signal
● Multiple values for each memory transaction● Tells which bytes to replace and preserve
Ignore
Enable
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Byte-Enable Signal
● Multiple values for each memory transaction● Tells which bytes to replace and preserve
Ignore
Enable
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Parametrized Template
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Parametrized Template
● Memory Bus Width = MParameters
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● Word Width = W
Parametrized Template
● Memory Bus Width = MParameters
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● Word Width = W
Parametrized Template
● Memory Bus Width = MParameters
● Max Words = A = M / W
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● Word Width = W
Parametrized Template
● Memory Bus Width = MParameters
● Max Words = A = M / W
● Input FIFOs = X = Cx * A
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● Word Width = W
Parametrized Template
● Memory Bus Width = MParameters
● Max Words = A = M / W
● Input FIFOs = X = Cx * A
● Iterations = Output FIFOs = N = C
N * X
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● Word Width = W
Parametrized Template
● Memory Bus Width = MParameters
● Max Words = A = M / W
● Input FIFOs = X = Cx * A
● Iterations = Output FIFOs = N = C
N * X
● Burst Length
● Input FIFO Length
● Iteration Length
● Output FIFO Length
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● Word Width = W
Parametrized Template
● Memory Bus Width = MParameters
● Max Words = A = M / W
● Input FIFOs = X = Cx * A
● Iterations = Output FIFOs = N = C
N * X
● Burst Length
● Input FIFO Length
● Iteration Length
● Output FIFO Length
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Example – Reading Values
Values in Memory
Values to be read
Byte enabled
Byte disabled
Values processed
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Example – Processing Values
Values in Memory
Values to be read
Byte enabled
Byte disabled
Values processed
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Example – Writing Values
Values in Memory
Values to be read
Byte enabled
Byte disabled
Values processed
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Future Work
● More templates for other parallel for loops● Pipelined loop body● Data reuse
● Compiler identifies parallel for loop● No keywords● Check for loop dependencies, and do loop
transformations if required● Compiler suggests best memory template
● Chosen based on performance estimate● Design space exploration using templates
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Conclusions
● HLS Tools don't create memory designs● Manual memory designs can take
days/weeks/months to complete● Parametrized memory template designs are
generated in seconds● Easy to perform design space exploration using
different parameter values and/or templates
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Thank You!
Questions?
[email protected]://www.elis.ugent.be/~cmoore
Wim Meeus*, Harald Devos‡, and Dirk Stroobandt**{wim.meeus, dirk.stroobandt}@elis.ugent.be, ‡[email protected]
