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© 2010 Mulberry1 Ltd, Veriest-Venture Ltd
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Mulberry 1Your One Solution house
• Mulberry 1 Est. in 2006 • Provides First-Class multi-disciplinary outsource
Solutions & Design Services.Alliances:
Mulberry?
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What is a TALL TALE?
• TALL TALE is a kind of folk tale
• Focuses typically popular beliefs, Internet rumors, or other myths.
• A tall tale is based on a real fact, heroes of tall tales are 'larger than life'.
• Tall tale heroes solve problems in funny ways that are hard to believe.
ARE you a FPGA TALL-TALE Hero?
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Are You Influenced / Exposed to Tall Tales?
• FPGA is a good candidate implementing market needs for fast response, complex and involving solutions
• Need fast infrastructure ramp up?• Have limited Budget ? • Have tight schedule?• Need to provide tested product and fast?TOO MUCH TO DO and have
LACK of RESOURCES?
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Are You Influenced / Exposed to Tall Tales?
Now you are guided by
Tall Tales.
You wish to believe they are true
YES
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Planning – Tall Tales
• FPGA does not require specific planning. “Everything is programmable, Keep 50% utilization and everything will be OK”
Real fact – may be true for simple implementations
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Planning – Expert’s opinion
• FPGA technology and capacity today (Millions of gates, 100s of MHz) is comparable to ASIC implementation complexity.
• FPGA is usually located in the system’s core and affected by many factors and professionals in the team – ASIC architecture, system design, SW, HW.
• FPGA might be at the whole project bottle neck.
• Strategic decisions are very important – Pinout, vendor, device type, capacity, speed, etc.
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Design – Tall Tales
• FPGA design is like ASIC design , any ASIC Designer can do it. just write your code as you wish and the tools will optimize and do the rest.
• “Board designer is free to choose the pinout and FPGA tools will align later to the requirements”
or• “Let the tools decide - Vendor knows the best pinout fit”
Real fact – Functional RTL design is similar, Tools decision is a good start.
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Design – Expert’s opinion
• RTL design should be FPGA FRIENDLY, especially @ high speed. (Bad Example:66 logic levels)
• FPGA design requires high BE skills and not only logic design – Physical flow, timing closure, synthesis process, tools, etc.
• Resources are still limited in comparison to ASIC.
• Deep understanding of the FPGA internal architecture is crucial while trying to optimize the design. Initial pre-placement will result better performance.
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Verification – Tall Tale
• “WE DO NOT NEED TO GET THOSE VERIFICATION ENGINEERS INVOLVED.”
• “FPGA has fast turn around, test it in the lab, no need for verification efforts”
• “FPGA verification, same as ASIC verification would consume huge resources – thus we should avoid it”
Real fact –ASIC Verification is Complex task, FPGA configuration is fast
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Verification – Expert’s opinion
• Debug time in the LAB is very costly, debug cycle involves many tools and equipments – test stations are limited.
• FPGA verification strategy fits into the project scope: – Simplified environment and fast rampup.– Coverage and test plans are aligned with targets.– Specific scenarios reproduction capabilities.
• Good test plan partitioning – what should be tested by verification team and what will be covered in the LAB.
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Summery
• Plan- Involve FPGA process as early as possible• Design – FPGA is an expertise of itself.• Verify – Use FPGA verification strategy
FPGA Flow TALL TALES are nice.EXPERTS & TOOLS are a MUST!
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Thank You!
054 - 428-4574
www.Veriest-V.com
054 - 592-7962
www.Mulberry1.com
