i

ASEMINAR REPORT

ON“AC PERFORMANCE OF NANOELECRONIC”

Submitted by

BALDEV RAM

In partial fulfilment for the award of the degree

Of

BACHELOR OF TECHNOLOGY(RAJASTHAN TECHNICAL UNIVERSITY, KOTA)

INELECTRONICS AND COMMUNICATION ENGINEERING

UNDER THE GUIDANCE OF

PROF. PIYUSH VYASAT

JODHPUR INSTITUTE OF ENGINEERING AND TECHNOLOGYMOGRA, N.H. 62, PALI ROAD,

JODHPUR-342802

MARCH 2016

ii

Candidate’s Declaration

I hereby declare that the work, which is being presented in the Seminar, entitled “Ac PerformanceOf Nanoelecronics” in partial fulfilment for the award of Degree of “Bachelor of Technology” In

department Of Electronics & Communication Engineering with specialization in Electronics &

Communication Engineering And submitted to the Department of Electronics &Communication Engineering .Jodhpur Institute of Engineering and Technology, Rajasthan

Technical University is a record of my own Work carried under the Guidance of Prof. Piyush Vyas

Department of Electronics & Communication Engineering Jodhpur institute of engineering and

technology

I have not submitted the matter presented in this Seminar anywhere for the award of any other

Degree.

NAME-BALDEV RAMEnrolment No.: 12/2ECE/076

Counter Signed byName of guide Name of incharge

PROF. PIYUSH VYAS PROF.PIYUSH VYAS

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ACKNOWLEDGEMENTFirstly I would like to express my sincere gratitude to the Almighty for His solemn presence

throughout the seminar study. I would also like to express my special thanks to my seminar

supervisor, Assistant Professor in the Department of Electronics & Communication Engineering

Prof. Piyush Vyas for providing me with valuable advice and guidance of the Department of

Electronics & Communication Engineering For their constructive support and cooperation at each

and every juncture of the seminar study.

We deeply express our sincere thanks to our Head of seminar coordinator Prof. SHWETA

BHATI for encouraging and allowing us to present the project on the topic “AC

PERFORMANCE OF NANOELECRONIC”. We would like to make a number of

Acknowledgements to those who have helped us to prepare this Seminar.

We are highly grateful to Prof. O. P. VYAS, Dean (Engineering), JIET for proving us this

opportunity to carry out independent study on this topic.

The divine support given by our guide Prof. PIYUSH VYAS and Prof. K. K. ARORA, HOD(M. Tech) & Prof. (Dr.) HEMANT PUROHIT, HOD (B. Tech) Department of Electronics and

Communication Engineering, J.I.E.T, Jodhpur, without them the work would not be possible.

BALDEV RAM

12EJIEC708

iv

ABSTRACT

Nano electronic devices fall into two classes: tunnel devices and ballistic transport devices. In Tunnel

devices single electron effects occur if the tunnel resistance is larger than h/e″ = 25 KΩ. In Ballistic

devices with cross sectional dimensions in the range of quantum mechanical wavelength of electrons,

the resistance is of order h/e″ = 25 KΩ .This high resistance may seem to restrict the operational speed

of Nano electronics in general. However the capacitance values and drain source spacing are typically

small which gives rise to very small RC times and transit times of order of ps or less. Thus the speed

may be very large, up to THz range.

The goal of this seminar is to present the models an performance predictions about the effects that

set the speed limit in carbon nanotube transistors, which form the ideal test bed for understanding the

high frequency properties of Nano electronics because they may behave as ideal ballistic 1d transistors.

v

TABLE OF FIGURE

FIGURE FIGURE NAME PAGE NO.

NO.

Chapter -1

1.1 Inversion layer mobility is controlled by impurity 8

1.2 Distribution along the channel of a MOSFET 10

1.3 Double gate MOSFET design. Of silicon body 11

Chapter -2

2.1 Single wire Nano tube 14

2.2 The honey comb structure of grapheme 15

2.3 Three possible type of CNTFET 15

Chapter -3

3.1 Geometry for impedance calculation 17

3.2 Circuit diagram for a Id nanowire or Nano tube 17

Chapter-4

4.1 Typical nanotube transistor geometry 19

4.2 Typical nanotube transistor geometry 20

Chapter-

6.1 Science engineering and Nano electronics 25

vi

TABLE OF CONTENTS

Title Page…………………………………………………………………………………………..…...i

Candidate’s Declaration……………………………………………………………………………..…ii

Acknowledgement…………………………………………………………………………………….iii

Abstract…………………………………………………………………..........................................iv

List of Figures………………………………………………………………………….........................v

Introduction _______________________________________________________________________1

Literature survey___________________________________________________________________2

CHAPTERS

1. BALLISTIC TRANSPORT- AN OUTLINE__________________________________________3

1.1 Introduction ____________________________________________________________________3

1.2 Dependence on normal electric field_________________________________________________3

1.3 Dependence on temperature________________________________________________________5

1.4 Effects of ballistic transport in MOSFET’S____________________________________________6

1.5 Achieving ballistic transport in deeply-scaled MOSFET’S________________________________7

1.6 Minimizing phonon scattering______________________________________________________8

1.7 Minimizing impurity scattering_____________________________________________________9

2. CARBON NANOTUBES – AN OVERVIEW________________________________________10

2.1 Introduction___________________________________________________________________10

2.2 Depletion mode p-CNTFET_______________________________________________________11

2.3 MOSFET like CNTFET__________________________________________________________12

2.4 Schotty barrier CNTFETS________________________________________________________12

2.5 Am bipolar behaviour___________________________________________________________12

3. NANOTUBE INTERCONNECTS: QUANTUM IMPEDANCES_______________________13

3.1 Introduction___________________________________________________________________13

3.2 Electrostatic capacitance_________________________________________________________14

3.3 Quantum capacitance____________________________________________________________14

vii

3.4 Kinetic inductance______________________________________________________________14

4. ACTIVE DEVICES AND EQUIVALENT CIRCUIT_________________________________15

4.1 Active devices: Nanotube transistors________________________________________________15

4.2 Small signal equivalent circuit_____________________________________________________16

4.2.1 Gate-source capacitance_____________________________________________________16

4.2.2 Transconductance__________________________________________________________16

4.2.3 Drain resistance____________________________________________________________16

4.2.4 Series resistance____________________________________________________________17

4.2.5 Parasitic capacitance ________________________________________________________17

5. RELEVANT FREQUENCY AND CUTOFF FREQUENCY___________________________18

5.1 Relevant frequency scales________________________________________________________18

5.1.1 RC time _________________________________________________________________18

5.1.2Trans conductance _________________________________________________________18

5.2 Cut-off frequency_______________________________________________________________19

5.2.1 Scaling with length_________________________________________________________19

6. BEYOND MICROELECTRONICS _______________________________________________20

6.1 Introduction___________________________________________________________________20

CONCLUSION__________________________________________________________________22

REFERENCES__________________________________________________________________23

APPENDIX______________________________________________________________________24

1

INTRODECTION

The phenomenological predictions for the cut off frequency of carbon nanotube transistors and

the predictions of the effects of parasitic capacitances on AC nanotube transistor performance are

presented. The influence of quantum capacitance, kinetic inductance, and ballistic transport on

the high-frequency properties of nanotube transistors is analysed. The challenges of impedance

matching for ac nano-electronics in general, and how integrated nano systems can solve this

challenge, are presented

Nano electronic devices fall into two classes: tunnel devices and ballistic transport devices. In

Tunnel devices single electron effects occur if the tunnel resistance is larger than h/e″ = 25 KΩ.

In Ballistic devices with cross sectional dimensions in the range of quantum mechanical

wavelength of electrons, the resistance is of order h/e″ = 25 KΩ .This high resistance may seem

to restrict the operational speed of nano electronics in general. However the capacitance values

and drain source spacing are typically small which gives rise to very small RC times and transit

times of order of ps or less. Thus the speed may be very large, up to THz range.

The goal of this seminar is to present the models an performance predictions about the

effects that set the speed limit in carbon nanotube transistors, which form the ideal test bed for

understanding the high frequency properties of Nano electronics because they may behave as

ideal ballistic 1d transistors.

\

2

LITERATURE SURVEY

I. we referred following paper for writing this seminar report.

1. In this paper we present phenomenological predictions for the cutoff frequency of carbon

nanotube transistors by Integrated Nano systems Research Facility, CA 92697-2625, USA

P.J. Burke / Solid-State Electronics 48 (2004) 1981–1986. We also present predictions of

the effects parasitic capacitances on AC nanotube transistor performance.

2. In this paper present kinetic inductance, and ballistic transport on the high-frequency

properties of nanotube transistors is analyzed. We discuss the challenges of impedance

matching for ac nano-electronics in general, and show how integrated Nano systems

Burke PJ. “An RF circuit model for carbon nanotubes”. IEEE Transactions on

Nanotechnology 2003:2(1):55–8.

3. Burke PJ. “Luttinger liquid theory as a model of the GHz electrical properties of carbon

nanotubes” IEEE Transactions on Nanotechnology 2002:1(3):129–44.

4. that carbon Nano-electronics may be faster than conventional Si, SiGe, GaAs, or InP

semiconductor technologies Nauman Z. Butt, “Carbon-Nanotube Transistors present by ”

McEwen PL, Fuhrer M, Park H. “Single-walled carbon nanotube electronics”. IEEE

Transactions on Nanotechnology 2002;1(1):78-85;

II We referred following content from Internet

1. Application of AC performance of Nano electronics.

2. Advantage and disadvantage of ac performance of Nano electronics.

3. Future scope of Nano electronics.

3

CHAPTER 1

BALLISTIC TRANSPORT- AN OUTLINE

1.1 INTRODECTION

When carriers travel through a semiconductor material, they are likely to be scattered by any

number of possible sources, including acoustic and optical phonons, ionized impurities, defects,

inter faces, and other carriers. If, however, the distance travelled by the carrier is smaller than the

mean free path, it is likely not to encounter any scattering events; it can, as a result, move

ballistic ally through the channel. To the first order, the existence of ballistic transport in a

MOSFET depends on the value of the characteristic scattering length (i.e. mean free path) in

relation to channel length of the transistor. This scattering length, l, can be estimated from the

measured carrier mobility

Where t is the average scattering time, m* is the carrier effective mass, and vth is the thermal

velocity.

1.2 DEPENDENCE ON NORMAL ELECTRIC FIELD

In state-of-the-art MOSFET inversion layers, carrier scattering is dominated by phonons,

impurities (Coulomb interaction), and surface roughness scattering at the Si-SiO2 interface. As

shown in Figure2, the relative importance of each scattering mechanism is dependent on the

effective electric field component normal to the conduction channel. At low fields, impurity

scattering dominates due to strong Coulomb interactions between the carriers and the impurity

canters. As the electric field is increased, acoustic phonons begin to dominate the scattering

process. At very high fields, carriers are pulled closer to the Si-SiO2 gate oxide interface; thus,

4

surface roughness scattering degrades carrier mobility. A universal mobility model has been

developed to relate field strength with the effective carrier mobility due to phonon and surface ro

Where Vgs is the applied gate voltage, VT is the transistor threshold voltage, Tox is the gate

oxide thickness, and m0 and Ecrit are empirically-derived constants. As predicted by the

International Technology Roadmap for Semiconductors, device technologies at near ballistic

(~30nm) channel lengths will have power supplies of <0.8V, VT<0.2V, Tox,eq~10Å. This yields

an effective electric field of approximately ~1MV/cm. The actual value may be lower, depending

on the actual device structure and operating conditions. With doping concentrations in the

channel region of the MOSFET expected to be on the order of 1018, from ,we find that the

electron mobility is ~230cm2/Vsec and the hole mobility is ~65 cm2/Vsec at room temperature.

This yields scattering lengths of approximately 5.5nm and 2.4nm.

Fig.1.1: Inversion layer mobility is controlled by impurity

5

1.3 DEPENDENCE ON TEMPERATURE

When the temperature is changed, the relative importance of each of the aforementioned

scattering mechanisms is altered. Phonon scattering becomes less important at very low

temperatures. Impurity scattering, on the other hand, becomes more significant because carriers

are moving slower (thermal velocity is decreased) and thus have more time to interact with

impurity canters. Surface roughness scattering remains the same because it does not depend on

temperature. At liquid nitrogen temperatures (77K) and an effective electric field of 1MV/cm, the

electron and hole mobility are~700 cm2/Vsec and ~100cm2/Vsec, respectively. Using the above

equations, the scattering lengths are approximately 17nm and 3.6nm.These scattering lengths can

be assumed to be worst-case scenarios, as large operating voltages (1V) and aggressively scaled

gate oxides (10Å) are assumed. Thus, actual scattering lengths will likely be larger than the

calculated values. Further device design considerations in maximizing this scattering length will

be discussed in the last section of this paper .Still, the values calculated above are certainly in the

range of transistor gate lengths currently being studied in advanced MOSFET research (<50nm).

Ballistic carrier transport should thus become increasingly important as transistor channel lengths

are further reduced in size. In addition, it should be noted that the mean free path of holes is

generally smaller than that of electrons. Thus, it should be expected that ballistic transport in

PMOS transistors is more difficult to achieve, since current conduction occurs through hole

transport. Calculation of the mean scattering length, however, can only be regarded as a first-

order estimation of ballistic transport. To accurately determine the extent of ballistic transport

evident in a particular transistor structure, Monte Carlo simulation methods must be employed

.Only by modelling the random trajectory of each carrier travelling through the channel can we

truly assess the extent of ballistic transport in a MOSFET. Comparison of scattering length with

the device channel length can nevertheless provide a useful way of ascertaining whether ballistic

transport effects should be considered.

6

1.4 EFFECTS OF BALLISTIC TRANSPORT IN MOSFET’SIf carrier transport in a device can be assumed to be completely ballistic, analysis of MOSFET

current voltage characteristics reduces to carrier transmission over the channel potential barrier.

As shown in figure 3, the potential energy distribution in the channel of the transistor has a

maximum,

E max , near the source end of the device. Carriers with a higher energy than E max can be

transmitted over the barrier through the process of thermionic emission. Carriers with lower

energies can travel from source to drain only by tunnelling quantum mechanically through the

channel potential barrier. Such transport phenomena is markedly different from that generally

associated with mobility-limited diffusive transport. As a result, the current-voltage

characteristics of MOSFET’s operating in the ballistic regime will be different.

Fig.1.2: Distribution along the channel of a MOSFET In ballistic transport

1.5 ACHIEVING BALLISTIC TRANSPORT IN DEEPLY-SCALED MOSFET’SAs evidenced by preceding sections, ballistic transport allows for larger transistor saturation

currents because carriers are experience no scattering. Designing future transistors to maximize

the likelihood of ballistic transport is thus highly desirable. As shown, simply by shrinking

current transistor designs, a significant step can be taken towards this goal. However,

modifications to the operating conditions or to the device structure itself may help to further

induce ballistic transport. Recently, much interest has been placed on thin body double-gate

7

MOSFET designs (Figure 1.3) due to its superior immunity to detrimental short-channel effects.

This structure, in particular, lends itself to the promotion of ballistic carrier transport due to its

low-doped channel and dual-gate nature. The following briefly describes some techniques that

may be used in the design of future transistor technologies to minimize carrier scattering, thus

promoting ballistic transport. The primary goal is to reduce the likelihood of scattering events in

the MOSFET inversion layer and increase the mean free path. Minimizing surface roughness

scattering Because of the large electric fields experienced by carriers in MOSFET inversion

layers, scattering is due predominately to interface roughness. To minimize the impact of this

scattering mechanism, the problem can be attacked from two perspectives: improving the Si-

SiO2 interface quality, and decreasing the normal electric field. The former will indeed reduce

surface roughness scattering, but there is little room for improvement as current semiconductor

process technologies are quite mature and yield very clean and smooth interfaces. Even so, it

may be helpful to take precautions during processing to ensure a good interface; this may include

ion implantation through a screen oxide, sacrificial oxidation steps to clean up surfaces after

reactive ion etching, or dry as opposed to wet oxidation techniques. Decreasing the normal

electric field is a more viable option. As mentioned earlier, the normal electric field can be

express

Fig.1.3: Double gate MOSFET design the silicon body is on the order of 10nm

8

To decrease the normal electric field, either the power supply voltage (which becomes the

applied Vgs) must be scaled down or the oxide thickness must be increased. Lowering of the

power supply is already a widespread trend, mainly due to power dissipation and device

reliability concerns. However, this results in a smaller inversion charge density and thus a smaller

current. As such, a trade off in current drive can be observed between minimization of carrier

scattering and the decrease in inversion charge. There is likely an optimum point for the choice

of supply voltage. Normally, gate oxide thickness is decreased in advanced transistor

technologies to combat short channel effects and to improve the ability to “turn off” the

transistor. However, a thicker gate oxide may allow for ballistic transport, which may decrease

the effective field, increase current, and result in an overall advantage. The double-gate MOSFET

structure (Figure 4) is particularly attractive for this option because two gate electrodes exist to

help to control channel conductivity, the gate oxide thickness need not be as thin to achieve small

gate lengths. Additionally, in the double-gate MOSFET structure, because there are two gate

electrodes on opposite sides of the conduction channel, it is reasonable to assume that the two

will have a cancelling effect on the normal electric field component in the middle of the silicon

body . This should, in turn, reduce surface roughness scattering in the inversion layer. If indeed

the normal electric field component is reduced in double-gate MOSFET’s, it may be much easier

to achieve ballistic-mode transport in these devices.

1.6 MINIMIZING PHONON SCATTERING

Phonons resulting from vibrations in the silicon lattice are principally controlled by the ambient

temperature. Decreasing the operating temperature of a transistor reduces phonon scattering and

increases the carrier transmission coefficient and thus the likelihood of ballistic transport.

Transmission coefficients as high as 92% have been obtained at liquid nitrogen temperatures

(77K).However, low temperature operation, while interesting from an academic standpoint, is not

9

attractive for practical applications as the cooling system required to achieve such temperatures is

complex and expensive.

1.7 MINIMIZING IMPURITY SCATTERING

In order to alleviate the impact of impurity scattering, the doping concentration in the channel

region needs to be low. In a standard transistor design, because of concerns with the short-

channel effect and threshold voltage control, doping concentrations in the channel need to be

very high (~1018 cm-3). In order to decouple channel doping from these issues, super-steep

retrograde doping profiles or lightly doped epitaxial channel layers need to be employed. The

double-gate MOSFET structure described in Figure 4, however, already considers the use of a

low-doped channel region. Short-channel effects are controlled using the dual-gate structure,

while threshold voltage is dictated by the work function of gate material. Thus, impurity

scattering can be minimized with this device structure. As previously mentioned, in transistors

operating near the ballistic regime, carrier scattering will likely dominated by surface roughness

mechanisms. Thus, addressing effective normal electric field as well as Si-SiO2 interface quality

will be of utmost concern in achieving ballistic transport. Furthermore, additional device design

issues will have to be resolved before the full benefits of ballistic transport are realized. Most

importantly, parasitic resistances in the source and drain terminals of the device due either to

shallow source/drain junctions or the thin body region of the double-gate device will be

10

CHAPTER 2

CARBON NANOTUBES – AN OVERVIEW

2.1 INTRODUCTION

The remarkable properties of SWNT (single wire nanotube) stems from the unusual electronic

structure of the two dimensional material graphene from which they are constructed. Graphene is

a single atomic layer of graphite which consists of a 2D honey comb structure of sp² bonded

carbon atoms.

Fig.2.1: Single wire nano tube

It is sometimes called zero band semiconductors since it is semiconducting in some directions

and metallic in the other directions. In a SWNT, the momentum of the electrons moving around

the circumference of the tube is quantized, reducing the available states to slice through the 2-D

band structure. This shown in fig 2.2

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Fig 2.2 the honey comb structure of grapheme

The CNTFET technology is at an early stage of development. The device physics is relatively

unexplored: it is not clear that how the device operates or whether devices grown with different

structures and techniques operate in the same way. Most of the times, CNTFETs are categorized

in three types as shown in the figure 2.3

Fig.2.3: Three possible type of CNTFET (a) P-channel depletion (b) P-channel enhancement

(c) Barrier transistor

2.2 DEPLETION MODE P-CNTFET

In this type, the nanotube is uniformly doped and the contacts at the two ends are ohmic. In such

a device, the on-current would be limited by the ‘source exhaustion’ Id (on) = qplvt, where pl is

the hole density per unit length.

12

2.3 MOSFET LIKE CNTFET

In this type of nanotube transistors, the conductance of channel is controlled by the gate as in a

MOSFET. This is supported by the fact that some long channel CNTFETs Obeys the MOSFET

square law theory and no am bipolar behaviour is observed in these Devices. Some recent

CNTFETs that behaves as MOSFET like devices, have demonstrated performance that is many

orders of magnitude better than current state of-the-art MOSFETs.

2.4 SCHOTTY BARRIER CNTFETS

Another possibility is that the CNTFET operates as “Schottky barrier transistors” in which

transistor action takes place primarily by varying the contact resistance rather than the channel

conductance. This is supported by the observations of am bipolar behaviour in some CNTFETs.

The observation of am bipolar operation in some CNTFETs and the transition of the tube from n-

type top-type indicate that some CNTFETs operate as unconventional Schottky barrier

transistors. In such a device, the gate modulates the transmission through a Schottky barrier and

the transistor action takes place primarily by varying the contact resistance rather than the

channel conductance. In addition, the electrode geometry is crucial for good device performance.

2.5 AMBIPOLAR BEHAVIOR

The CNTFETs measured in air are unipolar with p type characteristics, i.e. the tube conducts

holes upon applying negative gate voltages and they show no evidence of electron conduction

events very large gate voltages. The origin of this p-type character of semiconducting SWNT is

still not clearly understood. Several proposals have been made to explain this effect including

contact doping, doping introduced by cleaning or handling the nanotube in oxidizing acids, or

doping by the adsorption of atmospheric oxygen. In principle any of the above mechanism can

influence the transistor characteristics. The device is said to be am bipolar when it behaves like

n-type or p-type depending on the applied gate voltage i.e. it shows large conduction for both

positive and negative gate voltages

13

CHAPTER 3

NANOTUBE INTERCONNECTS: QUANTUM IMPEDANCES

3.1 INTRODUCTION

The first step towards understanding the high frequency electronic properties of carbon

nanotubes is to understand the passive ac impedance of a 1d quantum system. In the presence of

a ground plane below the nanotube or top gate above the nanotube, there is electrostatic

capacitance between the nano tube and the metal. Due to quantum properties of 1d systems there

are two additional components to the ac impedance: the quantum capacitance and the kinetic

inductance. Thus the equivalent circuit of a nanotube consists of 3 distributed circuit elements as

shown in fig 1and fig 3.1.

Fig.3.1 Geometry for impedance calculation

Fig.3.2 Circuit diagram for a Id nanowire or Nano tube

14

3.2 ELECTROSTATIC CAPACITANCE

The electrostatic capacitance between a wire and a ground plane as shown infig1 is given by

where the approximation holds good to within 1% for h > 2d. For a typical value if h/d, this wire

length can be approximated numerically as

3.3 QUANTUM CAPACITANCE

Because of the finite quantum energy level spacing of electrons in 1d, it costs energy to add an

electron to the system. By equating this energy cost ∆E with an effective Quantum capacitance,

one arrives at the following expression for capacitance per unit length:

Where h is the Planck’s constant and νF is the Fermi velocity. The fermi velocity for graphene

and also carbon nano tubes is usually taken as νF = 8x 10ˆ5 m/s, so that numerically,

3.4 KINETIC INDUCTANCE

Due to inertia of electrons, the instantaneous velocity lags the instantaneous electric field in time.

This means the current lags the phase, which can be described as a kinetic inductance. For1d

systems we have the following expression for the kinetic energy per unit length:

Numerically,

15

CHAPTER 4

ACTIVE DEVICES AND EQUIVALENT CIRCUIT

4.1 ACTIVE DEVICES: NANOTUBE TRANSISTORS

Atypical nanotube transistor geometry is shown below in fig4.1.

Fig.4.1: Typical nanotube transistor geometry

The fundamental physical mechanism responsible for transistor action in nanotube Transistor

action in nano tube transistors is still not completely understood. One action of the gate may be to

modulate the (Schottky barrier) contact resistance complicating the issue is the question whether

the transport is diffusive or ballistic Experiments indicate that the mean free path in semi

conducting nanotubes at room Temperature is at least 1µm, so that nano tubes shorter than 1µm

may behave as ballistic transistors.

In conclusion, we have presented phenomenological predictions for the ac performance of

nanotube transistors. Based on our calculations, we predict carbon nanotube transistors may be

faster than conventional semiconductor technologies. There are many challenges that must be

overcome to meet this goal, which can be best be achieved by integration of nano systems.

16

4.2 SMALL SIGNAL EQUIVALENT CIRCUIT

In fig 4.2, we show the predicted small signal circuit model for a nano tube transistor

Fig.4.2 Proposed small-signal circuit model for a nanotube

4.2.1 GATE SOURCE CAPACITANCE

The gate source capacitance is given by

The quantum capacitance is multiplied by 4 because of the band structure degeneracy

4.2.2 TRANSCONDUCTANCE

The Transconductance is the most critical parameter the underlying mechanism is the least

understood. Transconductance up to 20µS have been measured using aqueous gate geometry. A

Transconductance of 60µS was recently predicted by simulation.

4.2.3 DRAIN RESISTANCE

In Fig. 4, gd represents the output impedance of the device, if it does not appear as an ideal

current source. The gd values from various source for nanotube transistor are 0.03µS Tans S,

Verschueren A, Dekker C 1 µS Martel R, Schmidt T, Shea HR 0.6µS Burke P J

17

4.2.4 SERIES RESISTANCE

In most conventional transistors the series resistance consists of the metallization layer and the

ohmic contact resistance. We argue that, in nanotube transistors, the intrinsic contact resistance

will be of order the resistance quantum because of the 1d Nature of the system. At dc, the lowest

value of resistance possible for a carbon nanotube is h/4e″. This is because there are four

channels for conductance in the Landauer-Buttiker formalism, each contributing h/e″ to the

conductance. To date very little experimental work has been done to measure the ac impedance

of ballistic systems. From a theoretical point of view, Buttiker and Christen have carefully

analysed the case of a capacitive contact to a ballistic conductor (in his case a 2DEG without

scattering) in contact with one dc electrical lead through a quantum point contact. They found

that the ac impedance from gate to lead includes a real part, equal to half the resistance quantum

h/2e″. Since there are channels in parallel this a contact resistance of h/8e″.There will be an

additional imaginary contribution to the contact resistance due to kinetic inductance on the order

of a few Nh

4.2.5 PARASITIC CAPACITANCE

The parasitic capacitance is due to fringing electric fields between the electrodes for the source,

drain and gate. While these parasitic capacitance are generally small, they may comparable to the

intrinsic device capacitances and hence must be considered. In order to estimate the order of

magnitude of the parasitic capacitance, we can use known calculations for the capacitance

between two thin metal films, spaced by a distance w, as drawn in Fig. 5. For this geometry, if w

is 1µm, the capacitance is ~ 10^-16 F/lm of electrode length. For a length of 1µm, this gives rise

to ~10^-16 F. Thus, typical parasitic capacitances are of the same order of magnitude as typical

intrinsic capacitances.

18

CHAPTER 5

RELEVANT FREQUENCY AND CUTOFF FREQUENCY

5.1 RELEVANT FREQUENCY SCALES

The frequency scales for most important processes: the RC time and the Trans conductance are

estimated.

5.1.1 RC TIME

The most important effect for high frequency performance is the RC time. For Typical Nanotube

geometry of 0.1µm length, C is of order 4aF. R can be as small as6.25kΩ.Thereforethe RC

frequency is given by

This shows that the speed limit due to RC times intrinsic to a nanotube transistor very large

indeed.

5.1.2 TRANSCONDUCTANCE

The Trans conductance gm over the gate source capacitance Cgs sets another important

Frequency.

Using experimentally measured value of 10µS, this gives

The above estimates indicate that a carbon nano tube transistor could be very fast, in spite its

high impedance. For more realistic estimates of device performance a small signal equivalent

circuit is considered

19

5.2 CUTOFF FREQUENCY

The estimates of the cut off frequency fT, defined as the frequency at which the current gain falls

to unity are provided in this section. Based on fig 4, fT is given by

Here p represent parasitic, Using the experimentally measured transconductance of 10µs, a

parasitic capacitance value of 10^-16 F, and a Cgs of4 x 10^-17 F (appropriate for a 1 lm long

tube), we predict a cut off frequency of 8 GHz. For this value, the parasitic capacitance is the

most important contribution. Thus, minimizing the parasitic capacitance is of prime importance

in increasing fT for nanotube transistors.

5.2.1 SCALING WITH LENGTH

If we assume that the parasitic capacitance can be reduced to negligible Values, the equation

simplifies to

Cgs scales linearly with gate length, and was calculated above. In the ballistic limit, gm should

be independent of gate length. Using the largest measured trans conductance to date of20µs, this

gives rise to the following prediction for fT

In fig 5.1, we plot the predictions for fT vs gate length for a nano tube transistor and

Compare it to other technologies.

20

CHAPTER 6

BEYOND MICROELECTRONICS

6.1 INTRODUCTION

Nano electronics is not simply a smaller version of microelectronics; things change at the nano

scale. At the device level, silicon transistors may give way to new materials such as organic

molecules or inorganic nano wires. At the interconnect level, microelectronics uses long, fat

wires, but nano electronics seeks to use short nano wires. Finally, fundamentally new

architectures will be needed to make use of simple, locally connected structures that are

imperfect and are comprised of devices whose performance varies widely. I have argued in this

paper that 21st century silicon technology is rapidly evolving into a true nanotechnology. Critical

dimensions are already below100 nm. The materials used in these silicon devices have properties

that differ from the bulk. Nano scale silicon transistors have higher leakage, lower-drive current,

and exhibit more variability from device to device. New circuits and architectures will need to be

developed to accommodate such devices. It matters little whether the material is silicon or

something else, the same issues face any nano electronics technology. It’s likely that many of the

advances and breakthroughs at the circuits and systems levels that will be needed to make nano

electronics successful will come from the silicon design community. Given that we have a nano

electronics technology and that another 20years of exponential progress in silicon technology can

be expected (leading to terascale integration, why explore radically new technologies? One

reason, of course, is that 20 years is not a long time to develop fundamentally new technologies,

so that we need to start now, but there are other reasons. The most compelling practical reason is

that the fabrication and assembly processes and the materials, device, circuit, and system

understanding that we develop by examining radically new technologies are almost certain to be

useful in silicon nanotechnology. Developing an understanding of how to engineer devices at the

nano scale is a good reason to support nano science research. Another reason is that devices to

complement silicon technology might be discovered. For example, carbon nanotube FETs could

be exquisite single molecule detectors, and single electron device should be integrated with

MOSFETs for high density memory applications. Another possibility is molecular structures that

21

improve the performance of a CMOS platform. For example, ballistic CNTs could be high

performance interconnects and efficient at heat removal. Nano wire thermos electric cooling

could lower chip temperature and increase performance. So there are several good reasons to

expect that research on nano electronics will prove to be a good investment. The successful

development of nano electronics will require a partnership between science and engineering. It

was the same for semiconductor technology. The scientific community developed the

understanding of semiconductor materials and physics and the engineering community used this

base to learn how to design devices, circuits, and systems. Figure 5 summarizes this partnership.

Science works in the nano world with individual atoms, molecules, nano scale structures and

devices, and assembly processes. Systems engineers work in the macro world on complex

systems with tera scale device densities. In the middle are the device and circuit engineers. They

must learn to think and work at the nano scale to build devices and circuits that can connect to

the macro world. Their job is to hide the complexity of the nano scale device by packaging it in a

form that systems engineers can use (e.g. a compact circuit model). To turn the promise of nano

science into practical technologies, it is essential that the systems engineering community be

Fig.6.1: Science engineering and Nano electronics

22

CONCLUSION

In conclusion, we have presented phenomenological predictions for the ac performance of

nanotube transistors. Based on our calculations, we predict carbon nanotube transistors may be

faster than conventional semiconductor technologies. There are many challenges that must be

overcome to meet this goal, which can be best be achieved by integration of nano systems.

Modelling and predictions for nano electronics as interconnects, transistors, and antennas. It is

clear that nano-electronic devices can full fill all three roles, with outstanding predicted

performance. Then we can predict carbon nanotube transistor may be faster than conventional

semiconductor technologies. There are many challenges that must be overcome to meet this goal,

which can be best be achieved by integration of nano systems. Future work remains to be done

on understanding non-linear- nano-electronic devices for applications such as mixers and

detectors.

23

REFERENCES

Burke PJ. An RF circuit model for carbon nanotubes. IEEE Trans Nanotechnology

P.J. Burke – Carbon nano electronics technology

1. www.cientifica.com

2. Burke PJ. Luttinger liquid theory as a model of the GHz electrical properties

of carbon nanotubes. IEEE Trans Nanotechnology 2002;1(3):129–44.

3. Burke PJ. An RF circuit model for carbon nanotubes. IEEE Trans

Nanotechnology 2003; 2(1):55–8.

4. Ramo S, Whinnery JR, Van Duzer T. Fields and waves in communications

electronics. New York: Wiley; 1994.

5. Li S, Yu Z, Gadde G, Burke PJ, Tang WC. Carbon nanotube growth for GHz

devices. In: Proc 3rd IEEE Conf Nanotechnology, 2003.

6. Li S, Yu Z, Yen S-F, Tang WC, Burke PJ. Carbon nanotube transistor

operation at 2.6 GHz. Nano Lett, in press.

7. Avouris Ph, Dresselhaus MS, Dresselhaus G, editors. Carbon Nanotubes:

Synthesis, Structure, Properties, and Applications. Topics in Applied Physics,

vol. 80. Berlin, Germany: Springer; 2001.

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APPENDIX

Nano-electronic devices fall into two classes: tunnel devices, and ballistic transport devices. In

tunnel devices, single electron effects occur if the tunnel resistance is larger than h=e2 25 kX.

In ballistic devices with cross-sectional dimensions of order the quantum mechanical wavelength

of electrons, the resistance is of order h=e2 25 kX. At first glance, these high resistance values

may seem to restrict the operational speed of Nano electronics in general. However, the

capacitance for these devices is also generally small, as is the typical source–drain spacing. This

gives rise to very small RC times, and very short transit times, of order ps or less. Thus, the speed

limit may be very large, up to the THz range.