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Kinetis KM34 Sub-Family ReferenceManual
Supports: MKM34Z256VLL7 MKM34Z256VLQ7
Document Number: KM34P144M75SF0RMRev. 3, 09/2017
Kinetis KM34 Sub-Family Reference Manual, Rev. 3, 09/2017
2 NXP Semiconductors
Contents
Section number Title Page
Chapter 1About This Document
1.1 Overview.......................................................................................................................................................................45
1.1.1 Purpose.........................................................................................................................................................45
1.1.2 Audience...................................................................................................................................................... 45
1.2 Conventions.................................................................................................................................................................. 45
1.2.1 Numbering systems......................................................................................................................................45
1.2.2 Typographic notation................................................................................................................................... 46
1.2.3 Special terms................................................................................................................................................ 46
Chapter 2Introduction
2.1 KM3x_256 family introduction.................................................................................................................................... 47
2.2 Detailed block diagram................................................................................................................................................. 47
2.3 KM3x_256 feature set...................................................................................................................................................48
2.4 Device configuration.....................................................................................................................................................51
2.4.1 Supported Packages..................................................................................................................................... 52
2.5 Modules on the device.................................................................................................................................................. 53
2.5.1 Platform modules......................................................................................................................................... 53
2.5.2 System modules........................................................................................................................................... 54
2.5.3 Clock............................................................................................................................................................ 55
2.5.4 Security modules..........................................................................................................................................56
2.5.5 Analog modules........................................................................................................................................... 57
2.5.6 Timer modules............................................................................................................................................. 58
2.5.7 Communication interfaces........................................................................................................................... 59
2.5.8 Human-machine interfaces.......................................................................................................................... 61
Chapter 3Core Overview
3.1 Introduction...................................................................................................................................................................63
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3.1.1 Buses, interconnects, and interfaces............................................................................................................ 63
3.1.2 System Tick Timer.......................................................................................................................................63
3.1.3 Debug facilities............................................................................................................................................ 64
3.1.4 Core privilege levels.................................................................................................................................... 64
3.2 Nested vectored interrupt controller (NVIC) ...............................................................................................................64
3.2.1 Interrupt priority levels................................................................................................................................ 64
3.2.2 Non-maskable interrupt................................................................................................................................64
3.2.3 Interrupt Channel Assignments....................................................................................................................65
3.3 AWIC introduction....................................................................................................................................................... 67
3.3.1 Wake-up sources.......................................................................................................................................... 67
Chapter 4System Memory Map
4.1 Introduction...................................................................................................................................................................69
4.2 System Memory Map....................................................................................................................................................69
4.3 Flash Memory Map.......................................................................................................................................................70
4.4 SRAM memory map.....................................................................................................................................................70
4.5 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................71
4.6 AIPS peripheral slot assignment...................................................................................................................................72
4.7 Private peripherals........................................................................................................................................................ 75
4.8 Private Peripheral Bus (PPB) memory map..................................................................................................................76
4.8.1 GPIO accessibility in the memory map....................................................................................................... 76
Chapter 5Clock Distribution
5.1 Introduction...................................................................................................................................................................79
5.2 High-level clocking diagram.........................................................................................................................................79
5.3 Clock definitions...........................................................................................................................................................81
5.3.1 Device clock summary.................................................................................................................................82
5.4 Internal clocking requirements..................................................................................................................................... 83
5.4.1 Clock divider values after reset....................................................................................................................83
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5.4.2 VLPR mode clocking...................................................................................................................................84
5.4.3 Enable PLL in VLPR or VLPR and PSTOP1 .............................................................................................84
5.5 Clock Gating................................................................................................................................................................. 85
5.6 Module clocks...............................................................................................................................................................86
Chapter 6Reset and Boot
6.1 Reset..............................................................................................................................................................................89
6.1.1 System resets and sources............................................................................................................................ 89
6.2 Boot...............................................................................................................................................................................93
6.2.1 Boot sources.................................................................................................................................................93
6.2.2 Boot options................................................................................................................................................. 93
6.2.3 FOPT boot options....................................................................................................................................... 93
6.2.4 Boot sequence.............................................................................................................................................. 94
Chapter 7Power Management
7.1 Introduction...................................................................................................................................................................97
7.2 Power Modes................................................................................................................................................................ 97
7.3 Entering and exiting power modes............................................................................................................................... 99
7.4 Power mode transitions.................................................................................................................................................100
7.5 Power modes shutdown sequencing............................................................................................................................. 101
7.6 Module Operation in Low Power Modes......................................................................................................................101
7.7 Clocking modes............................................................................................................................................................ 104
7.7.1 Partial Stop...................................................................................................................................................104
7.7.2 DMA Wakeup.............................................................................................................................................. 105
7.7.3 Compute Operation...................................................................................................................................... 106
7.7.4 Peripheral Doze............................................................................................................................................108
7.8 Clock Gating................................................................................................................................................................. 108
Chapter 8Security
8.1 Introduction...................................................................................................................................................................109
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8.2 External Watchdog Monitor......................................................................................................................................... 109
8.2.1 EWM counter...............................................................................................................................................109
8.2.2 EWM_out signal.......................................................................................................................................... 110
8.2.3 EWM_in signal............................................................................................................................................ 110
8.3 Robust Watchdog for Improved System Reliability.....................................................................................................111
8.3.1 32-bit programmable timeout Period........................................................................................................... 111
8.3.2 Independent Clock Source........................................................................................................................... 112
8.3.3 Write Protection........................................................................................................................................... 112
8.3.4 Robust Refresh Mechanism......................................................................................................................... 114
8.3.5 Windowed Refresh.......................................................................................................................................114
8.3.6 Fast Response to Code Runaway................................................................................................................. 114
8.4 Watchdog configuration................................................................................................................................................116
8.5 iRTC Write Protect State Machine............................................................................................................................... 116
8.6 iRTC Tamper Detection Mechanism............................................................................................................................ 117
8.6.1 Internal Tamper Condition 1: Battery removed when MCU is powered OFF............................................ 117
8.6.2 Internal Tamper Condition 2: Battery removed when MCU is powered ON..............................................117
8.6.3 External Tamper Condition: Off Chip Tamper Indication...........................................................................118
8.6.4 Tamper Detection Flow............................................................................................................................... 118
Chapter 9Debug
9.1 Introduction...................................................................................................................................................................121
9.2 Debug port pin descriptions..........................................................................................................................................121
9.3 SWD status and control registers..................................................................................................................................122
9.3.1 MDM-AP Control Register..........................................................................................................................123
9.3.2 MDM-AP Status Register............................................................................................................................ 124
9.4 Debug resets..................................................................................................................................................................126
9.5 Micro Trace Buffer (MTB) ..........................................................................................................................................126
9.6 Debug in low-power modes.......................................................................................................................................... 127
9.7 Debug and security....................................................................................................................................................... 127
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Chapter 10Pinouts and Packaging
10.1 Package Types.............................................................................................................................................................. 129
10.2 Port control and interrupt module features................................................................................................................... 130
10.3 KM3x_256 Signal multiplexing and pin assignments .................................................................................................131
10.4 KM3x_256 Family Pinouts...........................................................................................................................................136
10.4.1 100-pin LQFP.............................................................................................................................................. 136
10.4.2 144-pin LQFP.............................................................................................................................................. 137
10.5 Module Signal Description Tables................................................................................................................................138
10.5.1 Core Modules...............................................................................................................................................139
10.5.2 System Modules...........................................................................................................................................139
10.5.3 Clock Modules............................................................................................................................................. 140
10.5.4 Analog..........................................................................................................................................................140
10.5.5 Timer Modules.............................................................................................................................................141
10.5.6 Communication Interfaces........................................................................................................................... 142
10.5.7 Human-Machine Interfaces (HMI).............................................................................................................. 142
Chapter 11Port Control and Interrupts (PORT)
11.1 Introduction...................................................................................................................................................................145
11.2 Overview.......................................................................................................................................................................145
11.2.1 Features........................................................................................................................................................ 145
11.2.2 Modes of operation...................................................................................................................................... 146
11.3 External signal description............................................................................................................................................147
11.4 Detailed signal description............................................................................................................................................147
11.5 Memory map and register definition.............................................................................................................................147
11.5.1 Pin Control Register n (PORTx_PCRn).......................................................................................................154
11.5.2 Global Pin Control Low Register (PORTx_GPCLR).................................................................................. 156
11.5.3 Global Pin Control High Register (PORTx_GPCHR).................................................................................157
11.5.4 Interrupt Status Flag Register (PORTx_ISFR)............................................................................................ 157
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11.5.5 Digital Filter Enable Register (PORTx_DFER)...........................................................................................158
11.5.6 Digital Filter Clock Register (PORTx_DFCR)............................................................................................159
11.5.7 Digital Filter Width Register (PORTx_DFWR).......................................................................................... 159
11.6 Functional description...................................................................................................................................................160
11.6.1 Pin control.................................................................................................................................................... 160
11.6.2 Global pin control........................................................................................................................................ 161
11.6.3 External interrupts........................................................................................................................................161
11.6.4 Digital filter..................................................................................................................................................162
Chapter 12System Integration Module (SIM)
12.1 Introduction...................................................................................................................................................................163
12.2 Features.........................................................................................................................................................................163
12.3 Memory map and register definition.............................................................................................................................164
12.3.1 System Options Register 1 (SIM_SOPT1).................................................................................................. 165
12.3.2 SOPT1 Configuration Register (SIM_SOPT1_CFG)..................................................................................166
12.3.3 System Control Register (SIM_CTRL_REG)............................................................................................. 167
12.3.4 System Device Identification Register (SIM_SDID)...................................................................................170
12.3.5 System Clock Gating Control Register 4 (SIM_SCGC4)............................................................................172
12.3.6 System Clock Gating Control Register 5 (SIM_SCGC5)............................................................................174
12.3.7 System Clock Gating Control Register 6 (SIM_SCGC6)............................................................................178
12.3.8 System Clock Gating Control Register 7 (SIM_SCGC7)............................................................................181
12.3.9 System Clock Divider Register 1 (SIM_CLKDIV1)...................................................................................182
12.3.10 Flash Configuration Register 1 (SIM_FCFG1)........................................................................................... 184
12.3.11 Flash Configuration Register 2 (SIM_FCFG2)........................................................................................... 186
12.3.12 Unique Identification Register High (SIM_UIDH)..................................................................................... 187
12.3.13 Unique Identification Register Mid-High (SIM_UIDMH)..........................................................................187
12.3.14 Unique Identification Register Mid-Low (SIM_UIDML)...........................................................................188
12.3.15 Unique Identification Register Low (SIM_UIDL)...................................................................................... 188
12.3.16 Miscellaneous Control Register (SIM_MISC_CTL)...................................................................................188
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12.3.17 ADC Compensation Register 0 (SIM_ADC_COMP0)............................................................................... 193
12.3.18 ADC Compensation Register 1 (SIM_ADC_COMP1)............................................................................... 194
12.4 Functional description...................................................................................................................................................194
Chapter 13Inter-Peripheral Crossbar Switch (XBAR)
13.1 Chip-specific XBAR information.................................................................................................................................195
13.1.1 Overview......................................................................................................................................................195
13.1.2 Instantiation Information..............................................................................................................................195
13.1.3 Peripheral Interconnects...............................................................................................................................195
13.2 Introduction...................................................................................................................................................................198
13.2.1 Overview......................................................................................................................................................198
13.2.2 Features........................................................................................................................................................ 198
13.2.3 Modes of Operation..................................................................................................................................... 198
13.2.4 Block Diagram............................................................................................................................................. 198
13.3 Signal Descriptions....................................................................................................................................................... 199
13.3.1 XBAR_OUT[0:NUM_OUT-1] - MUX Outputs......................................................................................... 200
13.3.2 XBAR_IN[0:NUM_IN-1] - MUX Inputs.................................................................................................... 200
13.3.3 DMA_REQ[n] - DMA Request Output(s)...................................................................................................200
13.3.4 DMA_ACK[n] - DMA Acknowledge Input(s)............................................................................................200
13.3.5 INT_REQ[n] - Interrupt Request Output(s).................................................................................................200
13.4 Memory Map and Register Descriptions...................................................................................................................... 200
13.4.1 Crossbar Select Register 0 (XBAR_SEL0)................................................................................................. 202
13.4.2 Crossbar Select Register 1 (XBAR_SEL1)................................................................................................. 202
13.4.3 Crossbar Select Register 2 (XBAR_SEL2)................................................................................................. 203
13.4.4 Crossbar Select Register 3 (XBAR_SEL3)................................................................................................. 203
13.4.5 Crossbar Select Register 4 (XBAR_SEL4)................................................................................................. 204
13.4.6 Crossbar Select Register 5 (XBAR_SEL5)................................................................................................. 204
13.4.7 Crossbar Select Register 6 (XBAR_SEL6)................................................................................................. 205
13.4.8 Crossbar Select Register 7 (XBAR_SEL7)................................................................................................. 205
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13.4.9 Crossbar Select Register 8 (XBAR_SEL8)................................................................................................. 206
13.4.10 Crossbar Select Register 9 (XBAR_SEL9)................................................................................................. 206
13.4.11 Crossbar Select Register 10 (XBAR_SEL10)............................................................................................. 207
13.4.12 Crossbar Select Register 11 (XBAR_SEL11)............................................................................................. 207
13.4.13 Crossbar Select Register 12 (XBAR_SEL12)............................................................................................. 208
13.4.14 Crossbar Select Register 13 (XBAR_SEL13)............................................................................................. 208
13.4.15 Crossbar Select Register 14 (XBAR_SEL14)............................................................................................. 209
13.4.16 Crossbar Select Register 15 (XBAR_SEL15)............................................................................................. 209
13.4.17 Crossbar Select Register 16 (XBAR_SEL16)............................................................................................. 210
13.4.18 Crossbar Select Register 17 (XBAR_SEL17)............................................................................................. 210
13.4.19 Crossbar Select Register 18 (XBAR_SEL18)............................................................................................. 211
13.4.20 Crossbar Select Register 19 (XBAR_SEL19)............................................................................................. 211
13.4.21 Crossbar Select Register 20 (XBAR_SEL20)............................................................................................. 212
13.4.22 Crossbar Select Register 21 (XBAR_SEL21)............................................................................................. 212
13.4.23 Crossbar Control Register 0 (XBAR_CTRL0)............................................................................................212
13.4.24 Crossbar Control Register 1 (XBAR_CTRL1)............................................................................................215
13.5 Functional Description..................................................................................................................................................217
13.5.1 General......................................................................................................................................................... 217
13.5.2 Functional Mode.......................................................................................................................................... 217
13.6 Resets............................................................................................................................................................................ 217
13.7 Clocks........................................................................................................................................................................... 218
13.8 Interrupts and DMA Requests...................................................................................................................................... 218
Chapter 14Memory Mapped Arithmetic Unit (MMAU)
14.1 Chip-specific MMAU information............................................................................................................................... 219
14.1.1 Overview......................................................................................................................................................219
14.2 Introduction...................................................................................................................................................................219
14.2.1 Features........................................................................................................................................................ 220
14.2.2 Block diagram.............................................................................................................................................. 220
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14.2.3 Modes of operation...................................................................................................................................... 222
14.3 External signal description............................................................................................................................................223
14.4 Memory map and register definition.............................................................................................................................223
14.4.1 Operand Register X0 (MMAU_X0)............................................................................................................ 224
14.4.2 Operand Register X1 (MMAU_X1)............................................................................................................ 225
14.4.3 Operand Register X2 (MMAU_X2)............................................................................................................ 225
14.4.4 Operand Register X3 (MMAU_X3)............................................................................................................ 226
14.4.5 Accumulator Register A0 (MMAU_A0)..................................................................................................... 227
14.4.6 Accumulator Register A1 (MMAU_A1)..................................................................................................... 228
14.4.7 Control/Status Register (MMAU_CSR)...................................................................................................... 229
14.4.8 CSR Interrupt Flags Clearance Register (MMAU_CSR_IF_CLR).............................................................232
14.4.9 MMAU register access in Busy State.......................................................................................................... 233
14.5 Functional description...................................................................................................................................................234
14.5.1 MMAU Programming Model...................................................................................................................... 234
14.5.2 Numeric Types in MMAU...........................................................................................................................237
14.5.3 MMAU Arithmetic Computation Description.............................................................................................240
14.5.4 MMAU Software Interface.......................................................................................................................... 248
Chapter 15System Mode Controller (SMC)
15.1 Introduction...................................................................................................................................................................251
15.2 Modes of operation....................................................................................................................................................... 251
15.3 Memory map and register descriptions.........................................................................................................................253
15.3.1 Power Mode Protection register (SMC_PMPROT).....................................................................................254
15.3.2 Power Mode Control register (SMC_PMCTRL).........................................................................................255
15.3.3 Stop Control Register (SMC_STOPCTRL).................................................................................................256
15.3.4 Power Mode Status register (SMC_PMSTAT)........................................................................................... 258
15.4 Functional description...................................................................................................................................................258
15.4.1 Power mode transitions................................................................................................................................258
15.4.2 Power mode entry/exit sequencing.............................................................................................................. 261
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15.4.3 Run modes....................................................................................................................................................263
15.4.4 Wait modes.................................................................................................................................................. 265
15.4.5 Stop modes...................................................................................................................................................266
15.4.6 Debug in low power modes......................................................................................................................... 268
Chapter 16Low-Leakage Wakeup Unit (LLWU)
16.1 Chip-specific LLWU information.................................................................................................................................271
16.1.1 Overview......................................................................................................................................................271
16.1.2 Wakeup Sources...........................................................................................................................................271
16.1.3 Reset due to LLWU wakeup event.............................................................................................................. 272
16.2 Introduction...................................................................................................................................................................273
16.2.1 Features........................................................................................................................................................ 273
16.2.2 Modes of operation...................................................................................................................................... 273
16.2.3 Block diagram.............................................................................................................................................. 274
16.3 LLWU signal descriptions............................................................................................................................................ 275
16.4 Memory map/register definition................................................................................................................................... 276
16.4.1 LLWU Pin Enable 1 register (LLWU_PE1)................................................................................................277
16.4.2 LLWU Pin Enable 2 register (LLWU_PE2)................................................................................................278
16.4.3 LLWU Pin Enable 3 register (LLWU_PE3)................................................................................................279
16.4.4 LLWU Pin Enable 4 register (LLWU_PE4)................................................................................................280
16.4.5 LLWU Pin Enable 5 register (LLWU_PE5)................................................................................................281
16.4.6 LLWU Pin Enable 6 register (LLWU_PE6)................................................................................................282
16.4.7 LLWU Pin Enable 7 register (LLWU_PE7)................................................................................................284
16.4.8 LLWU Pin Enable 8 register (LLWU_PE8)................................................................................................285
16.4.9 LLWU Module Enable register (LLWU_ME)............................................................................................ 286
16.4.10 LLWU Pin Flag 1 register (LLWU_PF1).................................................................................................... 287
16.4.11 LLWU Pin Flag 2 register (LLWU_PF2).................................................................................................... 289
16.4.12 LLWU Pin Flag 3 register (LLWU_PF3).................................................................................................... 291
16.4.13 LLWU Pin Flag 4 register (LLWU_PF4).................................................................................................... 292
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16.4.14 LLWU Module Flag 5 register (LLWU_MF5)............................................................................................294
16.4.15 LLWU Pin Filter 1 register (LLWU_FILT1).............................................................................................. 296
16.4.16 LLWU Pin Filter 2 register (LLWU_FILT2).............................................................................................. 297
16.5 Functional description...................................................................................................................................................298
16.5.1 VLLS modes................................................................................................................................................ 298
16.5.2 Initialization................................................................................................................................................. 298
Chapter 17Power Management Controller (PMC)
17.1 Introduction...................................................................................................................................................................301
17.2 Features.........................................................................................................................................................................301
17.3 Low-voltage detect (LVD) system................................................................................................................................301
17.3.1 LVD reset operation.....................................................................................................................................302
17.3.2 LVD interrupt operation...............................................................................................................................302
17.3.3 Low-voltage warning (LVW) interrupt operation....................................................................................... 302
17.4 I/O retention..................................................................................................................................................................303
17.5 Memory map and register descriptions.........................................................................................................................303
17.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)........................................................ 304
17.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)........................................................ 305
17.5.3 Regulator Status And Control register (PMC_REGSC).............................................................................. 306
Chapter 18Reset Control Module (RCM)
18.1 Introduction...................................................................................................................................................................309
18.2 Reset memory map and register descriptions............................................................................................................... 309
18.2.1 System Reset Status Register 0 (RCM_SRS0)............................................................................................ 310
18.2.2 System Reset Status Register 1 (RCM_SRS1)............................................................................................ 311
18.2.3 Reset Pin Filter Control register (RCM_RPFC).......................................................................................... 313
18.2.4 Reset Pin Filter Width register (RCM_RPFW)........................................................................................... 314
18.2.5 Sticky System Reset Status Register 0 (RCM_SSRS0)...............................................................................315
18.2.6 Sticky System Reset Status Register 1 (RCM_SSRS1)...............................................................................316
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Chapter 19Miscellaneous Control Module (MCM)
19.1 Introduction...................................................................................................................................................................319
19.1.1 Features........................................................................................................................................................ 319
19.2 Memory map/register descriptions............................................................................................................................... 319
19.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)................................................................320
19.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)............................................................ 321
19.2.3 Platform Control Register (MCM_PLACR)................................................................................................321
19.2.4 Process ID register (MCM_PID)................................................................................................................. 324
19.2.5 Compute Operation Control Register (MCM_CPO)................................................................................... 325
19.2.6 Master Attribute Configuration Register (MCM_MATCRn)......................................................................326
Chapter 20Bit Manipulation Engine (BME)
20.1 Introduction...................................................................................................................................................................329
20.1.1 Overview......................................................................................................................................................330
20.1.2 Features........................................................................................................................................................ 330
20.1.3 Modes of operation...................................................................................................................................... 331
20.2 Memory map and register definition.............................................................................................................................331
20.3 Functional description...................................................................................................................................................331
20.3.1 BME decorated stores.................................................................................................................................. 332
20.3.2 BME decorated loads................................................................................................................................... 339
20.3.3 Additional details on decorated addresses and GPIO accesses....................................................................345
20.4 Application information................................................................................................................................................346
Chapter 21Micro Trace Buffer (MTB)
21.1 Introduction...................................................................................................................................................................349
21.1.1 Overview......................................................................................................................................................349
21.1.2 Features........................................................................................................................................................ 352
21.1.3 Modes of operation...................................................................................................................................... 353
21.2 External signal description............................................................................................................................................353
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21.3 Memory map and register definition.............................................................................................................................354
21.3.1 MTB_RAM Memory Map...........................................................................................................................354
21.3.2 MTB_DWT Memory Map...........................................................................................................................367
21.3.3 System ROM Memory Map.........................................................................................................................377
Chapter 22Crossbar Switch Lite (AXBS-Lite)
22.1 Chip-specific AXBS-Lite information..........................................................................................................................383
22.1.1 Overview......................................................................................................................................................383
22.1.2 Crossbar Switch Master Assignments..........................................................................................................384
22.1.3 Crossbar Switch Slave Assignments............................................................................................................384
22.2 Introduction...................................................................................................................................................................384
22.2.1 Features........................................................................................................................................................ 384
22.3 Memory Map / Register Definition...............................................................................................................................385
22.4 Functional Description..................................................................................................................................................385
22.4.1 General operation.........................................................................................................................................385
22.4.2 Arbitration....................................................................................................................................................386
22.5 Initialization/application information........................................................................................................................... 387
Chapter 23Peripheral Bridge (AIPS-Lite)
23.1 Introduction...................................................................................................................................................................389
23.1.1 Features........................................................................................................................................................ 389
23.1.2 General operation.........................................................................................................................................389
23.2 Memory map/register definition................................................................................................................................... 390
23.2.1 Peripheral Access Control Register (AIPS_PACRn)...................................................................................390
23.2.2 Peripheral Access Control Register (AIPS_PACRn)...................................................................................393
23.3 Functional description...................................................................................................................................................396
23.3.1 Access support............................................................................................................................................. 396
Chapter 24DMA Controller Module
24.1 Introduction...................................................................................................................................................................397
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24.1.1 Overview......................................................................................................................................................397
24.1.2 Features........................................................................................................................................................ 398
24.2 DMA Transfer Overview..............................................................................................................................................399
24.3 Memory Map/Register Definition.................................................................................................................................400
24.3.1 Source Address Register (DMA_SARn)..................................................................................................... 401
24.3.2 Destination Address Register (DMA_DARn)............................................................................................. 402
24.3.3 DMA Status Register / Byte Count Register (DMA_DSR_BCRn).............................................................403
24.3.4 DMA Control Register (DMA_DCRn)........................................................................................................405
24.4 Functional Description..................................................................................................................................................410
24.4.1 Transfer requests (Cycle-Steal and Continuous modes).............................................................................. 410
24.4.2 Channel initialization and startup................................................................................................................ 411
24.4.3 Dual-Address Data Transfer Mode.............................................................................................................. 413
24.4.4 Advanced Data Transfer Controls: Auto-Alignment................................................................................... 414
24.4.5 Termination..................................................................................................................................................415
Chapter 25Direct Memory Access Multiplexer (DMAMUX)
25.1 Chip-specific DMAMUX information......................................................................................................................... 417
25.1.1 DMA Request Sources.................................................................................................................................417
25.2 Introduction...................................................................................................................................................................419
25.2.1 Overview......................................................................................................................................................419
25.2.2 Features........................................................................................................................................................ 420
25.2.3 Modes of operation...................................................................................................................................... 420
25.3 External signal description............................................................................................................................................421
25.4 Memory map/register definition................................................................................................................................... 421
25.4.1 Endianness................................................................................................................................................... 421
25.4.2 Channel Configuration register (DMAMUX_CHCFGn)............................................................................ 422
25.5 Functional description...................................................................................................................................................423
25.5.1 DMA channels with periodic triggering capability......................................................................................423
25.5.2 DMA channels with no triggering capability...............................................................................................426
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25.5.3 Always-enabled DMA sources.................................................................................................................... 426
25.6 Initialization/application information........................................................................................................................... 426
25.6.1 Reset.............................................................................................................................................................426
25.6.2 Enabling and configuring sources................................................................................................................427
Chapter 26Memory Protection Unit (MPU)
26.1 Chip-specific MPU information (Write Access Restrictions for RGD0 Registers)..................................................... 431
26.2 Introduction...................................................................................................................................................................432
26.3 Overview.......................................................................................................................................................................432
26.3.1 Block diagram.............................................................................................................................................. 432
26.3.2 Features........................................................................................................................................................ 433
26.4 Memory map/register definition................................................................................................................................... 434
26.4.1 Control/Error Status Register (MPU_CESR).............................................................................................. 436
26.4.2 Error Address Register, slave port n (MPU_EARn)....................................................................................437
26.4.3 Error Detail Register, slave port n (MPU_EDRn)....................................................................................... 438
26.4.4 Region Descriptor n, Word 0 (MPU_RGDn_WORD0).............................................................................. 439
26.4.5 Region Descriptor n, Word 1 (MPU_RGDn_WORD1).............................................................................. 439
26.4.6 Region Descriptor n, Word 2 (MPU_RGDn_WORD2).............................................................................. 440
26.4.7 Region Descriptor n, Word 3 (MPU_RGDn_WORD3).............................................................................. 443
26.4.8 Region Descriptor Alternate Access Control n (MPU_RGDAACn)...........................................................444
26.5 Functional description...................................................................................................................................................446
26.5.1 Access evaluation macro..............................................................................................................................446
26.5.2 Putting it all together and error terminations............................................................................................... 448
26.5.3 Power management...................................................................................................................................... 448
26.6 Initialization information.............................................................................................................................................. 449
26.7 Application information................................................................................................................................................449
Chapter 27Flash Memory Module (FTFA)
27.1 Introduction...................................................................................................................................................................453
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27.1.1 Features........................................................................................................................................................ 453
27.1.2 Block Diagram............................................................................................................................................. 454
27.1.3 Glossary....................................................................................................................................................... 455
27.2 External Signal Description.......................................................................................................................................... 456
27.3 Memory Map and Registers..........................................................................................................................................456
27.3.1 Flash Configuration Field Description.........................................................................................................456
27.3.2 Program Flash IFR Map...............................................................................................................................457
27.3.3 Register Descriptions................................................................................................................................... 457
27.4 Functional Description..................................................................................................................................................466
27.4.1 Flash Protection............................................................................................................................................466
27.4.2 Interrupts...................................................................................................................................................... 467
27.4.3 Flash Operation in Low-Power Modes........................................................................................................ 468
27.4.4 Functional Modes of Operation................................................................................................................... 468
27.4.5 Flash Reads and Ignored Writes.................................................................................................................. 468
27.4.6 Read While Write (RWW)...........................................................................................................................469
27.4.7 Flash Program and Erase..............................................................................................................................469
27.4.8 Flash Command Operations.........................................................................................................................469
27.4.9 Margin Read Commands............................................................................................................................. 474
27.4.10 Flash Command Description........................................................................................................................475
27.4.11 Security........................................................................................................................................................ 488
27.4.12 Reset Sequence............................................................................................................................................ 491
Chapter 28Flash Memory Controller (FMC)
28.1 Introduction...................................................................................................................................................................493
28.1.1 Overview......................................................................................................................................................493
28.1.2 Features........................................................................................................................................................ 493
28.2 Modes of operation....................................................................................................................................................... 494
28.3 External signal description............................................................................................................................................494
28.4 Memory map and register descriptions.........................................................................................................................494
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28.5 Functional description...................................................................................................................................................494
Chapter 29Watchdog Timer (WDOG)
29.1 Chip-specific WDOG information................................................................................................................................497
29.1.1 Overview......................................................................................................................................................497
29.1.2 Clock Connections....................................................................................................................................... 497
29.2 Introduction...................................................................................................................................................................498
29.3 Features.........................................................................................................................................................................498
29.4 Functional overview......................................................................................................................................................499
29.4.1 Unlocking and updating the watchdog.........................................................................................................501
29.4.2 Watchdog configuration time (WCT).......................................................................................................... 502
29.4.3 Refreshing the watchdog..............................................................................................................................503
29.4.4 Windowed mode of operation......................................................................................................................503
29.4.5 Watchdog disabled mode of operation.........................................................................................................503
29.4.6 Low-power modes of operation................................................................................................................... 503
29.4.7 Low-power and Debug modes of operation.................................................................................................504
29.5 Testing the watchdog.................................................................................................................................................... 504
29.5.1 Quick test..................................................................................................................................................... 505
29.5.2 Byte test........................................................................................................................................................505
29.6 Backup reset generator..................................................................................................................................................507
29.7 Generated resets and interrupts.....................................................................................................................................507
29.8 Memory map and register definition.............................................................................................................................508
29.8.1 Watchdog Status and Control Register High (WDOG_STCTRLH)........................................................... 509
29.8.2 Watchdog Status and Control Register Low (WDOG_STCTRLL)............................................................ 510
29.8.3 Watchdog Time-out Value Register High (WDOG_TOVALH).................................................................511
29.8.4 Watchdog Time-out Value Register Low (WDOG_TOVALL).................................................................. 511
29.8.5 Watchdog Window Register High (WDOG_WINH).................................................................................. 512
29.8.6 Watchdog Window Register Low (WDOG_WINL)................................................................................... 512
29.8.7 Watchdog Refresh register (WDOG_REFRESH)....................................................................................... 513
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29.8.8 Watchdog Unlock register (WDOG_UNLOCK).........................................................................................513
29.8.9 Watchdog Timer Output Register High (WDOG_TMROUTH)................................................................. 513
29.8.10 Watchdog Timer Output Register Low (WDOG_TMROUTL).................................................................. 514
29.8.11 Watchdog Reset Count register (WDOG_RSTCNT).................................................................................. 514
29.8.12 Watchdog Prescaler register (WDOG_PRESC).......................................................................................... 514
29.9 Watchdog operation with 8-bit access.......................................................................................................................... 515
29.9.1 General guideline......................................................................................................................................... 515
29.9.2 Refresh and unlock operations with 8-bit access......................................................................................... 515
29.10 Restrictions on watchdog operation..............................................................................................................................516
Chapter 30External Watchdog Monitor (EWM)
30.1 Chip-specific EWM information.................................................................................................................................. 519
30.1.1 Overview......................................................................................................................................................519
30.1.2 Clock Connections....................................................................................................................................... 519
30.1.3 Low Power Modes....................................................................................................................................... 519
30.2 Introduction...................................................................................................................................................................520
30.2.1 Features........................................................................................................................................................ 520
30.2.2 Modes of Operation..................................................................................................................................... 521
30.2.3 Block Diagram............................................................................................................................................. 522
30.3 EWM Signal Descriptions............................................................................................................................................ 522
30.4 Memory Map/Register Definition.................................................................................................................................523
30.4.1 Control Register (EWM_CTRL)................................................................................................................. 523
30.4.2 Service Register (EWM_SERV)..................................................................................................................524
30.4.3 Compare Low Register (EWM_CMPL)...................................................................................................... 524
30.4.4 Compare High Register (EWM_CMPH).....................................................................................................525
30.4.5 Clock Control Register (EWM_CLKCTRL)...............................................................................................526
30.4.6 Clock Prescaler Register (EWM_CLKPRESCALER)................................................................................ 526
30.5 Functional Description..................................................................................................................................................527
30.5.1 The EWM_out Signal.................................................................................................................................. 527
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30.5.2 The EWM_in Signal.................................................................................................................................... 528
30.5.3 EWM Counter.............................................................................................................................................. 528
30.5.4 EWM Compare Registers............................................................................................................................ 529
30.5.5 EWM Refresh Mechanism...........................................................................................................................529
30.5.6 EWM Interrupt.............................................................................................................................................529
30.5.7 Selecting the EWM counter clock............................................................................................................... 530
30.5.8 Counter clock prescaler................................................................................................................................530
Chapter 31Analog Front End (AFE)
31.1 Chip-specific AFE information.....................................................................................................................................531
31.1.1 Overview......................................................................................................................................................531
31.1.2 Clock Sources.............................................................................................................................................. 531
31.2 Introduction...................................................................................................................................................................533
31.3 Features.........................................................................................................................................................................533
31.4 Block Diagram..............................................................................................................................................................534
31.5 AFE Clocking............................................................................................................................................................... 535
31.6 OSR Select....................................................................................................................................................................536
31.7 Analog Gain Select....................................................................................................................................................... 536
31.8 Memory Map and Register Definition..........................................................................................................................536
31.8.1 Channel0 Configuration Register (AFE_CH0_CFR).................................................................................. 537
31.8.2 Channel1 Configuration Register (AFE_CH1_CFR).................................................................................. 540
31.8.3 Channel2 Configuration Register (AFE_CH2_CFR).................................................................................. 542
31.8.4 Channel3 Configuration Register (AFE_CH3_CFR).................................................................................. 544
31.8.5 Control Register (AFE_CR).........................................................................................................................547
31.8.6 Clock Configuration Register (AFE_CKR).................................................................................................549
31.8.7 DMA and Interrupt Register (AFE_DI).......................................................................................................550
31.8.8 Channel0 Delay Register (AFE_CH0_DR)................................................................................................. 551
31.8.9 Channel1 Delay Register (AFE_CH1_DR)................................................................................................. 551
31.8.10 Channel2 Delay Register (AFE_CH2_DR)................................................................................................. 552
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31.8.11 Channel3 Delay Register (AFE_CH3_DR)................................................................................................. 552
31.8.12 Channel0 Result Register (AFE_CH0_RR).................................................................................................553
31.8.13 Channel1 Result Register (AFE_CH1_RR).................................................................................................553
31.8.14 Channel2 Result Register (AFE_CH2_RR).................................................................................................554
31.8.15 Channel3 Result Register (AFE_CH3_RR).................................................................................................554
31.8.16 Status Register (AFE_SR)........................................................................................................................... 556
31.9 Power Modes................................................................................................................................................................ 558
31.9.1 Normal Run Mode....................................................................................................................................... 558
31.9.2 Wait Mode....................................................................................................................................................558
31.9.3 Low Power Run Mode................................................................................................................................. 558
31.9.4 STOP Mode..................................................................................................................................................558
31.10 Functional Description..................................................................................................................................................559
31.10.1 Start Up........................................................................................................................................................ 559
31.10.2 Conversion Control...................................................................................................................................... 559
31.10.3 Modes of Conversion................................................................................................................................... 563
31.10.4 Independent Control for Conversion............................................................................................................567
31.11 Decimation Filter.......................................................................................................................................................... 568
31.11.1 Sampling Phase Control...............................................................................................................................568
31.11.2 Frequency response......................................................................................................................................568
31.12 Modulator Bypass Mode...............................................................................................................................................569
Chapter 32Analog-to-Digital Converter (ADC)
32.1 Chip-specific ADC information....................................................................................................................................571
32.1.1 Overview......................................................................................................................................................571
32.1.2 Instantiation..................................................................................................................................................571
32.1.3 DMA Support on SAR ADC....................................................................................................................... 571
32.1.4 Chan
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