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Network Reduction for Crosstalk Analysis in Deep Submicron Technologies
Davide Pandini, Primo Scandolara and Carlo GuardianiAdvanced Research, SGS-THOMSON Microelectronics,
via C. Olivetti 2, 20041 Agrate Brianza, ITALY
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Abstract: A new fast and accurate methodology focrosstalk analysis of large VLSI IC interconnects is prsented. In the proposed approach a reduced order approxtion of the original interconnect network is derived by usinggeneral application of the moment matching technique. Susequently, a macromodel of the crosstalk voltage in the tidomain is obtained, and a general method for a precise evation of the crosstalk voltage peak is described. Finally, macromodel is used in order to evaluate the delay causedcrosstalk effects. The methodology described has been immented in a sign-off tool that can be effectively used to evaate crosstalk effects in signal integrity analysis of large digicircuits. Potentially hazardous circuit behavior caused crosstalk can thus be detected without running massive tconsuming circuit simulations. The effectiveness of oapproach is demonstrated by application examples.
I - INTRODUCTION
As the geometry of transistors and interconnects becomsmaller, wire resistance tends to increase. At the same ticoupling capacitance becomes a critical portion of the ochip wire capacitance. In deep submicron technologies, capacitance between wire and substrate can be regardethe fringing component of the total wire capacitancParallel running wires, on the contrary show high paralleplate capacitive coupling effects, since the distance betwwires on the same layer is smaller than the distance betwwires on different layers. For this reason, parallel-placapacitance between adjacent interconnects generacauses major on-chip crosstalk effects. Crosstalk effects among the limiting factors for high-speed digital circuperformance and can sometimes cause global circuit failuThey have been carefully described and their impact circuit performances has been thoroughly investigated[1]. In VLSI ICs one can typically count a large number ointerconnection lines (up to some thousands), across the level routing area. Many of these nets carry high-frequendigital signals at 300 MHz and more. In order to achiehigh performance, the interconnect resistance has to be ksufficiently low. Therefore, the metal layer thickness cannscale as readily as the wire width. As a consequence, amplitude of crosstalk signals coming from adjacent netends to increase and to cause hazards and unexpe
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stochastic soft errors. The problem of crosstalk reductican be effectively addressed during post-routing compactor at the optimization level, by increasing the spacinbetween potentially noisy lines as described in [2], or iterative re-assignment of wire segments to rows acolumns [3]. However, also the dynamic behavior ocrosstalk has to be taken into account in order to obtainaccurate modeling of the coupling effects. In fact, crosstnoise is a function not only of the circuit topology and of thinterconnect parasitics, but also of the frequency arelative strength of the driving signals which determine tactual analog amplitude and spectral power of the injecnoise. Knowledge of the crosstalk signal amplitude cavoid unnecessary spacing between adjacent interconnethus leading to improved routing density. However, becauof the effect of the driving signal strength and frequency, tcrosstalk voltage amplitude can be accurately determinonly by using a circuit simulator [4]. This approach iinefficient for computationally intensive applications, sucas signal integrity analysis of large digital circuits. In thpaper a new methodology to derive an accurate macromoof the crosstalk voltage is presented. The model accountsthe physical parameters and the dynamic characteristicthe interconnect network. The proposed methodologybased on extended application of the moment matchtechnique. First, a reduced order approximation of toriginal interconnect network is found. Next, a generformulation for the crosstalk voltage in the time domain obta ined. Final ly, a s imple and accurate analyt icexpression for the crosstalk voltage is derived. Thanalytical expression allows to efficiently and accurateevaluate the vo ltage bump amplitude and the delintroduced by crosstalk. The derived macromodel has bintegrated in a tool for sign-off signal integrity analysis olarge VLSI systems on chip. The paper is organizedfollows. Section II introduces the network reductiotechnique. Section III presents the crosstalk voltamacromodel and Section IV describes the methodoloused to evaluate the voltage bump and the delay causecoupling effects. In Section V an implementation of thmethodology is presented. Application examples aexperimental results on interconnect networks of industrstrength, showing the effectiveness of our approach, are
theent
in
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ing
nn ofitging-uphilesaryaanyyt iny.
emscyeut tothesionsed
reported. Finally, Section VI presents a few conclusiveremarks.
II - BACKGROUND
The moment matching based network reduction techniqueused in our methodology was originally presented by Pillageand Rohrer in [5] and has become popular with the name ofAWE (Asymptotic Waveform Evaluation). Using AWE it ispossible to f ind relatively low order approximations,consisting of a few dominant poles and their residues, to thetransfer functions of extremely complex systems. As theorder of approximation increases, the correspondingt ra n s i e n t re s p ons e o f t h e re duc e d o rd e r sy s te masymptotically approaches the actual response. Whilemaintaining an accuracy of the result within a few percent ofa circuit simulator, AWE is significantly faster and has beenapplied to many CAD problems. In particular, one of thefields where this technique has proven successful is theevaluation of large RC(L) interconnect networks [6]. VLSIIC interconnects are represented by large RC networks andcrosstalk effects are produced by coupling capacitancesbetween adjacent wires as shown in Fig. 1. The networktransfer functions can be modeled by using the Padéapproximation [7] obtained via the moment matchingtechnique [5]. A lumped, linear, time-invariant circuit, likean interconnect network, can be represented in terms of thedifferential state equation
(1)
where x is the state vector, A is the state matrix and u is
the input vector.
Fig. 1: RC network with coupling capacitances.
Expanding the network transfer function in aMacLaurin series (about s = 0) in the complex frequency
domain yields:
(2)
where the coefficients of the power series terms are moments of the network impulse response. The mom
matrices , can be evaluated recursively
as shown in [5]. By considering the state variables
vector as the network output variables, the approximtransfer functions can be obtained after computing tmoment matrices. Matrix is inverted only once, thureducing the computational cost of finding moments tosingle LU factorization and a number of forward anbackward substitutions. For matrices typical of interconnenetworks, using sparse matrix techniques, the cost of find
the LU fac to r i za t ion is where N is t hedimension of the circuit matrix. Moreover, it can be showthat for tree-like network topologies, commonly found iintegrated circuit interconnects, the computational costfinding the LU factors is linear with the size of the circumatrix [8]. An efficient algorithm based on path tracintechniques has been presented in [6]. However, by ussuitable sparse matrix algorithms, a computational speedcomparable to path tracing methods can be achieved, wat the same time preserving the generality that is necesfor circuits without a tree-like topology (i.e. circuits where large number of coupling capacitances is present and mdriving signals are active). Since AWE was originallproposed, a large amount of work has been carried ouorder to investigate the properties of this methodologTechniques have been proposed to overcome the problcaused by numerical instability and to improve accura[8],[9],[10],[11]. In order to apply the reduction techniqudescribed above, to a mult iple input, multiple outpinterconnect network with coupling effects, it is necessaryconsider that the output of the wire is affected by boits input signal and the signals driving the adjacent wirthrough the coupling capacitances. The transfer functbetween the output and the input can be expresin terms of the network moments in the following way:
(3)
x· Ax Bu+=
H s( )
H s( ) m0 m1s m2s2 …+ + +=
m0 m1 … mq …, , , ,
m0 A1–B–=
mk A1–mk 1– k 0>,=
x
A
O N1.4 1.7÷( )
i-th
i-th j-th
Hi j, s( ) m0i j,m1i j,
s m2i j,s2 … mqi j,
sq …
i, j
+ + + + +
1 …N,
=
=
the
ealstheer
heheut,
erism
tput the
ut
ngsferlk
ssed
ond.ne
where is the entry of the moment matrix .
By truncating the power series expansion in (2) after the term, AWE yields the order Padé approximation
of the actual transfer function . The Padé
approximation employs a rational approximant [7] and itsapplicability to lumped, time-invariant, linear networktransfer functions is particularly appealing since thesefunctions are rational functions and the poles obtained by thePadé approximant closely match the actual network poles.As the order of approximation is increased, more and moreaccurate approximations of the exact transfer function areexpected. Unfortunately when the Padé approximant is
generated with AWE, the accuracy of improves up to
about eight poles [11] and then the process does not improvesignificantly. However, from three to six dominant poles areusually sufficient to obtain a good approximation of theactual transfer function. In our methodology for crosstalkanalysis, a fast algorithm for network reduction, i.e. AWE, isused. However, different approaches like PVL [12], PACT[13] and PRIMA [14] can be used to obtain a lower ordermodel of the original network. Our moment matching basedapproach is general, and all the effects caused by the inputsignals driving the adjacent wires can be consideredsimultaneously. The presence of floating capacitors betweenany pairs of nets does not increase the matrix size nor itsignificantly decreases its sparsity. Thus the computationalcost of the moment matrix generation step is not appreciablyincreased. By expressing the transfer function betweenthe output and the input as in (3), it is possible toobtain the complete voltage frequency domain description atthe output of the wire
where is the Laplace transform of the input. In
this way, the crosstalk effects caused by all the networkinput signals by means of the coupling capacitances aretaken into account.
III - CROSSTALK VOLTAGE MACROMODEL
For the sake of simplicity and without any loss ofgenerality, let us consider two adjacent wires in order toderive a crosstalk voltage macromodel. Wire i, called thevictim, is the wire under observation, while wire j, theaggressor, causes crosstalk effects. For digital systems, thecells driving the interconnects can be modeled by aThevenin equivalent circuit [15]. In this way the overallnetwork is linear and the input voltage waveforms can be
represented by saturated ramps as descr ibed by following expression:
(4)
where time intervals and correspond to thrising and falling edge respectively. The victim output signin the frequency domain consists of two terms. The firterm is given by the product of the Laplace transform of tvictim input signal with the transfer function between th
output and the input, called the auto-transfefunction. The second term is given by the product of tLaplace transform of the aggressor input signal with ttransfer function between the output and the inp
when . This transfer function is the cross-transffunction. Since the overall RC(L) interconnect network linear, the effects of the and inputs on the victi
wire can be considered separately. Therefore, the ousignal in the frequency domain is expressed by means ofauto-transfer function and the cross-transfer function:
. (5)
When N coupled wires are present, the victim outpsignal in the frequency domain has the following form:
(6)
where all the crosstalk effects caused by the couplicapacitances are taken into account by the cross-tranfunctions . In the frequency domain, the crossta
voltage caused by the aggressor wire can thus be expreby means of the cross-transfer function
(7)
and by applying inverse Laplace transform to equati(7), the crosstalk signal in the time domain is obtaineAlternatively the crosstalk voltage in the time domain caalso be obtained by convolving the network impuls
mki j,i j,( )-th mk
2q-th q-th
Hqˆ s( ) H s( )
Hqˆ s( )
i-th j-th
i-th
Xi s( ) Hik s( )Uk s( )
k 1=
N
∑ i, 1 … N, ,= =
Uk s( ) k-th
vinp
t( )
0 0 t t0≤ ≤
VDDt1 t0–---------------t t0– t0 t t1≤ ≤
VDD t1 t t2≤ ≤
VDDt3 t2–---------------t3 t– t2 t t3≤ ≤
0 t t3>
=
t0 t1,( ) t2 t3,( )
i-th i-th
i-th j-th
i j≠
i-th j-th
i-th
Viout
s( ) Hii s( )Viinp
s( ) Hij s( )Vjinp
s( )+=
Viout
s( ) Hij s( )Vjinp
s( )
j 1=
N
∑=
Hij s( ) i j≠,
Vijxtalk
Hij s( )Vjinp
s( )=
is1),lyhee a
all aller200fnt
net
se
enyresece.nd thees. isalknceue.
response between output i and input j with the
aggressor input signal:
. (8)
The reduced order model network impulse responsebetween output i and input j has the following form [5]:
(9)
where is the set of dist inct dominant-pole
approximations and is the corresponding set of
residues. For every input signal there is a distinct set of polesand residues for all network nets, that can be evaluated bythe moment matching technique described in Section II. Bysubstituting equation (9) in (8) and using (4) as the inputvoltage waveform, the crosstalk voltage in the time domain
can be obtained. Since expressed by (4) is active in
three distinct time intervals, the convolution integral (8) canbe split into three different parts, which can be computedseparately. Therefore, the crosstalk voltage is expressed by:
(10)
in the time interval , by:
(11)
in the time interval , and by:
(12)
which holds in the time interval . Finally, when
, the time domain crosstalk voltage is given by:
(13)
In general, the crosstalk voltage in every time intervalaffected by the past history of the signal, as shown in (1(12) and (13). However, if the signal period is sufficientlarger than the rising and falling edge delays, then texponential terms in (11), (12) and (13) rapidly becomnegligible, and the crosstalk voltage promptly settles toconstant value after each switching event. A typical rise/ftime for a submicron CMOS library cell is in the range offew hundreds of picoseconds, which is considerably smathan a 5 nanosecond period, corresponding to a typical MHz clock frequency. Therefore, without any loss ogenerali ty, the assumption that each switching eveindependently affects the crosstalk voltage on the victim holds true, thus leading to the fol lowing simpli f iedexpressions for (11):
(14)
which holds when , and for (12):
(15)
which ho lds t rue when . F ina l ly, fo r ,
holds, since the crosstalk effects tend to elap
when the driving signals sett le. The extension of thcrosstalk macromodel to a general case, where maadjacent wires are present is straightforward and requinegligible addit ional computational cost. In fact, thmoment matching algorithm needs to be executed only onThe macromodel described by (10), (11), (12), (13), (14) a(15) can be used to evaluate the crosstalk voltage andpeak values between every pair of mutual coupled wirTherefore, the global crosstalk voltage on the victim wireobtained by means of linear superposition of the crosstvoltage between the victim and every aggressor signal, sithe assumption that the overall network is linear holds tr
hij t( )
vijxtalk
t( ) hij t τ–( )vjinp τ( ) τd
0-
t
∫=
q-th
hij t( ) rkepkt
k 1=
q
∑=
p1 … pq, ,
r1 … rq, ,
vjinp
t( )
vijxtalk
t( )VDD
t1 t0–--------------
rk
pk2
----- epk t t0–( )
1 pk–– t t0–( )( )
k 1=
q
∑=
t0 t t1≤ ≤
vijxtalk
t( )VDD
t1 t0–--------------
rk
pk2
----- epk t t0–( )
epk t t1–( )
– p– k t1 t0–( )( )
k 1=
q
∑=
t1 t t2≤ ≤
vijxtalk
t( )VDD
t1 t0–--------------
rk
pk2
----- epk t t0–( )
epk t t1–( )
– pk t1 t0–( )–( )
VDD
t3 t2–--------------
rk
pk2
----- 1 epk t t2–( )
– pk t t2–( )+( )
k 1=
q
∑
+
k 1=
q
∑=
t2 t t3≤ ≤
t t3≥
vijxtalk
t( )VDD
t1 t0–--------------
rk
pk2
----- epk t t0–( )
epk t t1–( )
– pk– t1 t0–( )( )
VDD
t3 t2–--------------
rk
pk2
----- epk t t3–( )
epk t t2–( )
– pk t2 t3–( )–( )
k 1=
q
∑
+
k 1=
q
∑=
.
vijxtalk
t( ) VDD
rkpk-----
k 1=
q
∑–≈
t t1»
vi jxtalk
t( )VDD
t3 t2–--------------
rk
pk----- 1 e
pk t t2–( )– pk t t2–( )+( )
k 1=
q
∑≈
VDD–rk
pk-----
k 1=
q
∑
t2 t1» t t3»
vijxtalk
t( ) 0≈
al
iesng
talk
heessisosees
, a
educh can
there
s:
he
ut
g
However, for crosstalk analysis the most likely situation tooccur is represented by a victim wire coupled with paralleladjacent wires on the same layer, as shown in Fig. 2, and thesum in (6) usually consists of three terms.
Fig. 2: Three coupled adjacent wires cross section.
IV - CROSSTALK EFFECTS ANALYSIS
In order to obtain a fast and accurate evaluation ofcrosstalk effects such as voltage bumping and parasiticdelay, the macromodel presented in Section III is used. Aprecise estimation of the time instants when a crosstalkvoltage bump occurs has to be obtained first. This can beachieved by finding the stationary points (maximum and/orminimum) of the crosstalk voltage, i.e. the solutions of theequation:
. (16)
Subsequently, such instants are considered in order tocompute the voltage bump by using the previously describedmacromodel. In fact, they are the initial guesses for the rootfinding algorithm and it is important that such initial guessesare close to the actual time instants where the bump occurs.The LHS of equation (16) can be obtained analytically byderiving (10), (11), (12) and (13). Solving equation (16) inthe corresponding t ime intervals is carried out withnumerical methods. In our implementation the Mulleralgorithm has been used [16]. It is worth noting that thetypical frequency range of submicron technologies cancause the interaction between the victim and the aggressorsignals to happen within short time intervals, i.e. hundredsand even tens of picoseconds. Therefore, the numericalsolution of (16) needs to be carefully driven in order to findall the t ime instants corresponding to extremely closevoltage bumps, i.e. roots of (16) belonging to a very smallinterval. Numerical root finding algorithms are known toconverge very efficiently when the initial guess is close tothe actual solution [17]. Since the crosstalk voltage bumpsoccur in proximity of the instants , , and , a suitable
initial guess for the Muller algorithm is expected to be closeto these values. In order to find a good initial guess, theTaylor power series expansion of the LHS of equation (16)
about the time instants , , and of the input sign
waveform (4) is considered. By truncating the power serexpansion about after the second order, the followi
expression for the time instant corresponding to the crossvoltage peak is obtained:
. (17)
Equation (17) represents an approximate value for tinstant when the bump occurs and is used as the initial gufor the Muller algorithm. When the network response extremely fast, the actual instant of the voltage peak is clto . Therefore, the truncation error in the power seri
expansion could yield a value smaller than . Obviously
shift forward of the crosstalk voltage bump is expectbecause of the interconnect resistive effect. Hence, in scases is used as the initial guess. The same approach
be used to generate the proper initial guesses for the otime intervals. In the second order truncation of th
power series expansion of the LHS of (16) about yield
(18)
where in order to have a more compact notation tfollowing term is defined:
.
In , by truncating the power series expansion abo
after the second order, and solving (16) the followin
expression is obtained:
(19)
where A, B and C are defined as:
Aggressor AggressorVictim
dvijxtalk
t( )
dt------------------------- 0=
t0 t1 t2 t3
t0 t1 t2 t3
t0
t̂ t0 t1,( ) max t0 t0
2 rkk 1=
q∑rkpkk 1=
q∑----------------------------–,
=
t0
t0
t0
t1 t2,( )
t1
t t1 t2,( ) max t1 t1 t1∆+,( ) ,=
t1∆
Ek Ek
k 1=
q
∑ 2
2 Ekpk
k 1=
q
∑
Ekpk------
k 1=
q
∑
–±
k 1=
q
∑–
Ekpkk 1=q∑
--------------------------------------------------------------------------------------------------------------------------------------=
Ek rk epk t1 t0–( )
1–( )≡
t2 t3,( )
t2
t̂ t2 t3,( ) max t2 t2B– B
24AC–±
2A-------------------------------------------+,
=
thegess
dhiseence
nfor
.at
ts.heionle toleow
pore
.
Finally, the solution of (16) after truncating the powerseries about at the second order is given by:
(20)
where A, B and C are defined as:
and , as:
.
By using and as initial guesses
for the Muller algorithm, convergence is always obtainedafter few iterations and the actual time instants when thecrosstalk voltage peaks occur are thus found efficiently andaccurately. Once these time instants are available, it isalways possible to obtain the amplitude of the injectedcrosstalk noise and that of the overall voltage on the victimby evaluating equations (7) and (5) respectively in the timedomain. A similar approach can be used to determine theextra delay caused by the coupling capacitances. By solvingfor the equation:
(21)
the instants when the overall output voltage on a given netreaches an user defined fraction of the asymptotic value, arefound. In our experiments this fraction has been set to
, which is a mostly common used value. The
difference between the largest root of equation (21) and instant when the input signal crosses the same voltathreshold conventionally yields the propagation delay acrothe interconnect.
V - EXPERIMENTAL RESULTS
The overall methodology for crosstalk analysis is outlinein Fig. 3. The algorithms and macromodel presented in tpaper have been implemented in a CAD tool that has bused in the crosstalk analysis of large, high-performanmicroprocessor designs, in 0.25 µm, 6 metal layer CMOStechnology. For this application, the parasitic extractioaccuracy is critical. Therefore we decided to use a tool layout parasitic extraction, i.e. ARCADIA [18], based on aquasi-3D field solver for critical layout shape extractionARCADIA generates a Detailed Standard Parasitic Form(DSPF) file containing the RC model of the interconnecSubsequently, this fi le needs to be extended with textracted coupling capacitance values. The implementatof the tool consists of two main modules. The first moducarries out the reduction of large interconnect networksmuch lower order systems, while the second moduperforms the crosstalk analysis, as it is described in the flshown in Fig. 3.
Fig. 3: Flow diagram of the methodology for crosstalk analysis.
The modular implementation of the tool allows a two-steapproach. The first step, i.e. the network reduction, is m
AVDD
t1 t0–--------------
rkpk
2---------- e
pk t2 t0–( )e
pk t2 t1–( )–( )
VDD
t3 t2–--------------
rkpk
2----------
k 1=
∑–
k 1=
∑≡
BVDD
t1 t0–-------------- rk e
pk t2 t0–( )e
pk t2 t1–( )–( )
VDD
t3 t2–-------------- rk
k 1=
q
∑–
k 1=
q
∑≡
CVDD
t1 t0–--------------
rk
pk----- e
pk t2 t0–( )e
pk t2 t1–( )–( )
q
∑≡
t3
t̂ t3 +,( ) max t3 t3B– B
24AC–±
2A-------------------------------------------+,
=
AVDD
t1 t0–--------------
Akpk
2------------
VDD
t3 t2–--------------
Bkpk
2------------
k 1=
∑+
k 1=
∑≡
BVDD
t1 t0–-------------- Ak
VDD
t3 t2–-------------- Bk
k 1=
q
∑+
k 1=
q
∑≡
CVDD
t1 t0–--------------
Ak
pk------
VDD
t3 t2–--------------
Bk
pk------
q
∑+
q
∑≡
Ak Bk
Ak rk epk t3 t0–( )
epk t3 t1–( )
–( )≡
Bk rk 1 epk t3 t2–( )
–( )≡
t̂ t0 t1,( ) t̂ t1 t2,( ) t̂ t2 t3,( ), , t̂ t3 +,( )
t
viout
t( ) αVDD=
α 0.5=
LAYOUT PARASITICEXTRACTION
NETWORK
REDUCTION
CROSSTALKMACROMODEL
DSPF
POLESRESIDUES
REPORT
INPUTSIGNALS
endselyer, arkheracyit
computationally expensive than the second step, i.e. thecrosstalk analysis. However, the network reductiontechnique based on moment matching has proven to beconsiderably faster than circuit simulations and it isexecuted only once for a given interconnect topology. Theparameters obtained after the first step, can thus be passed tothe crosstalk macromodel in order to execute an exhaustiveanalysis of noise and delay effects for every sensitizablecombination of the driving signal waveforms. The subset ofsensitizable input signals needs to be provided either by astatic/dynamic timing simulation or by circuit designers. Thecomputational cost of the second step is negligible, since themacromodel equations presented in Section III and SectionIV always yield an accurate solution after a few iterations.Both tool modules have been implemented in C++ underSolaris 2.5. The effectiveness of our approach has beenverified on a large number of test cases in an industrialenvironment. The application of the tool to the analysis ofcrosstalk effects on an interconnect network extracted fromthe layout of a test chip in 0.25 µm technology is shown.This test case is particularly significant since it has beendesigned in order to evaluate the impact of strong couplingbetween adjacent wires on the same layer. It consists of threeadjacent wires as shown in Fig. 2. Each wire is driven by abuffer that has been modeled by its Thevenin equivalentcircuit and the input signals are represented by saturatedramps as those described by (4). By changing the phaserelation between the input signal sequences, i.e. the set oftime instants of every voltage waveform, a
thorough analysis of the crosstalk effects has been carriedout. In Fig. 4, the aggressor signals represented by plotsv(in_j) and v(in_k) , pull down the victim output signalv(out_i220) after a rising transition on its input v(in_i), thusintroducing signal distortion and increasing the delaysignificantly. In Table 1 the results obtained by the circuitsimulator ELDO [19] and by our tool are compared and theerror is always within a few percents. In Fig. 5 theaggressors kick in simultaneously in opposite phase withrespect to the victim thus generating a negative voltagebump and a delay increase. The results reported in Table 2show a good agreement between our tool and the circuits imulation. Final ly, in Fig. 6 the aggressors switchsubsequently in the same direction of the victim before thetransition on the victim triggers, thus reducing the outputvoltage swing, and actually decreasing the delay. Thecorresponding numerical results are reported in Table 3. Inorder to consider aggressive worst case condit ions,extremely fast input transitions, i.e. tens of picoseconds,have been used in the examples shown. As a consequence,the accuracy of the crosstalk voltage peak evaluation isimpaired. However, when more realistic rising and fallingedges, i.e. hundreds of picoseconds, are taken into account,the error is reduced significantly. This is illustrated by the
plots in Fig. 7 and in Fig. 8 showing a crosstalk voltagbump caused by rising edges of 10 and 100 picosecorespectively. The error for the 10ps case is approximat16%, while for the 100ps case it drops below 10%. In ordto obtain better accuracy for very fast signal transitionshigher order of approximation of the reduced netwoshould be used. Since the typical clock frequency of tdesign under analysis never exceeded 500 MHz the accuof our tool was always within few percent of the circusimulation results.
t0 t1 t2 t3, , ,( )
Fig. 4: Two shifted aggressors in opposite phase wrt the victim.
.
Fig. 5: Two overlapped aggressors in opposite phase wrt the victim.
Fig. 6: Two shifted aggressors in phase wrt to the victim.
Fig. 7: Crosstalk voltage bump caused by a 10ps rising edge.
Fig. 8: .Crosstalk voltage bump caused by a 100ps rising edge.
lkgn-dothrkrse to ase
gycronenentIns,al
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ion
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,
,P.r,
-.
--
ic
VI - CONCLUSIONS AND FUTURE WORK
A new methodology for an accurate and efficient crosstaeffects analysis has been presented. A signal integrity sio f f too l for VLSI c i rcu i ts, based on the proposemethodology has been implemented. The tool achieves beff ic iency and accuracy by using a general networeduction algorithm, and a careful implementation of spamatrix techniques. We have shown how it is possibleperform an exhaustive analysis of crosstalk effects suchdelay and voltage noise, without running massive timconsuming circuit simulations. The proposed methodolohas been applied to several test cases in deep submitechnologies. A significant application example has bepresented in this paper, showing an excellent agreembetween our estimated data and full circuit simulation. this way, it is possible to identify critical signal interactionand potential design bugs that a simple timing or functionverification will not detect. This results in a substantialcompetitive advantage by reducing the time spent for timiand signal integrity verification, which is currently a largfraction of the total design time. Future work includes thextension of the methodology in order to take into accouthe effects of driver and load non-linearity and eventuallyfur ther improve the accuracy of the ana lys is. Thdevelopment of an automatic methodology for the detectof worst case signal sequences is also an ongoing effort.
VII - REFERENCES
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TABLE 1: CROSSTALK VOLTAGE BUMP AMPLITUDES AND DELAY (ELDO VS. MACROMODEL)
Two shifted aggressors in opposite phase wrt the victim
Voltage bump Delay
ELDO 100.190 ns 100.390 ns 0.446 ns
1.305 V 1.409 V
Macromodel 100.182 ns 100.389 ns 0.445 ns
1.312 V 1.480 V
Error
percent
0.007 0.001 0.27
0.5 5
TABLE 2: CROSSTALK VOLTAGE BUMP AMPLITUDES AND DELAY (ELDO VS. MACROMODEL)
Two overlapped aggressors in opposite phase wrt the victim
Voltage bump Delay
ELDO 100.056 ns 0.3040 ns
-0.3190 V
Macromodel 100.049 ns 0.3185 ns
-0.2894 V
Error
percent
0.006 4.8
9.3
TABLE 3: CROSSTALK VOLTAGE BUMP AMPLITUDES AND DELAY (ELDO VS. MACROMODEL)
Two shifted aggressors in phase wrt the victim
Voltage bump Delay
ELDO 99.670 ns 99.870 ns 0.0419 ns
0.8200 V 1.2700 V
Macromodel 99.711 ns 99.890 ns 0.0480 ns
0.7242 V 1.1726 V
Error
percent
0.04 0.02 14.5
11.7 7.7
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