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1
A Low-Offset Latched Comparator Using Zero-Static Power Dynamic
Offset Cancellation Technique
Masaya Miyahara and Akira Matsuzawa
Tokyo Institute of Technology, Japan
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Outline
• Motivation• Design Concept • Proposed Comparator• Measurement Results• Conclusions
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MotivationComparator performance is important in comparator based ADCs.
Comparator offset ⇒Low linearity, Low SNDR
-VFS
+VFSVin
2N N bit
Comparators
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Influence of the offset voltageENOB is deteriorated by the offset voltage.
1bit down @Voff(σ) = 1/2 LSB
( )⎥⎥
⎦
⎤
⎢⎢
⎣
⎡
⎟⎟⎠
⎞⎜⎜⎝
⎛+−=
2
q
off2
σ121log21ENOB
VVN
N : Resolution [bit]Voff(σ) : Offset voltage @ 1sigmaVq : 1 LSB ideal voltage
Vq=15.6 mV @ 1Vp-pVoff (σ) < 3.9 mV (ENOB > 5.6 bit)
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Conventional Offset Cancellation• Using pre-amplifiers with offset cancellation
techniques– High voltage gain, wide bandwidth amplifier is needed– Consume static power
• Digital calibration techniques [2]– Dynamic circuit, no static power– Accuracy is limited by the resolution of calibration DAC– Calibration is executed before operation
We propose the zero static power dynamic offset cancellation technique.
[2] G. Van der Plas, et al., ISSCC 2006.
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Outline
• Motivation• Design Concept • Proposed Comparator• Measurement Results• Conclusions
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Double-tail Latched Comparator
M.Miyahara, A-SSCC 2008.
Vout
out
d
L
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Offset voltage contributionEach stage’s contribution to the offset voltage obtained from Monte-Carlo simulation.
0
4
8
12
16
20
24
0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0Input common mode voltage
V cm_i [V]
Inpu
t ref
erre
d of
fset
vol
tage
Vof
f (σ
) [m
V]
1st stage2nd stageAll
• 90nm CMOS process• W/L = 1 µm / 0.1 µm • VDD = 1.0 V• fc= 500 MHz
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Offset voltage contributionEach stage’s contribution to the offset voltage obtained from Monte-Carlo simulation.
0
4
8
12
16
20
24
0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0Input common mode voltage
V cm_i [V]
Inpu
t ref
erre
d of
fset
vol
tage
Vof
f (σ
) [m
V]
1st stage2nd stageAll
• Mismatch of the 1st stage transistors becomes dominant
•The most of the offset voltage of the 1st stage is input transistor’s threshold voltages (VT)
• Input common mode voltage (overdrive voltage of the input transistors) should be kept low
1.35 mV
8.7 mV
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Design Concept
• The VT mismatch of the input transistors must be canceled.
• The overdrive voltage of the input transistors should be decided without being affected by the input common mode voltage.
• An offset cancellation circuit must be realized without static current for low power operation.
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Outline
• Motivation• Design Concept • Proposed Comparator• Measurement Results• Conclusions
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Proposed Comparator
Vin-Vin+
Vb
CC- CC+
1L
R
VDD
R
L
Di- Di+
M1' M2'
M3' M4'
MbM5'
MR1 MR2
Vcm_i Vcm_i
M6 M7 M9
M10 M11M13
M14 M15
Vout-Vout+
VDD VDD
2nd stage
M12
M8
1 1
2 2
1st stage
Vct+ Vct-
Vcb
• The 1st stage is modified to cancel the mismatch voltage.
Cc+, Cc- : Offset canceling capacitorVb : Bias voltage to set the overdrive voltage of M1' and M2'MR1, MR2 : Switches to reset Cc+ and Cc-
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Proposed Comparator Behavior
1.2
0.6
0.01.2
0.6
0.01.2
0.6
0.0
0.0
0.25
0.5
2.0n 3.0nTime [s]
4.0n 5.0n 6.0n[V
][V
][V
][V
]
L R
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Di+
Di-
Vct+
Vct-
Voff
Vin-Vin+
Vb
CC- CC+
1L
R
VDD
R
L
Di- Di+
M1' M2'
M3' M4'
MbM5'
MR1 MR2
Vcm_i Vcm_i
M6 M7 M9
M10 M11M13
M14 M15
Vout-Vout+
VDD VDD
2nd stage
M12
M8
1 1
2 2
1st stage
Vct+ Vct-
Vcb
bth2cm_icbc
bth1cm_icbc
VVVVVVVVVV
−−≈−
−−≈−
−
+
binod2
binod1
VVVVVV+∆−=
+∆=
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Simulation Results : Vcm_i Variation Proposed comparator can suppress increase of offset voltage caused by Vcm_i variation.
0
2
4
6
8
10
12
14
0.4 0.5 0.6 0.7 0.8 0.9 1.0V cm_i [V]
Vof
f (σ
) [m
V]
ProposedConventional
• 90nm CMOS process• VDD = 1.0 V• Vb = 0.1 V• fc= 500 MHz
• All transistor channel length is minimized.• Each transistor channel width is optimized for fast latching.
2.6 mV
10.7 mV
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Simulation Results : Vb Variation
0
2
4
6
8
10
12
14
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0.0 0.2 0.4 0.6 0.8 1.0
V b [V]
Vof
f (σ
) [m
V] • 90nm CMOS process• VDD = 1.0 V• Vcm_i = 0.6 V• fc= 500 MHz
The bias voltage Vb had better to be set low.However, too much small overdrive voltage causes a deterioration of the latch speed.
2.3 mV
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Outline
• Motivation• Design Concept • Proposed Comparator• Measurement Results• Conclusions
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LayoutA prototype comparator has been realized in a 90 nm 9M1P CMOS technology with a chip area of 0.0354mm2.The core comparator size is only 152 µm2.
27 µm
5.6 µm
64 comparators with SR Latch
Input switches
Output selector & decoupling capacitor
Ground line & decoupling capacitor
27 µm
361 µm
98 µ
m
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Measurement System
VoutRamp wave,Fin = 1MHz
CLK Vb
Vcm
Vout The offset voltage is the input voltage at the point that output changes from low to high.
Vin-
Voffset
Vin+
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Measurement Results: Vb Variation
0
2
4
6
8
10
12
0.0 0.2 0.4 0.6 0.8 1.0
V b [V]
Vof
f (σ
) [m
V]
3.8 mV
• VDD = 1.2 V• Vcm_i = 0.6 V• fc= 500 MHz
The offset voltage can be minimized in case of Vb= 0.15 V.
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Measurement Results: Vcm_i Variation
0
2
4
6
8
10
12
14
0.4 0.5 0.6 0.7 0.8 0.9 1.0V cm_i [V]
Vof
f () [
mV] Proposed (Sim)
Conventional (Sim)Measurement
The offset voltage increases by only 0.4 mV when Vcm_i changes from 0.6 V to 0.9 V.
• The measured offset voltage is slightly higher than simulation result.=> Dummy metals affect to mismatch
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Performance Summary
Technology 90nm, 1poly, 9metals CMOSActive Area 5.6µm x 27µm (core comparator)Voffset(σ) 3.8 mV (ENOB = 5.6 bit @ 1Vp-p)Supply Voltage 1.2 VPower consumption 4.8mW @ 500 MHz *
* Power consumption includes 64 comparators, I/O buffers and clock drivers.Simulated power consumption of the comparator is 68 µW/GHz.
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Outline
• Motivation• Design Concept • Proposed Comparator• Measurement Results• Conclusions
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Conclusion
A low offset voltage dynamic latched comparator using a zero-static power dynamic offset cancellation technique is proposed.
☺Features• The proposed comparator consumes no static power.• Measured results show the input offset voltage is improved from 12.8 mV to 3.8 mV by using proposed technique.• The offset voltage of the comparator does not change by increasing the input common mode voltage.
