Chap11 Operational Amplifiers

7/27/2019 Chap11 Operational Amplifiers

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Jaeger/Blalock 01/03/04

Microelectronic Circuit DesignMcGraw-Hill

Chapter Goals

• Understand behavior and characteristics of ideal differential and

operational amplifiers (op amps)

• Study non-ideal op-amp behavior

• Demonstrate circuit analysis techniques for ideal and non-ideal

op amps

• Characterize inverting, non-inverting, summing and

instrumentation amplifiers, voltage follower and integrator

• Learns factors involved in circuit design using op amps

• Understand frequency response limitations of op-amp circuits

• Find characteristics of cascaded amplifiers such as gain, input

resistance, output resistance and frequency response

Chap 11-2





Differential Amplifier Model: Basic

Represented by:

A = open-circuit voltage gain

vid = (v+-v-) = differential input signal

voltage

Rid = amplifier input resistance

Ro = amplifier output resistance

Signal developed at amplifier output is in

phase with the voltage applied at the + input(non-inverting) terminal and 180o out of phase

with that applied at the - input (inverting)

terminal.

Chap 11-3





Differential Amplifier Model: With

Source and Load R L = load resistance

RS = Thévenin equivalent resistance

of signal source

v s = Thévenin equivalent voltage of

signal source

vO Avid

R L

Ro R

L

and vid

vS

Rid

Rid

RS

•Op amp circuits are mostly dc-coupled amplifiers. Signals vo and v s may have

a dc component representing a dc shift of the input away from Q-point.

•Op-amp circuits amplify both dc and ac components

Av

vO

vS

Rid

Rid

RS

R L

Ro R

L

Chap 11-4





Differential Amplifier Model: With

Source and Load (Example)• Problem: Calculate voltage gain

• Given Data: A = 100, Rid = 100k W, Ro = 100W, RS = 10k W, R L = 1000W

• Analysis:

• Ideal amplifier’s output depends only on input voltage difference and noton source and load resistances.This can be achieved by using fullymismatched resistance condition ( Rid >> RS or infinite Rid and Ro << R L

or zero Ro ).

A = open-loop gain (maximum voltage gain available from the device)

Av

vo

v s

Rid

Rid

RS

R L

Ro R

L

100 100k W10k W100k W

1000W100W1000W

82.6 38.3 dB

vO

Avid

or Av

vO

vid

A

Chap 11-5





Ideal Operational Amplifier

• The ideal op amp is a special case of an ideal differential amplifier withinfinite gain, infinite Rid and zero Ro .

– If A is infinite, vid

is zero for any finite output voltage.

– Infinite input resistance Rid forces input currents i+ and i- to be zero.

• The ideal op amp has the following assumptions:

– Infinite common-mode rejection, power supply rejection, open-loop bandwidth, output voltage range, output current capability and slewrate

– Zero output resistance, input-bias currents and offset current, input-offset voltage.

vid vO

Aand lim

A vid = 0

Chap 11-6





Inverting Amplifier Configuration

• Positive input is grounded.• Feedback network consisting of resistors R1 and R2 is connected

between the inverting input, the signal source and the amplifier output

Chap 11-7







Inverting Amplifier: Input and Output

Resistances

Rout is found by applying a test current

(or voltage) source to the amplifier

output and determining the resulting

voltage (or current). All independent

sources must be turned off. Hence, vs = 0

vx i2 R2 i1 R1

But i1= i2

vx i1( R2 R1)

Since v- = 0, i1= 0 and vx = 0

irrespective of the value of ix .

0out

R

Chap 11-9







Non-inverting Amplifier: Configuration

• Input signal is applied to the non-inverting input terminal.• A portion of the output signal is fed back to the negative input terminal.

• Analysis is done by relating voltage at v1 to input voltage v s and output

voltage vo .

Chap 11-11





Non-inverting Amplifier:Voltage Gain,

Input Resistance and Output Resistance

But vid = 0

Since i+= 0

Since i- 0 : v1 vO

R1

R1 R2

and vS vid v1

vS v1

vO vS

R1 R2

R1

Av vO

vS

R1 R2

R1

1R2

R1

Rin

vS

i Rout is found by applying a test current source to amplifier output and

setting vs = 0. The resulting circuit is identical to that used for the output

resistance calculation for the inverting amplifier. Therefore Rout = 0.

Chap 11-12





Non-inverting Amplifier: Example

• Problem:Determine the characteristics of given non-inverting

amplifier

• Given Data: R1 = 3 k W, R2 = 43 k W, v s= +0.1 V

• Assumptions: Ideal op amp

• Analysis:

Since i-= 0,

Av 1R2

R1

143k W3k W

vO AvvS (15.3)(0.1V) 1.53 V

iO vO

R2 R1

1.53V

43k W 3k W 33.3 A

Chap 11-13





Unity-gain Buffer

• A special case of the non-inverting amplifier; also called avoltage

follower with infinite R1 and zero R2. Hence Av =1.

• Provides excellent impedance-level transformation while maintaining

signal voltage level.• Ideal voltage buffer does not require any input current and can drive

any desired load resistance without loss of signal voltage.

• Unity-gain buffer is used in may sensor and data acquisition systems.

Chap 11-14





Summing Amplifier

• Scale factors for the 2 inputscan be independently adjusted by proper choice of R2 and R1.

• Any number of inputs can beconnected to the summing

junction through additional

resistors.• This circuit is also an example

of a simple digital-to-analogconverter.

Since negative amplifier input is

at virtual ground,

Since i-= 0, i3 = i1 + i2 ,

Chap 11-15

i1 v1

R1

i2 v2

R2

i3 vO

R3

vO R3

R1

v1 R3

R2

v2





Difference Amplifier

• Also called a differentialsubtractor, the circuit amplifiesthe difference between the inputsignals.

• Rin2 is series combination of R1 and R2 because i+ is zero.

• For v2 = 0, Rin1= R1 , as the circuitreduces to an inverting amplifier .

• For general case, i1 is a functionof both v1 and v2.

vo v

-i

2 R

2 v

-i

1 R

2

vo v-

R2

R1(v1v-)

R1 R

2

R1

v-

R2

R1

v1

Also, v

R

2

R1 R

2

v2

Since v- v

, vo

R2

R1

(v1v

2)

For R2 R

1, v

o(v

1v

2)

Chap 11-16





Difference Amplifier: Example

• Problem: Determine V o, V +, V -, I o, I 1, I 2, I 3 .

• Given Data: R1 = 10 k W, R2 = 100 k W, V 1 = 5 V, V 2 = 3 V

• Assumptions: Ideal op amp - hence, V -= V + and I -= I += 0.

• Analysis: Using dc values,

V V - R2

R1 R

2

V 2

100k W10k W100k W

3V 2.73 V

I 1 I

2

V 1V

-

R1

5V -2.73V

10k W227 A

V O

V 1 I

1 R

1 I

2 R

25V (227 A)(110k W)20.0 V

I O

I 2227 A

Chap 11-17





Instrumentation Amplifier

Combines 2 non-inverting amplifiers

with the difference amplifier to

provide higher gain and higher input

resistance.

vO

R

4

R3

(vav

b)

vaiR

2i(2 R

1)iR

2 v

b

But, i

v1v

2

2 R1

vO

R

4

R3

1R

2

R1

(v

1v

2)

Input resistance is infinite because

input current to both op amps is zero.

Output resistance is set to zero by the

difference amplifier.

Wk 15

Chap 11-18





Instrumentation Amplifier: Example

• Problem:Determine V O, V A, V B.

• Given Data: R1 = 15 k W, R2 = 150 k W, R3 = 15 k W, R4 = 30 k W,

V 1 = 2.5 V, V 2 = 2.25 V

• Assumptions: Ideal op amp. Hence, V - = V + and I - = I + = 0.

• Analysis:Using dc values,

V O

R

4

R3

1R

2

R1

(V

1V

2) 30k W

15k W1150k W

15k W

(2.52.25)5.50V

I V

1V

2

2 R1

2.5V -2.25V

2(15k W)

8.33 A

V A

V 1 IR

22.5(8.33 A)(150k W)3.75 V

V B

V 2 IR

2 2.25(8.33 A)(150k W)1.00 V

Chap 11-19





Active Low-Pass Filter

A generalized inverting amplifier’s gain is

Av( s)

Vo( s)

Vs( s)

Z

2(s)

Z 1(s)

In a single-pole low-pass filter,

Z 1( s) R

1 Z

2( s)

R2

1 sC

R2

1

sC

R

2

sC R2

1

Av( s)

R2

R1

1

(1 sC R2)

R2

R1

1

(1 s

H

)

H

2 f H

1 R

2C

Chap 11-20





Active Low-Pass Filter (cont.)

• Single pole at H

• At frequencies below H

amplifier is an inverting

amplifier with gain set by ratio

of resistors R2 and R1.

• At frequencies above H , the

amplifier response rolls of at

-20dB/decade.

• Cutoff frequency and gain can be independently set.

Chap 11-21





Active Low-pass Filter: Example

• Problem: Design an active low-pass filter

• Given Data: Av = 40 dB, Rin = 5 k W, f H = 2 kHz

• Assumptions: Ideal op amp, specified gain represents low-frequency

gain.

• Analysis:

Input resistance is controlled by R1 and voltage gain is set by R2 / R1.

Closest capacitor value of 160 pF lowers cutoff frequency to 1.95 kHz.

Another choice of 150 pF raises cutoff frequency to 2.08 kHZ.

Av 1040dB /20dB 100

R1 R

in5 k W and A

v

R2

R1

R2

100 R1 500 k W

C 12 f

H R

2 1

2 (200kHz )(510k W)156 pF

Chap 11-22





Inverting Integrator

• Feedback resistor R2 in the inverting

amplifier is replaced by capacitor C.

• The circuit uses frequency-dependentfeedback.

iS

v

S

R i

C C

dvO

dt

Voltage at the circuit’s output at

time t is given by the initial

capacitor voltage integral of the

input signal from start of integration interval, here, t = 0.

Integration of an input step signal

results in a ramp at the output.

Chap 11-23

Since iC iS ,

dvO

1

RC v

S d

vOt

1

RC vS

0

t

d vO

0

vO

0 V C

0





Differentiator

• Input resistor R1 in the inverting

amplifier is replaced by capacitor C.

• Derivative operation emphasizes high-frequency components of input signal,

hence it is less often used than the

integrator.

i R

v

O

R i

S C

dvS

dt

Since i R iS , vO RC dv

S

dt

Output is scaled version of the

derivative of the input voltage.

Chap 11-24





Cascaded Amplifiers

• Connecting several amplifiers in cascade can meet design specifications not

met by a single amplifier (output of one stage connected to input of next).

• Each amplifier is built by using an op amp with parameters A, Rid , Ro, called

the open-loop parameters that describe the op amp with no external elements.

• Av , Rin , Rout are closed-loop parameters that describe both the closed-loop op

amp with the feedback network as well as the overall composite (cascaded)

amplifier.

Chap 11-25





Two-port Model for 3-stage Cascade

Amplifier

• Each amplifier in the 3-stage cascaded amplifier is replaced by its 2-portmodel.

vo A

vAv

s

RinB

RoutA

RinB

A

vB

RinC

RoutB

RinC

A

vC

Av

vo

v s

AvA AvB AvC If Rout = 0

Rin= RinA and Rout = RoutC = 0

Chap 11-26





Non-ideal Operational Amplifier

• Various error terms arise in practical operational amplifiers due to non-

ideal behavior.

• Some of the non-ideal characteristics include:

– Finite open-loop gain that results in gain error – Non zero output resistance

– Finite input resistance

– Finite CMRR

– Common-mode input resistance

– DC offst voltage and input currents

– Output voltage and current limits

Chap 11-27





Finite Open-loop Gain

v1

R1

R1 R2

vo

vo

R

1

R1 R

2

is called the

feedback factor.

vo Av

id A(v s v

1) A(v

s vo)

Av

v

o

v s

A

1 A

A is called the loop gain.

For A >>1,

Aideal

1

1

R2

R1

vid

v s

v1 v

s v

o

vid v s A 1 A

v s v s

1 A

Although no longer zero , vid is

small for large A .

Chap 11-28





Gain Error

• Gain Error is given by

GE = (ideal gain) - (actual gain)

For non-inverting amplifier,

• Gain error is also expressed as a fractional or percentage

error.

GE 1

A1 A

1 (1 A )

FGE

1

A

1 A 1

1

1 A 1

A

Chap 11-29





Gain Error: Example

• Problem: Find ideal, actual gain and gain error in percent

• Given data: Closed-loop gain of 200 (46 dB); open-loop gain of op

amp is 10,000 (80 dB).

• Approach: Amplifier is designed to give ideal gain and deviations

from ideal case are determined. Hence,

R1 and R2 are not noramlly designed to compensate for finite open-loop

gain of amplifier.

• Analysis:

200

1

Av A

1 A 104

1104

200

196 FGE 200196200

0.02 or 2

Chap 11-30



Jaeger/Blalock 01/03/04 Microelectronic Circuit DesignMcGraw-Hill

Non-zero Output Resistance

Output terminal is driven by test source v x and

current i x is calculated to determine output

resistance (all independent sources are turned

off). The equivalent circuit is same for both

inverting and non-inverting amplifiers.

Rout

v

x

i x

Chap 11-31






Open-loop Gain Design: Example

• Problem: Design non-inverting amplifier and find open-loop gain

• Given Data: Av = 35 dB, Rout = 0.2 W, Ro = 250 W

• Analysis:

Av

1035dB /20dB 56.2 and 1

Av

1

56.2

Rout

R

o

1 A 0.2W

A

1

Ro

Rout

1

56.2

250

0.2 1

7.0310

4

96.9 dB

Chap 11-33




Finite Input Resistance: Non-inverting

Amplifier

Test voltage source v x

is applied to

input and current i x is calculated.

i x

v

xv

1

Rid

Assuming i-<<i2 implies i1 = i2.

v1i

1 R

1i2 R

1

v1

R1

R1 R

2

vo v

o

v1 ( Av

id ) A (v

xv

1)

v1 A

1 A v x

i x

v x

A

1 A v x

Rid

v x

(1 A ) Rid

Rin

Rid

(1 A )

Chap 11-34




Finite Input Resistance: Inverting

Amplifier

Rin

v x

i x

i x R

1v

-

i x

R1 v

-

i x

R1 removed

i1 i-i

2 v

1

Rid

v1v

o

R2

v1

Rid

v1 Av

1

R2

G1 i

1v

1

1

Rid

1 A R

2

Rin

R1 R

id

R2

1 A

R

1 R2

1 A

For large A, Rin= R1

Chap 11-35




Finite Common-Mode Rejection Ratio

(CMRR)

A (or Adm)= differential-mode gain

Acm = common-mode gain

vid = differential-mode input voltage

vic = common-mode input voltage

A real amplifier responds to the signal

common to both inputs, called the

common-mode input voltage. In

general,

vo A v

id

Acm

vic

A

A v

id

vic

CMRR

CMRR A A

cm

Ideal amplifier has Acm = 0, but for a real

amplifier,

v1 vic

vid

2 v2 vic

vid

2

vo A(v

1v

2) A

cmv1 v2

2

vo A(v

id ) A

cm(v

ic)

Chap 11-36

Actual sign of CMRR isn’t known before hand

as only a lower bound is given.




Finite Common-Mode Rejection Ratio:

Example

• Problem: Find error introduced by finite CMRR.

• Given Data: A = 2500, CMRR = 80 dB, v1 = 5.001 V, v2 = 4.999 V

• Assumptions: Op amp is ideal except for finite gain and CMRR. Here,CMRR of 80 dB corresponds to CMRR of ±104. Assume CMRR = + 104.

• Analysis:

Error introduced by common-mode input is 25% of differential input voltage.

Also,

vid

5.001V 4.999V 0.002 V

vic

5.001V 4.999V 2

5.000 V

vo A v

id v

ic

CMRR

2500 0.002 5.000

104

V 6.25 V

whereas desired output is vo Av

id 5.00 V

Acm

A

CMRR 2500

100000.25 or 12 dB

Chap 11-37




Voltage Follower Gain Error

due to CMRR

vid

v s

vo v

ic

v s

vo

2

vo

A v s

vo

v s

vo

2CMRR

Av

vo

v s

A1 1

2CMRR

1 A1 1

2CMRR

Ideal gain for the voltage follower

is unity. The gain error is

GE1 Av

1 A

CMRR

1 A1 1

2CMRR

Since, both A and CMRR are

normally >>1,

GE 1

A

1

CMRR First term is due to finite amplifier

gain; second term shows that CMRR

may introduce an even larger error.

Chap 11-38






DC Error Sources

Input-Offset Voltage

With inputs being zero, theamplifier output actually

rests at some non-zero dc

voltage level. The equivalent

dc input offset voltage is

The amplifier is connected as

a voltage-follower to give an

output voltage equal to the

offset voltage.

V OS

V O A

vO

A vid

v

ic

CMRR V

OS

To include effect of offset voltage,

If vid = 0,

Thus, CMRR is a measure of how

total offset voltage changes from

its dc value when common-mode

voltage is applied.

vO

Av

ic

CMRRV

OS

A(v

OS )

CMRR vic

vOS

Chap 11-40




DC Error Sources

Input-Offset Voltage (Example)

Problem: Find quiescent dc voltage

at output.

Given data: R1 = 1.2 k W, R2 = 99k W,

Assumptions: Ideal op amp except

for non-zero offset voltage.

V OS

3mV

Output voltage is given by

Actual sign of V OS is unknown as

only upper bound is given. Note: Offset voltage of most IC op

amps can be manually adjusted by

adding a potentiometer as shown.

V OS

1 99k W1.2k W

(0.003) 0.25 V

Chap 11-41




DC Error Sources

Power Supply Rejection Ratio (PSRR)

• Power supply voltages change due to long-term drift or noise on

supplies.

• Equivalent input offset voltage changes in response to power supply

voltage changes.

• PSRR measures the ability of amplifier to reject power supply

variations.

• PSRR indicates how offset voltage changes in response to change in

power supply voltages.

• Generally PSRR values for v+ and v- are different.

• Both CMRR and PSRR both degrade rapidly with frequency increase.

PSRR vv

OS

(usually expressed in dB

PSRR v-v

OS (usually expressed in dB

Chap 11-42




DC Error Sources

Input-Bias and Offset Currents

I OS

I B1

I B2

Bias currents I B1 and I B2 ( base

currents in BJTs or gate currents in

MOSFETs or JFETs) are similar in

value with directions depending on

internal amplifier circuit type.

In inverting amplifier shown, I B1 is

shorted out by ground connection.

Since, inverting input is at virtual

ground, amplifier output is forced to

supply I B2 through R2 .Sign of offset current is unknown

as only upper bound is given.

V O

I B2

R2

Chap 11-43



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Microelectronic Circuit Design

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DC Error Sources: Input-Bias and Offset

Currents - Bias Current Compensation

Bias current compensation

resistor R B is used in series with

non-inverting input. Output due

to I B1 alone is

V O

I B1

R B

1R

2

R1

By superposition,

if .

Since, offset current is typically 5-10

times smaller than the individual biascurrents, dc output voltage error can be

reduced by using bias compensation.

V O

I B2

R2 I

B1 R

B1

R2

R1

V O

( I B2

I B1

) R2

I OS

R2

R B

R

1 R

2

R1 R

2

Chap 11-44



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01/03/04


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DC Error Sources: Input-Bias and Offset

Currents - Errors in Integrator

At t < 0, reset switch is closed,

circuit becomes a voltage-follower,

V O

V OS

At t = 0, reset switch is opened, and

circuit starts integrating its own offset

voltage and bias current. Using

superposition analysis,

Output becomes ramp with slope

determined by V OS and I B2, and it

eventually saturates at one of the power supplies.

vO(t )V

OS V OS

RC t I B2

C t

Chap 11-45



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01/03/04


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Output Voltage and Current Limits

Practical op amps have limitedoutput voltage and current ranges.

Voltage: Limited to several volts

less than power supply span.

Current: Limited by internalcircuitry (to limit power

dissipation or protect against

accidental short circuits).

Current limit specified as

minimum load resistance that theamplifier can drive with a given

voltage swing. e. g.:

iO

10V

5k W2 mA

For inverting amplifier,

iO

i L

i F

v

O

R L

v

O

R2

R1

v

O

R EQ

R EQ

R L

( R1

R2

)

R EQ

R L

R2

Chap 11-46



Jaeger/Blalock

01/03/04


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Output Voltage and Current Limits:

Example

• Problem: Design inverting

amplifier with given

specifications.

• Given Data: Av = 20 dB,

Magnitude of output

current less than 2.5 mA.

R L

5 k W, vO

10 V

• Assumptions: Ideal op amp except for

limited output current.

• Analysis:

We choose R1 = 10 k Wand R2 = 100 k W,

providing an input resistance of 10 k W.

Maximum output current will be:

R EQ

R L

R2

10V

2.5mA 4 k W

iO

10V

100k W10V

5k W2.1 mA2.5 mA

Chap 11-47

Since R L 5k W, R2 20k WFor Av 20dB, R2 10 R1





Jaeger/Blalock

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Frequency Response of Op Amps:

General Case (Example)

• Problem: Find transfer function describing frequency-

dependent amplifier voltage

gain.

AO

1080dB/20dB 104

B

103rad / s

Av( s ) A

O

B

s B

107

s103

Frequency values are often

expressed in Hz.

f B

B

2

159 Hz

f T

T

2 1.59 MHz

Chap 11-49





Jaeger/Blalock

01/03/04


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Non-inverting Amplifier (Example)

• Problem: Characterize frequency response of a non inverting amplifier.

• Given data: Ao = 105 = 100 dB, f T = 107 Hz, desired Av = 1000 = 60 dB

• Assumptions: Amplifier is described by a single-pole transfer function.

• Analysis:

f B

f T

AO

107 Hz

105 100 Hz

f H

f B

(1 AO )100(1105103)10.1 kHz

1 A

v(0)

11000

103

Av( s)

AO

B

s B 105(2 )(102) s(2 )(102)

2 107

s200

Av( s) A

O

B

s B

(1 AO )

2 107

s2.02 104

Op amp transfer

function

Non-inverting amplifier

transfer function

Chap 11-51



Jaeger/Blalock

01/03/04


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Inverting Amplifier

Av( s )

R2

R1

A( s) 1 A( s)

Av( s )

R2

R1

AO

B

s B

1A

O

B

s B

R

2

R1

AO

1 AO

s

(1 AO )

B

1

For Ao >>1,

Av( s )

R

2

R1

AO

1 AO s

H

1

R

2

R1

s

H

1

H

T

AO

1 AO

T

Chap 11-52



Jaeger/Blalock

01/03/04


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Inverting Amplifier (Example)

• Problem: Characterize frequency response of inverting amplifier.

• Given data: Ao = 2x105, f T = 5x105 Hz, desired Av = -100 or 40 dB

• Assumptions: Amplifier is described by single-pole transfer function.

• Analysis:

f B f

T

AO

510

5

Hz 2105 2.5 Hz

f H

f B

(1 AO ) 2.5 Hz (1 2105

101) 4.95 kHz

Av( s) A

O

B

s B

T

s B 5105(2 )

s(2 )(2.5)

106

s5

Av( s)

R2

R1

AO

B

s B(1 A

O )

9.90105

s9.91103

Op amp transfer

function

Inverting amplifier

transfer function

11 A

v(0)

1101

Chap 11-53



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01/03/04


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Frequency Response of Cascaded

Amplifiers

Av( s) V

oN ( s)

V s( s)

V o1

V s

V o2

V o1

...V

oN

V o( N -1)

Av( s) A

v1( s) A

v2( s)... A

vN ( s)

Assume that stages do not interact,

Av( s) Av1(0)

1 s

H 1

Av2(0)

1 s

H 2

... AvN (0)

1 s

HN

Av(0) A

v1(0) A

v2(0)... A

vN (0)

Bandwidth of the cascade

amplifier is the frequency at

which gain is reduced by -3

dB from its low frequencyvalue.

Av( j

H )

Av1

(0) Av2

(0)... AvN

(0)

2

For identical stages,

Av( j

H )

Av1

(0)

N

2

H

H 1

21/ N 1

Chap 11-54

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Frequency Response of Cascaded

Amplifiers: Example

• Problem: Calculate gain and bandwidth of a 2-stage

amplifier with

• Approach: Av = Av1 Av2

Find Av( 0 ), apply definition of

bandwidth to find f H .

• Analysis:

Av1

500

1 s

2000

Av2

250

1 s

4000

Av( s) 125,0001 s

2000

1 s

4000

Av(0)(500)(250)125,000 or 102 dB

Av( j ) 1.25105

1 2

200021 2

40002

H is defined by

A( j H

) A

mid

2

Av(0)

21.25105

2

1 2

20002

1 2

40002

2 f H

267 Hz

Bandwidth of the cascaded amplifier is

less than that of the individual stages.

Chap 11-55

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Large Signal Limitations

Slew Rate and Full-Power Bandwidth

• Slew rate: Maximum rate of change of voltage at output of op amp. Typicalvalues range from 0.1V/s to 10V/s.

• For given frequency, slew rate limitsmaximum signal amplitude that can beamplified without distortion.

vO

V M

sin t

dvO

dt max

V M

cos t max

V M

For no signal distortion,

Full-power bandwidth is highest

frequency at which a full-scale

signal can be developed.

V M SR

V M

SR

f M

SR

2 V FS

Chap 11-56

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Operational Amplifier Macro Model for

Frequency Response

• Macro Models are simplified circuit representations that model terminal behavior of op amps and attempt to include all non-ideal limitations of op amps - A large number of parameters can be adjusted to model op amp behavior.

• To model single-pole roll-off, an auxiliary “dummy” loop (voltage-controlled voltagesource v1 in series with R and C ) is added to original 2-port.

• RC product chosen to give desired -3dB point for open loop amplifier.

Av( s) v

o( s)

v1( s)

A

O

B

s B

for B

1 RC

Chap 11-57



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End of Chapter 11

Ch 11 58

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Chap11 Operational Amplifiers