CHATELAIN CharlyOral Presentation

ForB2 Level

Presentation OutlineThe development of LEON1, LEON2 &

LEON3LEON3 and GRLIB overviewFault Injection

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What is LEON ?LEON is a 32-bit SPARC processor, implemented

as a synthesisable VHDL model.LEON was primarily developed for critical space

applications, funded by the European Space Agency (ESA)

The LEON VHDL model was released in open-source to improve test coverage and adoption of SPARC ISA

Three processor versions have so far been developed: LEON1, LEON2 and LEON3.

Today, the LEON3 processor is part of a larger IP core library called GRLIB, making up a versatile SOC platform for both FPGA and ASIC.

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LEON1 DemonstratorFirst LEON design

5-stage pipeline2 x 4 Kbyte cachesMeiko FPUCustom on-chip busPROM/SRAM

control.Full FT logic30 mm2, 100

Kgates50 MHz, 0.5 W

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LEON2 – first flight part LEON1FT 5-stage pipeline with HW MUL/DIV Multi-way caches with LRU On-chip AMBA bus for modularity 32-bit PC133 SDRAM controller with EDAC 32-bit full PCI interface with DMA On-chip debug support unit (DSU) Maintained FT logic Targeted for 100 MHz on 0.18 um processes 120% performance improvement over LEON1

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LEON2 block diagram and layout

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GRLIBLEON2 was designed for a single function

(processor), but was increasingly being used as SOC platform. A more efficient

SOC platform was needed to minimize design work.

Design goals for GRLIB IP libraryPortabilityCAD tool independenceCoherent IP interfacesUniform method for HW & SW debugRich functionality Processor with MP support

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GRLIB Open-Source CoresLEON3 32-bit SPARC V8 ProcessorAMBA AHB Controller/Arbiter & AHB/APB BridgePROM, SRAM, SDRAM, DDR controllers10/100 Mbit Ethernet MAC32-bit PCI Bridge with optional DMA and FIFOCAN-2.0 with FIFOUART, Timers, Interrupt controller, GPIO,

CLK/RST gen.JTAG/TAP controllersSVGA frame bufferIDE interface for disks and CF

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GRLIB Commercial CoresFully pipelined IEEE-754 FPU (singe/double)Low-area single-issue IEEE-754 FPU (singe/double)AHB/AHB bridge with prefetch and FIFOUSB-2.0 device controller with DMA1G Ethernet MAC with UDP/TCP off-loadingFault-Tolerant LEON3FT for Military and Space app.Memory controllers with ECC (BCH & Reed-

Solomon)MIL-STD-1553 BC/RT/BM interfaces with DMASpace wire 200 Mbit/s serial link with DMAOnly commercially available (free netlists for

evaluation)

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LEON3/GRLIB

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LEON3 SPARC V8 Processor7-stage pipeline, multi-processor supportSeparate multi-way caches with LRU/LRR/RNDHighly configurable:

Way size 1-256 Kbyte, 1-4 ways, LRU/LRR/RandomHardware MUL/DIV/MAC options, FPU, MMU, Co-Proc.Pipeline optimization for specific target technologies

On-chip debug support unit with trace buffer250/400 MHz on 0.18/0.13 um, 250/400 MIPS, 25

Kgates125 MHz on Virtex2pro FPGA, 3500 LUTFault-tolerance by design for space applications

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What is Fault Injection ?The technique of fault injection dates back to the 1970s When it was first used to induce faults at a hardware level This type of fault injection is called Hardware

Implemented Fault Injection (HWIFI) and attempts to simulate hardware failures within a system.

The first experiments in hardware fault injection involved nothing more than shorting connections on circuit boards and observing the effect on the system (bridging faults).

It was used primarily as a test of the dependability of the hardware system.

Later specialised hardware was developed to extend this technique, such as devices to bombard specific areas of a circuit board with heavy radiation.

It was soon found that faults could be induced by software techniques and that aspects of this technique could be useful for assessing software systems

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What is SER ?Soft error rate (SER) is the rate at which a

device or system encounters or is predicted to encounter soft errors.

It is typically expressed as either number of failures-in-time (FIT), or mean-time-between-failures (MTBF).

The unit adopted for quantifying failures in time is called FIT, equivalent to 1 error per billion hours of device operation.

MTBF is usually given in years of device operation.

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What is SET ?A Single Event Transient (SET) occurs when

an ionizing particle hits a sensitive knot of combinatory logic

A SET does not always procreate an error.

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What is SEU ?A Single Event Upset (SEU) occurs when an

ionizing particle hits a sensitive knot of a cell memory and entrained the swing of the memorized logical value

Elements sensitive to SEU are all elements volatile memories of a system:Flip-flopsLatches registersRAM (SRAM, DRAM).

Two main types of faults :stuck-at faults asynchronous bit-flips

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LEON1FT Radiation test boardRadiation test

boardDual LEON1FT in

master/checker m.

SEU proof with FT

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LEON2FT Radiation test board

Atmel LEON2-FT, AT697 ASIC Compact PCI Board

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LEON3FT Radiation test board

LEON3-FT-RTAX

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ConclusionFault injection allows to make out a will

simulating circuit of disabled entries or stressful environment.

They can so change circuit to make it more robust in stressful environment.

The processor LEON FT are very practical to make this.

Other processor exists on the market : UltraSPARC T1 Processor of Sun Microsystems

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Thank you very much for you attention

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