Upload
vudat
View
222
Download
0
Embed Size (px)
Citation preview
Compact Modeling and Simulation of PD-SOI MOSFETs:Current Status and Challenges
Jung-Suk Goo1, Richard Q. Williams2, Glenn O. Workman3, Qiang Chen4, Sungjae Lee2, and Edward J. Nowak2
1Technology Development Group, Advanced Micro Devices Inc.2SOI Compact Modeling Group, IBM Corporation3CMOS Next Generation Design Foundations, Freescale Semiconductor Inc.4Was with AMD Inc., now with Synopsys Inc.
| IEEE SSC Society Fort Collins Chapter | Nov 10, 20082
Outline
Overview of the PD-SOI CMOS Technology
Self-heating
Model Parameter Calibration Flow
Challenges in Measurement and Calibration
Floating-Body Effects Modeling: History-Effect
Body-Contacted Device Modeling
Floating-Body Effects Simulation Issues
Model Standardization
Conclusion
| IEEE SSC Society Fort Collins Chapter | Nov 10, 20083
History of Manufacturing PD-SOI
Successfully manufactured in ULSI from the 225 nm through the 45 nm nodes
1999 ISSCC by D. H. Allen et al. 2008 VLSI Symp. by P. Klim et al.
0.2um 64b PowerPC µProcessor 45 nm 2GHz eDRAM
Inverter +15%
2-input NAND +20%
4-input NAND +28%
2-input NOR +21%
4-input NOR +26%
XOR +40%
Domino AND +15%
Domino MUX +25%
SRAM +20%
0%(bulk) 20% 40%
PD-SOI Performance Improvement
compared to bulk
| IEEE SSC Society Fort Collins Chapter | Nov 10, 20084
Benefits of PD-SOI CMOS
Higher performance and lower powerDynamic threshold (Vt) loweringReduced capacitive loadingReduced body effects in stack transistor circuits
Better controlReduced Vt versus Lgate sensitivityElimination of well-implant proximity effects (WPE)Natural isolation of auxiliary device elements (embedded DRAM, passives, high-voltage, and RF devices)
Better reliabilityReduced soft-error ratesElimination of latch-up
| IEEE SSC Society Fort Collins Chapter | Nov 10, 20085
Bulk CMOS vs. PD-SOI CMOS
The chief difference of the PD-SOI is that the body of each SOI transistor is an independent 4th terminal for the deviceWhen absolutely needed, the body can be fixed to a chosen potential with a body tie
However, in 99.9% of the chip, transistors will be operating as floating body devices
Bulk CMOS
Identical body potential
PD-SOI CMOS
Floating Body
Transistor
Transistorwith body tie
Floating Body
Transistor
Transistorwith body tie
Independent body potential
| IEEE SSC Society Fort Collins Chapter | Nov 10, 20086
Self-Heating: DC Rth Measurement
Device Turned Off Device Turned On
-50 0 50 100 150300
400
500
600
RG
ate [Ω
]
Chuck Temperature [oC]0 1 2 3 4
400
500
600
700
RG
ate [Ω
]
Device Power [mW]
Ith=PowerRthCth
TD
T0
dPowerdR
dRdT
dPowerdTR Gate
Gateth ×==
+ VR -
IR
+ VR -
IR
Gate
Source
Drain
| IEEE SSC Society Fort Collins Chapter | Nov 10, 20087
Self-Heating Removal
Channel Current Parasitic Current
0.0 0.2 0.4 0.6 0.8 1.0 1.20.0
0.5
1.0
1.5
2.0
2.5
3.0
Dra
in C
urre
nt [m
A]
Drain Voltage [V]
As Measured Self-Heating Removed
0.0 -0.5 -1.0 -1.50.0
1.0
2.0
3.0
4.0
Bod
y C
urre
nt [n
A]
Gate Voltage [V]
As Measured Self-Heating Removed
Based on measured temperature dependence of the currentLinearQuadraticExponential
| IEEE SSC Society Fort Collins Chapter | Nov 10, 20088
Self-Heating during Simulation
Addition of temperature node leads to simulation time increase, and, possibly, convergence issueCan disable self-heating mode for many high-performance logic products
Switching time is much faster than the thermal time constantMost analog blocks are operating at low enough bias range
| IEEE SSC Society Fort Collins Chapter | Nov 10, 20089
PD-SOI Model Parameter Calibration
Body Effect & CV Fitting
First -pass BC IV Fitting
DC Body Currents Fitting(Idiode , Igb, Iii, IGIDL )
Check CircuitResponse
Recenter Model
BodyContacted
Fitting
FloatingBody
Fitting
First -pass FB IV Fitting
Refine Calibration
Done
method 1 method 2
Self-HeatingRemoval from IV
Self-HeatingRth, Cth fitting
| IEEE SSC Society Fort Collins Chapter | Nov 10, 200810
Do History-Effect Modeling First!
Intrinsic MOSFET characteristics have only small impact on history effect
Except for the body-effectAdjusting parasitic characteristics have huge impact on history effect and cause noticeable change in channel current
Intrinsic MOSFETCharacteristicsIDsat, Ioff, Vt, …
ParasiticCharacteristics
Idiode, Igb, …
History Effect
| IEEE SSC Society Fort Collins Chapter | Nov 10, 200811
Challenges in Measurement & Calibration
Active
Gate Poly
P+ I/I
STI
P+ N+
P+ P- P w/ halo
Parasitic Opposite-Type Gate
Bridge-Region Easily Gets Fully-
Depleted
| IEEE SSC Society Fort Collins Chapter | Nov 10, 200812
Parasitic Opposite-Type Gate
Big discrepancy in Igb characteristic due to the parasitic Especially in inversion region
Solutions:Selectively use specific regionsUse bulk wafer
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.510-14
10-13
10-12
10-11
1x10-10
1x10-9
1x10-8
1x10-7
1x10-6
Bulk BT/SOI IGG IGB
Gat
e C
urre
nt [A
]
VG [V]
pMOS
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.510-14
10-13
10-12
10-11
1x10-10
1x10-9
1x10-8
1x10-7
1x10-6
Bulk BT/SOI IGG IGB
Gat
e C
urre
nt [A
]
VG [V]
nMOS
| IEEE SSC Society Fort Collins Chapter | Nov 10, 200813
Fully Depleted Body
Body bias can cause a fully-depleted bodyLow-doped bridge region can introduce artifacts in measured dataSolutions:
Selectively use specific regionsEmphasize intrinsic response
-0.6 -0.4 -0.2 0.0 0.2 0.4 0.60.0
0.1
0.2
0.3
0.4
0.5
VDS=1.2V
VDS=0.1V
nMOSFET 2/0.0875μm
V T [V
]
Vbs [V]
Body-Effect
-1.0 -0.5 0.0 0.50.0
0.5
1.0
1.5
CJu
nctio
n [pF
]
Vbias [V]
Junction Capacitance
DBS1
Slide 13
DBS1 I cannot change this graphic image, but it should not be hyphenated because the ly in fully = the hyphen in this use David B. Schlosser, 9/13/2008
| IEEE SSC Society Fort Collins Chapter | Nov 10, 200814
Implicit Calibration using RF Data
RF measurement offers much implicit information:Self-heating response timeImpact ionizationBody-contact time constant
103 104 105 106 107 108 109 101080
82
84
86
88
90
Body-Contacted
Floating-Body
Tran
scon
duct
ance
(Gm)
Frequency [Hz]
Self-heating
Impact Ionization
Body Resistance
| IEEE SSC Society Fort Collins Chapter | Nov 10, 200815
What Causes Floating-Body Effect?
Source Drain
Substrate
Buried Oxide
Body potential is a function of:Capacitive coupling to
SourceDrainGateSubstrate (small)
Diode leakages toSourceDrain
Gate leakageImpact ionization
Also subject to the previous switching history
| IEEE SSC Society Fort Collins Chapter | Nov 10, 200816
CMOS Inverter Operation
| IEEE SSC Society Fort Collins Chapter | Nov 10, 200817
Definition of History-Effect
| IEEE SSC Society Fort Collins Chapter | Nov 10, 200818
Definition of History-Effect
1st switch : input transition after being held constant for a long time2nd switch: input transition short time after the 1st switch
τ 1st
τ 2nd
History-effectH = (τ 1st – τ 2nd) / τ 2nd
| IEEE SSC Society Fort Collins Chapter | Nov 10, 200819
Typical History-Effect
Delay is subject to switching history of the logic gate
Input Clock Shape
Dynamic Steady State
2nd SW
1st SW
10-10 10-9 10-8 10-7 10-6 10-5 10-410
11
12
13
14
15
Time [s]
Del
ay/S
tage
[ps]
tr=tf=0.8ns
tper=40ns (50% duty)
step=100ps
Evolution of Switching Delay
| IEEE SSC Society Fort Collins Chapter | Nov 10, 200820
Pulse Compression vs. Expansion
Positive H (τ 1st > τ 2nd)
Negative H (τ 1st < τ 2nd)
Compression
Expansion
| IEEE SSC Society Fort Collins Chapter | Nov 10, 200821
12.3%
10-10
10-9
10-8
10-7
10-6
10-54
4.5
5
5.5
6
6.5
Time [s]
Del
ay/S
tage
[ps]
1st trr
2nd tff
tr=t
f=0.8ns
tper
=40ns (50% duty)
step=100ps
12.3%
10-10 10-9 10-8 10-7 10-6 10-5 10-465
70
75
80
85
90
95
100
1s t trr
2nd tff
IBM 9S2 Model (1.2V 25C)
tr=t
f=0.8ns
tper
=40ns (50% duty)
s tep=100ps
14.9%
10-10 10-9 10-8 10-7 10-6 10-5 10-465
70
75
80
85
90
95
100
1s t trr
2nd tff
IBM 9S2 Model (1.2V 25C)
tr=t
f=0.8ns
tper
=40ns (50% duty)
s tep=100ps
14.9%
10-4
Time [s]D
elay
/Sta
ge [p
s]
Impact of Loading on History-Effect
Unloaded Heavily Loaded
Very limited impact of loading capacitanceExtremely large loading (100fF) -- changing switching delay by ~15XOnly changes ~2% in history-effect
| IEEE SSC Society Fort Collins Chapter | Nov 10, 200822
Combined Capacitive/Resistive Network
R1C1
R2C2
Time
Vol
tage
R-Divider
C-Divider
RC Decay
| IEEE SSC Society Fort Collins Chapter | Nov 10, 200823
Time for Actual Contribution to Speed
1st SW : Initial DC2nd SW : Initial DC + Capacitive Coupling
Capacitive Coupling
Initial DCConditions
| IEEE SSC Society Fort Collins Chapter | Nov 10, 200824
Capacitive Coupling
Capacitive coupling is stronger to drain than to gate
Gate Coupling
Drain Coupling
Gate Coupling
Drain Coupling
| IEEE SSC Society Fort Collins Chapter | Nov 10, 200825
Key Components (Initial DC Condition)
1st SW InitialKCL balance between forward and (reverse Idiode+IGIDL+II/I)Accumulation Igb is much smaller than forward Idiode
2nd SW InitialKCL balance between forward Idiode*2 and inversion Igb
1st SW1st SW
Idio,forIdio,for
Igb,accIgb,acc
Igb,invIgb,inv
2nd SW2nd SW
Idio,forIdio,for
Idio,revIGIDLII/I
| IEEE SSC Society Fort Collins Chapter | Nov 10, 200826
Key Components (Capacitive Coupling)
Basically a voltage-divider that consists ofGate-body capacitance, and Junction capacitance
revjforjaccgb
revjDDbs CCC
CVV
,,,
,
++=Δ
Cj,forCj,for
Cj,revCj,rev
Cgb,accCgb,acc
VDDVDD
+
ΔVb-
+
ΔVb-
| IEEE SSC Society Fort Collins Chapter | Nov 10, 200827
Key Components (Body-Effect)
Body potential is established mostly by diode and gate characteristics (DC and AC)This body potential is translated into the actual switching performance by the body-effect (the main transfer function)
Vbody
Vt vs. Vbody
Vt & speed
Diode currentGate current
Gate capacitanceJunction capacitance
| IEEE SSC Society Fort Collins Chapter | Nov 10, 200828
Impact of Gate Capacitance & Current
Cgb is critical for VDD dependence slopeIgb became a major factor from 90 nm technology onward
Increasing inversion Igb
2nd Vb ↑
0.8 1.0 1.2 1.4 1.6-10
-5
0
5
10
15
20
25
30
(1st-2
nd)/2
nd [%
]
VDD [V]
Inversion Igb ImpactInversion Cgb Impact
0.8 1.0 1.2 1.4 1.6-10
-5
0
5
10
15
20
25
30
(1st-2
nd)/2
nd [%
]
VDD [V]
Increasing accumulation Cgb
2nd Vb ↓
dbsbgb
dbDDndb CCC
CVV++
=Δ 2,
| IEEE SSC Society Fort Collins Chapter | Nov 10, 200829
Impact of Diode Current
The diode current characteristic is the key characteristic dominating the VDDand temperature dependences of the history-effect
Proportional to forward Idiode
Inversely proportional to reverse Idiode
Increasing forward Idiode
1st Vb ↓↓ 2nd Vb ↓
Forward Idiode Level Impact
0.8 1.0 1.2 1.4 1.6-10
-5
0
5
10
15
20
25
30
(1st-2
nd)/2
nd [%
]
VDD [V]
Reverse Idiode Impact
0.8 1.0 1.2 1.4 1.6-10
-5
0
5
10
15
20
25
30
(1st-2
nd)/2
nd [%
]
VDD [V]
Increasing reverse Idiode
1st Vb ↑
| IEEE SSC Society Fort Collins Chapter | Nov 10, 200830
Final Reproduction of History-Effect
0.6 0.8 1.0 1.2 1.4 1.6
0
5
10
151000-stage Delay ChainINV FO=1 @25oCTechnology-A
His
tory
Effe
ct [%
]
VDD [V]
Data Model 25oC 100oC
The measured history-effect can be successfully reproduced across a wide range of conditions when all the key components are properly modeled
| IEEE SSC Society Fort Collins Chapter | Nov 10, 200831
Other Floating Body Effects: Parasitic BJT
2007 CICC by W. Wu et al.
C
C
OUTIN
| IEEE SSC Society Fort Collins Chapter | Nov 10, 200832
Challenges: Statistical Modeling
0.8V 1.0V 1.2V 1.5V-5
0
5
10
15
Data Typical Corner
1000-stage Delay ChainINV FO=1 @25oC46-Sites in TotalTechnology-B
His
tory
Effe
ct [%
]
VDD [V]
Single-stage logic gate measurementRequires very high-accuracy test equipmentExtremely low throughput
Delay chain measurementAveraged over all stages, loosing variation detailsLarge area
In-line characterizationApproximate precision
| IEEE SSC Society Fort Collins Chapter | Nov 10, 200833
Back-Bias Range of Interest
Sometimes the body effect is not able to fit for the entire rangeThen some range should be compromisedSeparating body-contacted and floating-body models maybe more desirable
Body-Contactedand Bulk
Floating Body
-0.6 -0.4 -0.2 0.0 0.2 0.4 0.60.0
0.1
0.2
0.3
0.4
0.5
VDS=1.2V
VDS=0.1V
nMOSFET 2/0.0875μm
V T [V
]
Vbs [V]
Reverse
Forward
| IEEE SSC Society Fort Collins Chapter | Nov 10, 200834
Can Body Be Really Tied?
Body-contacted PD-SOI circuit experiences the coupling effects exactly same as floating-body oneThus, it also exhibits history effect
0.0 0.1 0.2 0.3 0.4 0.5-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
V body
[V]
Time [nsec]
Body Potential Fluctuation
Gate Coupling
Drain Coupling
Body RC Decay
108 109 1010
0
4
8
12WN=WP/2=1μm
(1st-2
nd)/2
nd [%
]
Frequency [Hz]
History Effect of BC CMOS
| IEEE SSC Society Fort Collins Chapter | Nov 10, 200835
Body-Contact: Gate Capacitance
Active
Gate Poly
P+ I/I Drain
Source
Body
An+Ap+
Physical
Drain
Source
Body
BSIMPD ~ BSIMSOI 4.0
Agbcp
Rbodyext Rbp
n+/pn+/p-p+/p-
Rbodyext Rbp
n+/pn+/p-p+/p-
Rbodyext Rbp
n+/p n+/p n+/p
Rbodyext Rbp
n+/p n+/p n+/p
| IEEE SSC Society Fort Collins Chapter | Nov 10, 200836
1 2 3-3 -2 -1 0
VG [V]
CG
G
Body-Contact: Gate Capacitance
∫ ⋅≈ T
FB
V
V GSGGB dVCQ
N+ gateP body
P+ gateP body
Gate CapacitanceActive
Gate PolyP+ I/I
STI
P+ N+
P+ P- P w/ halo
Over-Estimated ∫ ⋅≈ DD
T
V
V GSGGC dVCQ
| IEEE SSC Society Fort Collins Chapter | Nov 10, 200837
Body-Contact: Gate Capacitance
108 109 10106
7
8
9
WN=WP/2=1μm10 FET Segments
Physical Agbcp=An++Ap+
Agbcp=An+
Del
ay (1
st+2
nd)/2
[ps/
stag
e]
Frequency [Hz]
Impact on Switching Delay
0 1 2 30
10
20
30
40
Qp+ Qn+ Qp+/Qn+ Ratio
VG [V]
QG
C
0.0
0.2
0.4
0.6
0.8
Qp+
/Qn+
Charge Ratio
~4.5%
The charge ratio is 0.2 ~ 0.5 within practical range2 ~ 5x overestimation
Its impact of switching delay is not negligible
| IEEE SSC Society Fort Collins Chapter | Nov 10, 200838
Body-Contact: Gate Capacitance
Active
Gate Poly
P+ I/I Drain
Source
Body
An+Ap+
Physical
Drain
Source
Body
BSIMSOI 4.1
Rbodyext Rbp
n+/pn+/p-p+/p-
Rbodyext Rbp
n+/pn+/p-p+/p-
AgbcpAgbcp2
Rbodyext Rbp
p+/p n+/p n+/p
Rbodyext Rbp
n+/p n+/p
| IEEE SSC Society Fort Collins Chapter | Nov 10, 200839
Bias Dependence of Body Resistance
Body resistance is determined by majority carriers in the neutral region
Courtesy of Alvin Loke et al.
| IEEE SSC Society Fort Collins Chapter | Nov 10, 200840
Bias Dependence of Body Resistance
Bias significantly modulates the depletion region; in turn, body resistanceNot captured in BSIMSOIWell captured in PSP-SOI
2007 CICC by W. Wu et al.
Gate Bias DependenceBody Bias Dependence
| IEEE SSC Society Fort Collins Chapter | Nov 10, 200841
Body-Contact: Distributed Body R
Single LumpedDistributed
Rbodyext RbpH/N
n+/pFET
n+/p-cap
p+/p-cap
n+/pFET
RbpH/N
N segments
Rbodyext Rbp
ModelMeasurement
DC Values AC Values?
| IEEE SSC Society Fort Collins Chapter | Nov 10, 200842
Body-Contact: Distributed Body RRule of Thumb
Factor of 1/3 for single-side contact; 1/12 for double-side contactMathematically derived for gate resistance noise
A. B. Philips, BJT Base Resistance (McGraw-Hill, 1962)R. P. Jinal, MOSFET Gate Resistance (IEEE T-ED, pp. 1505-1509, October 1984)
Applicable for other distributed resistance associated with active gain
108 109 1010
0
2
4
6
8
1010-seg T-gate10-seg H-gate 1-Lump 1/3 1-Lump 1/12
Technology-CWN=WP/2=5μm
His
tory
Effe
ct [%
]
Frequency [Hz]
| IEEE SSC Society Fort Collins Chapter | Nov 10, 200843
PD-SOI Circuit Simulation: Accuracy
Accuracy optionsΔVbody << VDD needs higher accuracy in voltage convergence criteria (vntol, etc.)Ibody << IDS needs tighter control on off-conductance of capacitors (gmindc)Stronger sensitivity of diode currents at low temperature needs special attention on numerical convergence criteria
10-9 10-8 10-7 10-6 1x10-5 1x10-44
5
6
7
8
Del
ay/S
tage
[ps]
vntol in HSPICE [V]
1st SW 2nd SW
| IEEE SSC Society Fort Collins Chapter | Nov 10, 200844
PD-SOI Circuit Simulation: TimeHarmonic balance
Solves Fourier series in f-domainRequires over-sampling and sufficient harmonics
Periodic steady stateProjects the evolution of the net body charges using the Newton method
Indirect body initialization technique
.ic v(n)=VDD/2Transient HB
Speed up by orders in magnitude
Charging/dischargingCircuits in sleep and wake-up modes
Steady-stateCritical for larger multi-input circuits, SRAMs, clock drivers, I/O, PLL, etc.Takes µs~ms impractically long
10-9 10-7 1x10-5 10-3 10-140
45
50
55
60
Sw
itchi
ng D
elay
[ps]
Time [sec]
Transient Transient HB
10-9 10-7 1x10-5 10-3 10-140
45
50
55
60
2nd SW
Technology-D
1st SW
Sw
itchi
ng D
elay
[ps]
Time [sec]
Transient Transient HB
| IEEE SSC Society Fort Collins Chapter | Nov 10, 200845
Model Standardization
Compact Modeling Council (CMC)Hosted by the Government Electronics and Information Association (GEIA)Evaluates fundamental physics and numerical properties
Symmetry, continuity, convergence, and runtime
Publishes requirements and procedure
BenefitsConsistency in implementation on user sideRecognition and funding to model developersImproved model accuracy and features
Through detailed review during the standardization process
CMC-Standard SOI ModelBSIMPD BSIMSOI (University of California, Berkeley)Next-generation SOI standardization was kicked off in 2006Candidates
PD PSP-SOI PD, XSIM PDDD (FD) PSP-SOI DD, HiSIM-SOI, ULTRA-SOI, XSIM DD
| IEEE SSC Society Fort Collins Chapter | Nov 10, 200846
Conclusion
Reviewed the current and future challenges in compact modeling, characterization, and circuit simulation of PD-SOI CMOSFloating-body effects
One of the main performance boostersMain complexity in PD-SOI compact modelingMeasuring key components is challengingNevertheless, mechanisms are well understood; thus, can be reproduced
Body-contacted device modelingParasitic gate capacitance and body resistance need to be accurateDistributed effect of the body resistance can be simplified
PD-SOI simulation requires tighter convergence criteria and novel simulation techniques, mainly due to the floating-body effectsModel standardization promotes implementation consistency and improved accuracy and features.
| IEEE SSC Society Fort Collins Chapter | Nov 10, 200847
Acknowledgments
Advanced Semiconductor Technology Alliance (ASTA)Technical contributions
K. Bernstein (IBM)B. Rice (Freescale)
Management supportA. Icel and N. Kepler (AMD)S. Springer and R. Wachnik (IBM)S. Jallepalli and M. Zunino (Freescale)
Academic SOI Compact Modeling Research GroupsBSIMSOI Prof. Chenming Hu (University of California, Berkeley)PSP-SOI Prof. Gennady Gildenblat (Arizona State University)UFSOI Prof. Jerry G. Fossum (University of Florida, Gainesville)HiSIM-SOI Prof. Mitiko Miura-Mattausch (Hiroshima University)XSIM Prof. Xing Zhou (Nanyang Technological University)ULTRA-SOI Prof. Jin He (Peking University)