Crosstalk Noise Optimization by Post-Layout Transistor Sizing

Masanori HashimotoMasao Takahashi

Hidetoshi OnoderaDept. CCE, Kyoto University

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Post-Layout Tr. Sizing for Crosstalk Noise Reduction Overview

Crosstalk noise depends on• coupling length• coupling position

• driver strength of aggressor• hold strength of victim

Routing & interconnect optimization

Our target

Use analytic noise model suitable for a lot of repetitive noise estimation

Optimize Tr. sizes preserving interconnects no iterations between Tr. sizing and layout

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Post-Layout Tr. Sizing for Crosstalk Noise Reduction Features

Downsize too strong drivers continuous sizing vary PN ratio consider noise margin and transition

time constraints

Optimization with interconnect preservation no iterations between layout and Tr. sizing

accurately-extracted coupling information

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On-Demand Cell Layout Generation(VARDS)

Same height

Normal size Half size

Shrink Tr. width

Terminals arefixed.

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Contents

Crosstalk noise estimation Noise optimization algorithm Experimental results Conclusion

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Generic RC Trees on LSI

victim

aggressor 1

aggressor 3

aggressor 2branch 1

branch 2

Multiple aggressors, multiple branches

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Noise estimation for two partially-coupled interconnects closed-form noise waveform

Multiple aggressors superpose noises from each aggressor

Multiple sinks transform into two partially-coupled

interconnects

Crosstalk Noise Estimation 　 Overview

Aggressor

Victim

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Modeling of Two Partially-Coupled Interconnects

Vnoise(t)

victim model

aggressor model Vagg(t)

Vagg(t)

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Noise Waveform and Peak Noise Voltage

Rv1 Rv2 Rv3

Cv1 Cv2 Cv3

CcVagg

Vnoise

333223211 )()( vvcvvvcvvvvv CRCCCRCCCCR

va tt

va

ddcvvnoise ee

VCRRtV

//21)(

va

v

v

a

a

ddcvvpeak

VCRRV

21

peak noise

noise waveform

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Multiple Aggressors

victim

aggressor 1

aggressor n

Vnoise1(t)

aggressor n

Vnoisen(t)aggressor 1

Vnoise(t)

Vnoise(t)=Vnoise1(t)+・・・+Vnoisen(t)

Superposition

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Superposition Considering Timing Window

j jpeaknoise VtktV ,)()(

0

1)(tk

fastest arrival time t latest arrival time

other

Superposition of peak noise

(timing window)

Timing window calculation

Fastest arrival time: STA with coupling cap. multiplied by -1Latest arrival time: STA with coupling cap. multiplied by 3

[P. Chen, et.al., ICCAD2000]

Eliminate pessimistic estimation using timing window

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Contents

Crosstalk noise estimation Noise optimization algorithm Experimental results Conclusion

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Optimization Algorithm in Each Victim Net

Downsize Tr. Select agg. net with max-priority from no

n-optimized net. Downsize Tr. such that Va

2+Vv2 is minimu

m. Finish?

All aggressors are optimized? Noise is smaller than Vtarget?

ipeakii Vslackpriority ,

Calculate priorityi

Downsize Tr.

Finish？Y

N

start

end

timing marginnoise voltage

victim

aggressor aggressor

High priority strong impact and loose timing constraint downsize

Consider both noisesat aggressor and victim

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Overall Optimization Algorithm

Put nets into L Put nets(> threshold・ Vmax) into list

L. Execute local opt.

Optimize net with max-noise in L. threshold・ Vmax is target value Vtarget.

Finish? L is empty?

Calculate noise

Execute local opt.

Finish？Y

N

start

end

Put nets into L

Execute several times, decreasing threshold.1 threshold 0

Peak noise reduction Most of nets are optimized.

Global optimality

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Contents

Crosstalk noise estimation Noise optimization algorithm Experimental results Conclusion

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Experimental Conditions

0.35m technology Two combinational circuits designed for minimizing de

lay dsp_alu: 2.3x2.3mm2, 13k cells des: 0.8x0.8mm2, 3k cells

RC extraction Small coupling caps.(<10fF) are treated as caps. to ground.

Supply voltage: 3.3V Cell height: 13 routing pitches

Tr. Width: 6.2m(standard), 0.9m(minimum)

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Optimization Results of Crosstalk Noise Reduction

des circuit dsp_alu0.40 -> 0.19 peak noise[V] 1.00 -> 0.50

12 CPU time[s] 6043.4k #cells 13k

Optimize noise without delay increase

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Initial and Optimized Layouts

Initial

Optimized

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Accuracy of Peak Noise Estimation

Average error: 10mV

All coupled interconnects in des circuit

Actual interconnects with branches driven by CMOS gates

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Conclusion

Propose crosstalk noise reduction method by post-layout Tr. sizing use analytic noise model downsize too strong aggressors preserve interconnects completely reduce peak noise by 50%