R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003

DEPFET pixel sensor – concept and statusDEPFET pixel sensor – concept and status

» DEP(leted)F(ield)E(ffect)T(ransistor) operation principles

» DEPFET prototype run

» Simulation and design examples

» Production status

» Read out electronics and steering chips

» Summary

R.H. Richtera, L. Andriceka, P. Fischerb, G. Lutza, I. Pericc, J. Treisa, M. Trimplc, N. Wermesc

aMPI Halbleiterlabor Munich bUniv. of Mannheim

cUniv. of Bonn

R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003

DEPFET-PrincipleDEPFET-Principle

FET integrated on high ohmic n-bulk

Collection of electrons within the internal gate

Modulation of the FET current by the signal charge!

p+

p+ n+

n

n+

totally depletedn --substrate

internal gate

rear contact

source top gate drain bulk potential via axistop-gate / rear contact

V

potential m inim umfor electrons

p-channel

p+

Radiation

-

-

- -+

+

++

-

-

~1m

~300 m

Advantages: Amplification of the charge at the position of collection=> no transfer loss

Full bulk sensitivity Non structured thin entrance window (backside) Very low input capacitance => very low noise

R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003

Proposed concept for TESLAProposed concept for TESLA

• thin detector-area down to 50µm• frame for mechanical stability carries readout- and steering-chips

first thinned samples:

[L.Andricek, MPI Munich]

steering chips

readout chips

520 x 4000 pixelDEPFET-Matrix

(25 x 25 µm pixel)

readout chips

matrix is read out row-wise

R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003

2 4 6

0

1000

2000

3000

4000

5000

6000

Escape - Peak

K

K

# Z

ähle

r

Energie [keV]

ENC = 4.8 +/- 0.1 e-

55Fe-spectra @ 300K

Excellent noise values measured on single pixels

BioScope - imaging of tracer-marked bio-medical samples

(P. Klein and W. Neeser)

Noise: ca. 70 ENC @ 300KSlow operation (old technology)Large arrays are impossible(JFET => VP variations)Large cell size

R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003

DEPFETDEPFET pixel matrix pixel matrix

- Read filled cells of a row- Clear the internal gates of the row - Read empty cells

Low power consumption

Fast random access to specific array regions

R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003

DEPFET TechnologyDEPFET Technologyon 6” waferon 6” wafer

Double poly / double aluminum process on high ohmic n- substrate

along p-channel perpendicular to channel (with clear)

R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003

Rectangular DEPFET pixel Rectangular DEPFET pixel detectordetector

MOS transistor instead of JFET

A pixel size of ca. 20 x 20 µm² is achievable using 3µm minimum feature size.

Active Pixel Sensor (rectangular)

• 2 pixels

30 x 30 µm²

• DEPFET

L = 5 µm

W = 18 µm

reduce the required read out speed by 2doubles the number of read out channels

R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003

Potential during collection - 3D Poisson equation (Poseidon)Potential during collection - 3D Poisson equation (Poseidon) (50µm thick Si, N (50µm thick Si, NBB=10=101313cmcm-3-3,V,VBackBack=-20V)=-20V)

Depth 10µmDepth 7µmDepth 4µmDepth 1µm

So

urce

sD

rain

External (internal) Gates

n+

cle

ar

con

tact

s

Cell size 36 x 27 µm²

R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003

Current production statusCurrent production status

Pixel array section – design with clockable clear gatePixel array section – design with clockable clear gate

Done:

N-side with two polysilicon layers and contact openings

Backside processing

Aluminium Sputtering

To do:- 1st metal lithography (2 weeks)- First measurements- 2nd metal process

Drain Gate

Clear

Cleargate

Source

1 pixel cell

R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003

Readout architecture (triggerless) Readout architecture (triggerless)

keep potential at input node constant (regulated cascode)

(signal+pedestal current) stored in current memory cell (inverting property)

pedestal current after reset subtracted automatically

signal value is stored in FIFO (analog part)

hit identification with current comparator and store hit pattern in FIFO (digital part)

FIFO is emptied row wise:

DEPFET provides current + fast readout neededcurrent based readout (see Vertex2002 proceedings)

• ‘hit finder’ identifies hits in a row and multiplexes (MUX) the appropriated currents to ADC (respective analogous outputs)

R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003

Chip development for TESLAChip development for TESLA

TSMC 0.25µm, 5metal radiation tolerant design with annular nmos transistors contains: various current memory cells, hit finder, comparator size: 4 x 1.5 mm2

Readout chip 1.0: Steering chip:

AMS 0.8µm HV-Process steers 64 DEPFET-rows (cascadable) size: 4.6 x 4.8 mm2

internal sequencer flexible pattern

[I.Peric (Bonn) / P.Fischer (Mannheim)]

[M.Trimpl (Bonn)]

R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003

Results Results

digital part:hitfinder und comparator work with 50MHz

analoge performance:• 25 MHz sample frequency• 0.1 % differential nonlinearity (for 10µA (~ 10000 e-) dyn. input range)• 38 e- Noise (for complete analogous stage)

U2I

I2UR/O chip:

Readout concept works2 4 6 8 10 12

50

100

150

200

250

300

350Samplenoise of memory cell

m = 27,74 +/- 0,44 e- / sample

c = 15,82 +/- 3,6 e-

@ room-temperature 25 MHz - Samplefrequency

nois

e [e

lect

rons

]

sqrt (samples)

steering chip:

works with 50MHz @ 15pF load capacitance

[Testsetup for current memory cells]

R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003

Prototype system ...Prototype system ...

PC

Hybrid-PCB with• separate steering chips für select und reset • 64x128 pixel array• new R/O-Chip

Readout-PCB with

• ADC and RAM (external)• Datatransfer between Hybrid and PC

DEPFET -Matrix(25x25 µm)

Re

set

-Sw

i tc

he

r

R/O Chip 2.0

Gat

e-S

wi t

ch

er

Hybrid

Readout-PCB

ADC

DATA-RAM Controller

Sequencer

R/O chip (July 2003):

• readout chip with 128 channels• 50MHz sample frequency• 25 e- noise

R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003

Summary / scheduleSummary / scheduleo Key features: low noise, full bulk sensitivity, no charge transfer loss, low power

consumption, random access within an arrayo A new DEPFET technology (2 poly/ 2 aluminum) was developed for large arrays and

high speed operation.o A DEPFET prototype production has been started with DEPFET arrays

30 x 30 µm² pixel size. o First measurements in 2 weekso Read out electronics first test chip successfully tested (50MHz operation possible) o 128 channel read out chip (2.0) currently in design, submission this month, chip

delivery in summero Steering chip for Gate and Clear access successfully fabricated

(first tests very encouraging) o Complete prototype system ready by end of the year

Further plans

In 2004: Design and production of large arrays

Some wafer on SOI (thinned technology) ?

R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003

Back up transparenciesBack up transparencies

R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003

Crossing polysilicon linesCrossing polysilicon lines

Problems with demolished polysilicon lines and bad polyI/polyII insulation

Solved now

R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003

Self aligning TechnologySelf aligning Technology

Positions of all essential implantations are determined not by masks but by polysilicon layers

shallow channel implantation

- mandatory for rectangular cells (lateral channel definition)

- reduces parameter variations on the wafer

R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003

Hiding the nHiding the n++-clear contacts-clear contacts

Depth 1µm

The positive Clear pulse removes the electrons from the Internal Gate and also pushs the holesout of the deep p cover region. After returning of theclear the deep p remains negatively charges forminga shield for the signal electrons.

TeSCA (2D, time dependent)Removal of 1600 electrons from the internal gate (VClear=15V)

Simulation of the Clear mechanism

Poseidon (3D Poisson equ.)Includes 3D effects => VClear=20V

R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003

Pixel prototype production (6“ wafer)Pixel prototype production (6“ wafer)for XEUS and LC (TESLA)for XEUS and LC (TESLA)

Many test arrays- Circular and linear DEPFETS up to 128 x 128 pixels minimum pixel size about 30 x 30 µm² - variety of special test structures

Aim: Select design options for an optimized array operation (no charge loss, high gain, low noise, good clear operation) On base of these results => production of full size sensors

Production will be finished in spring

purpose

detector format

pixel size

thickness

noise

readout time/ detector

/ row

particle tracking

1.3 x 10 cm² (x 8)

520 x 4000 pixels

(x 8)

2.1 Mpix (x8)

25 µm

50 µm

~ 100 el. ENC

50 µsec20 nsec

imaging spectroscopy

7.68 x 7.68 cm²

1024 x 1024 pixels

1 Mpix

75 µm

300 ... 500 µm

4 el. ENC

1.2 msec2.5 µsec