Hamburg, 07.05.2003 Marcel Trimpl, Bonn University A DEPFET pixel-based Vertexdetector for TESLA 55. PRC -MeetingHamburg, Mai 2003 M. Trimpl University

Hamburg, 07.05.2003

L ABSiliz ium Labor Bonn

S I

Marcel Trimpl, Bonn University

A DEPFET pixel-based Vertexdetector for TESLA

55. PRC -Meeting Hamburg, Mai 2003

M. Trimpl

University of BonnM.Karagounis, R.Kohrs, H.Krüger, I.Peric, M.Schumacher, M.Trimpl, J.Ulrici, N.Wermes

University of MannheimP. Fischer, M.Harter

MPI Munich, HLLL.Andricek, G.Lutz, R.H.Richter, M.Schnecke-Radau

MPE Garching, HLLS.Herrmann, G.Schaller, F.Schopper, L.Strüder, J.Treis

PNSensor GmbH, HLLK.Heinzinger, P.Lechner, H.Soltau

Hamburg, 07.05.2003


S I


CONTENT

Vertex Detection at TESLA

The DEPFET Principle

DEPFET pixels for TESLA

Present Status

- detector

- thinning

- Switcher (steering)

- CURO (readout) Summary

Hamburg, 07.05.2003


S I



geometry: same for all proposals

• pixel size: 20-30 µm • close to IP, r = 15 mm (efficient c-tagging)• high spatial resolution: few µm• 5 barrels – stand alone tracking• thinned sensor: d = 50µm, ~0.1% X0

• overall: ~ 1GPixel

50µs readout time for module / detector

Required clock rate: up to 50MHz for TESLA @ Layer I

time structure

950 µs 199 ms 950 µs

2820 bunches

high e+e--background: 80 hits / (mm2 train)

Hamburg, 07.05.2003


S I


CONTENT




Present Status

- detector

- thinning



Hamburg, 07.05.2003


S I


p+

p+ n+

rear contact

drain bulksource

p

sym

met

ry a

xis

n+

ninternal gate

top gate clear

n -

n+p+

DEPFET-Principle of Operation

FET-Transistor integrated in every pixel (first amplification) Electrons are collected in „internal gate“ and modulate the transistor-current Signal charge removed via clear contact

-

-

+

+

++

-

MIP

internal Gate

Potential distribution:

Drain

Source

Backcontact

[TeSCA-Simulation]

~1µm

50

µm

- -- ---

Hamburg, 07.05.2003


S I


p+

p+ n+

rear contact

drain bulksource

p

sym

met

ry a

xis

n+

ninternal gate

top gate clear

n -

n+p+

DEPFET-Principle of Operation

FET-Transistor integrated in every pixel (first amplification) Electrons are collected in „internal gate“ and modulate the transistor-current Signal charge removed via clear contact

internal Gate

Potential distribution:

Drain

Source

Backcontact

[TeSCA-Simulation]

~1µm

50

µm

- -- ---

0V

+15V

0V

Hamburg, 07.05.2003


S I


n x mpixel

IDRAIN

DEPFET- matrix

VGATE, OFF

off

off

on

off

VGATE, ON

gate

drain VCLEAR, OFF

off

off

reset

off

VCLEAR, ON

reset

output

0 suppression

VCLEAR-Control

• read pedestal current • reset pixel / clear internal gate (row wise)• read pixel-current at drain

Matrix Operation

Matrix-scheme:

64 x 64 matrix with 50 x 50 µm2 pixel designed for Biomedical Applications clock rate : 50 kHz achieved noise in matrix: ~100e-

(due to operation mode)

DEPFET-Hybrid:

Control-Chip:Switcher I

64x64 pixel DEPFET-Matrix(50x50µm2 pixel)

low noise Readout-Chip: CARLOS

Hamburg, 07.05.2003


S I


achieved performance

2 4 6

0

1000

2000

3000

4000

5000

6000

Escape - Peak

K

K

# Z

ähle

r

Energie [keV]

Single-pixel spectra:

ENC = 4.8 +/- 0.1 e-

55Fe-spectra @ 45C

[J.Ulrici, Bonn]

Autoradiogram with 3H:

~ 10 mm

detection of Tritium 3H(5,6 keV mean energy)

spatial resolution (50x50 µm2 pixel):

~ 4.5µm (22 keV, 109Cd) ~ 6.5µm (6 keV, 55Fe)

~ 3.2 mm

Matrix-picture with 55Fe:

measured atroom temperature

Hamburg, 07.05.2003


S I


CONTENT




Present Status

- detector

- thinning



Hamburg, 07.05.2003


S I


DEPFET-Pixels for TESLA

steering chips

readout chips

520 x 4000 pixelDEPFET-Matrix

(25 x 25 µm pixel)

readout chips

Layer I - Module:

attractive features for TESLA:

• small pixel size (20-30µm)

• low noise thin (50µm) S/N > 70 @ RT

- thin sensor (50µm) + frame 0.11% X0 / layer

• low power consumption little cooling !

- in active area : sensor + R/O chip or steering chip

- whole vtx-d (5 layers / pulsed mode ) :

sensor : 0.3W

steering: ~ 3-4 W

R/O chip: 1-2 W frame: ~300µm

sensor: ~50µm

whole vtx-d: ~5W

Hamburg, 07.05.2003


S I


DEPFET-Pixels for TESLA

attractive features for TESLA:

• small pixel size (20-30µm)

• low noise thin (50µm) S/N > 70 @ RT

- thin sensor (50µm) + frame 0.11% X0 / layer

• low power consumption little cooling !

- in active area : sensor + R/O chip or steering chip

- whole vtx-d (5 layers / pulsed mode ) :

sensor : 0.3W

steering: ~ 3-4 W

R/O chip: 1-2 W

whole vtx-d: ~5W

perforated frame for reduced material

Hamburg, 07.05.2003


S I


steps towards TESLA :

new DEPFET-sensor fabrication - smaller pixels (25µm) improved performance for TESLA

develop thinning of sensors -

fast (50 MHz) steering chip -

fast readout chip with 0 suppression -

(full size) prototype system

finished

first results

fabricated

prototype

Hamburg, 07.05.2003


S I


CONTENT




Present Status- detector

- thinning



Hamburg, 07.05.2003


S I


new sensors for TESLA

from JFETs to MOSFETs less device variation (large sensors), linear transistors (small pixels) double metal process (large sensors) higher amplification (1nA/e-) fast and complete clear

clear contact transistor channel

clear gate

new sensors:Potential distribution (1µm depth)

[Poseidon 3d – Simulator]

clearcontact

internal gate

potential energy [eV]

double pixel-cell

Hamburg, 07.05.2003


S I


new fabrication

just finished (April 2003) ...

16x128 DEPFET-Matrix

double pixel cell 33 x 47 µm2

in DEPFET-Matrix

dra

in

gate

reset

Hamburg, 07.05.2003


S I


new fabrication

just finished (April 2003) ...

double pixel cell 33 x 47 µm2

in DEPFET-Matrix

dra

in

gate

reset

First measurements: diode leakage current: ~ 300pA/cm² (fully depleted) pixel transistor:

VTH ~ 0V : Device can be completely switched off.

Step to MOSFETs successful

Hamburg, 07.05.2003


S I


DEPFET thinning

[L. Andricek, MPI Munich]

TESLA-Module („dummy“ sample) 50µm silicon with 350µm frame

thinned diode structures:leakage current: <1nA /cm2

d) anisotropic etching from backside (TMAH)

open backside passivation

c) process passivation

b) wafer bonding and grinding/polishing of top wafer

a) oxidation and back side implant of top wafer

Handle <100> Wafer

Top Wafer

Hamburg, 07.05.2003


S I


new steering chip

• AMS 0.8µm HV• versatile sequencing chip (internal sequencer flexible pattern)• high speed + high voltage range (20V)• drives 64 DEPFET-rows (can be daisy chained)• produced 12/2002

Switcher II:

[I.Peric (Bonn) / P.Fischer (Mannheim)]

4.6 mm

4.8

mm

Results:• power consumption: ~1W /channel• tested ok to 30MHz

1 0 1 1

U = 20V = 30 MHz

20ns

Hamburg, 07.05.2003


S I


IBias

input output

sample

I In

CGate

Current based Readout

Storage phase: input and sample-switch closed : gate-capacitance of nmos charged ISTORE

Transfer phase: output switch closed : (done immediately after sampling) ISTORE is flowing out

Sampling phase: input and sample-switch opened : voltage at capacitance „unchanged“ current unchanged

I = I In + IBiasI = I In + IBias

How to store a current ??

Hamburg, 07.05.2003


S I


CURO - Architecture

front end: automatic pedestal subtraction (double correlated sampling) - easy with currents -

analog currents buffered in FIFO

Hit-Logic performs 0 suppression and multiplexes hits to ADC (ADC only digitizes hits !)

CURO : CUrrent Read Out

Hamburg, 07.05.2003


S I


Results - CURO I

TSMC 0.25µm, 5metal contains all blocks for a fast DEPFET R/O radiation tolerant layout rules with annular nmos produced 05/2002

CURO I:

analog part (current memory cell):• tested up to: 25MHz• differential non-linearity: 0.1 %• noise contribution to readout: < 39e-

digital part: works with desired speed (50MHz)

0 10 20 30 40 50 60 70

0

10

20

30

40

50

60

70

IBias

= 70µA

Measured linearityof memory cell

Iou

tpu

t [µ

A]

Iinput [µA]

crucial elements of readout concept work

4 mm

1.5

mm

Hamburg, 07.05.2003


S I


Prototype System

Hybrid-PCB:

• steering chips for Gate and Reset (Switcher II) • 64x128 pixel DEPFET-Matrix• 128 channel R/O – Chip (CURO II) - submission scheduled: july 2003 - improved sampling speed : 50MHz - analog noise contribution : < 30 e-

- linearity well below 1%

PC

DEPFET -Matrix(25x25 µm)

Re

set

-Sw

i tc

he

r

CURO II

Gat

e-S

wi t

ch

er

Hybrid

Readout-PCB

ADC

DATA-RAM Controller

Sequencer Readout-PCB:

• ADC and RAM• communication between

Hybrid and PC

Hamburg, 07.05.2003


S I


Summary

main DEPFET features

high S / N ~ 70, high spatial resolution (~2 µm, analog readout) thin (50 µm) low power (< 5W total, pixel inactive during charge collection) current based fast readout (50 MHz)

Hamburg, 07.05.2003


S I


Outlook

2nd version of readout chip (CURO II): july 2003 study new DEPFET structures: summer 2003 system assembly: 2nd half of 2003 radiation hardness issues

prototype system

full size TESLA Module

Hamburg, 07.05.2003


S I


Hamburg, 07.05.2003


S I


Power consumption

• R/O Chip: 2mW / channel 200 W (whole vtx-d)

Number of R/O channels @ TESLA:

L1 : 520x2x8 = 8320 L2-5: (880x2)x(8+12+16+20) = 98560 All: 106880 channels

• Sensor: PDEPFET = 5V x 100 µA = 500µW 50 W

• Steering: 0.94mW /channelDC, 3.13mW / channel @ 50MHz

L1 : 2x3.13 + (3998x0.94) mW= 34W

L2-5: [2*3.13 + (13538x0.94)] x (8+12+16+20) mW = 713W

All: 747 W

All : 997W , 1/199 duty cycle : 5W

Hamburg, 07.05.2003


S I


material budget

Estimated Material Budget (1st layer):

Pixel area: 100x13 mm2, 50 m : 0.05% X0

steer. chips: 100x2 mm2, 50 mm : 0.008% X0

(massive) Frame :100x4 mm2, 300 m : 0.09% X0

Steuerchips

Auslesechips

520 x 4000 pixelDEPFET-Matrix

(25 x 25µm Pixel)

Auslesechips

reduce frame material!!!by

etching of "holes" in the frame

perforated frame: 0.05 % X0

total: 0.11 % X0

5-layer (CCD-like) layout for the vertex detector 1st layer module: sensitive area 100x13 mm2

sensitive area thinned down to 50 m, supported by a directly bonded 300 m thick

frame of silicon

Hamburg, 07.05.2003


S I


0 10 20 30 40 50 60 700,2

0,4

0,6

0,8

1,0

1,2

1,4

1,6

1,8

2,0

10nA

Accuracy of memory cell

Iout

- Ii

n [µ

A]

Iinput [µA]

Performance of Prototype R/O Chip

analog part (memory cell): speed: 25MHz accuracy: 0.1 % noise : < 30 electrons

digital part: the hit-finder and the current-comparator-block both work with desired speed (50MHz)

2 4 6 8 10 1250

100

150

200

250

300

350Samplenoise of memory cell

m = 27,74 +/- 0,44 e- / sample

c = 15,82 +/- 3,6 e-

@ room-temperature 25 MHz - Samplefrequency

nois

e [e

lect

rons

]

sqrt (samples)

0.1% accuracy reached

Hamburg, 07.05.2003


S I


different readouts

Layer I: Layer II..V:

Steuerchips

Auslesechips

650 x 5000 PixelDEPFET-Matrix

(20 x 20µm Pixel)

Auslesechips

Hamburg, 07.05.2003


S I


Background at TESLA

High magnetic field to „reduce“ background

But still:

Rate high ( 80 hits / mm bunchtrain ) One frame per Train: Occupancy 20% !!!!!

Simulation:

[C.Büssser, DESY]

Documents

Hamburg, 07.05.2003 Marcel Trimpl, Bonn University A DEPFET pixel-based Vertexdetector for TESLA 55. PRC -MeetingHamburg, Mai 2003 M. Trimpl University