Designing for EMI Compliance_1

7/31/2019 Designing for EMI Compliance_1

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EMI Compliance Design

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Feasibility and cost of EMC measures

Feasibility of

EMC measures

Cost of

EMC measures

Design improvement of prototype production in field

Stage working period

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Few coverage points

EMI Problems

Fundamentals revisit

Noise coupling

Grounding

Shielding

filtering

Protection General Engineering guidelines

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Electromagnetic Interference

There are three essentials to any EMI Problem.

Source CouplingPath

Receiver

orVictim

Electromagnetic problems are generally solved by identifying

at least two of these elements and eliminating (or attenuating)one of them.

Amplitude, Waveforms, Frequency Sensitivity, BandwidthConducted, Radiated

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Methods of Eliminating Interference

Shielding

Grounding

Filtering

Isolation

Separation and orientation Circuit impedance level control

Cable design

Cancellation techniques

Important : Noise cannot be completely eliminated only can be

minimised. Unique solution to noise reduction problem may notexist.

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Some fundamentals

A Quick Look for Designers

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Technology evolved for Backbone

for e.g. Intel X86 Family of Processors

4004 8008 8080 8088

X286 X386 X486 Pentium

Pentium Pro P2 P3 P47


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Other view

Source : Intel

Website

Technology evolved for Processors

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Ideal vs. In-application use of Passive components

Behaviors of the resistors,Capacitors and Inductors isbased on the frequency of thesignals passing through them

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Frequency we use

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Interference we create

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Coupling

Conducted :

Common impedance ( mostly resistive) with electrical contact

Radiated :

Coupling without electrical contact

Inductive or magnetic ( near H field)

Capacitive or electric (near E field)

Radiative or electromagnetic ( far field)

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Coupling Through Common Impedance

CKT. 1 CKT. 2

GROUNDVOLTAGE CKT.2

GROUNDVOLTAGE CKT.1 COMMON

GROUNDIMPEDANCE

POWERSUPPLY

CKT. 1

CKT. 2

COMMON LINEIMPEDANCE

I1

I2

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Magnetic Coupling

Due to current flowing at the source Magnetic flux is defined for a region with finite boundary so its

representation as inductance is only for a closed loop

Inductive effects if dominant, loop area needs to be reduced oralternatively path taken will be of least loop area

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Inductive Coupling

Powersource

CKT. 1 CKT. 2 CKT. 3 CKT. N

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Magnetic Coupling

Important mitigations aspects are Balanced circuits usage offering same impedance to ground on

both leads

Usage of Twisted pair

Usage of shield grounded at both ends

If design permits connect small capacitor between two leads of

secondary circuits at the terminals of apparatus (selectivefiltering)

Use radial circuits (avoid loops to the extent so as to have anylocation to be reached from one path only)

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Capacitive Coupling

Due to voltage of the source of disturbance

Coupling capacitance depends on distance and low couplingcapacitance is therefore desirable by increasing the distance

Logarithm of distance decided the capacitance

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Capacitive Coupling

Powersource 1

CKT. 1 CKT. 2 CKT. 3

c

c

c

Powersource 2

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Capacitive Coupling

Mitigation methods demands either

Increasing separation

Usage of shield between source and victim with single pointat least grounded

Shield quality not that significant

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Grounding

Classical Definition Ground is "an equipotential point or plane which serves as a

reference for a circuit or system".

Alternative Definition Ground is "a low impedance path by which current can return to

its source".

Objective of Good Grounding System Safety considerations

To minimise the noise voltage generated by currents from twoor more circuits flowing through common ground impedance

Avoid creating ground loops which are susceptible to magneticfields and differences in ground potential.

The purpose of the ground plane is not to provide shielding butto give a low high-frequency ground impedance.

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Signal Grounding

Single point

1 2 31 2 3

Multi Point

Series connection

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For freq. < 1Mhz single point grounding

For freq. >10Mhz multi point grounding


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Earth conductor

Ok for low Freq50Hz/60Hz but poor

for HF

MinimumWirelength is

improvement

Short wide braided

strap is better

Short wide metalplate with multiple

bond is still better

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Advantage of Braided Flat-Cables

High frequencies onlyconducting in surface


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Grounding Issues

Ideally speaking do not separate Analog, Digital, Chassis, audio,Power, etc. grounds. One should have only one ground mainly for intra-equipment applications

Grounding is The Most Important Technique and most economical

weapon in the arsenal of EMI reduction techniques.

If grounding is poor, radiation will increase and also other mitigationtechniques will become ineffective as there operation would dependupon low impedance ground.

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Ground Noise

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Grounding Considerations

Whenever, we make use of different grounds based on functionwe connect them together at one point(at least for DCpurposes).

For the reasons as mentioned back, Single Ground- Directmetallic connection is the best practice.

In a typical system following structures could be under use :

one or more PCB ground planes

metal cabinet or chassis Shields on external (and internal) cables,

Power supply ground

Earth and safety ground

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Single Ground

In case where inter equipment require ground isolation at power linefreq. ( to lessen the problem caused by power-line noise and excessiveground return currents)join the ground capacitively (@1000pf) so thatfor high frequency noise these grounds do become one.

PCB ground planes

One or more entire planes in a PCB should be reserved for ground.Never try to supply ground to the various components via traces-except for 1 /2 layer board where ground traces should be as wideas possible

Never route traces on a ground plane nor take any actions thatresults in cuts or slits in the ground plane that are over 0.5 inches

long.

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Single Ground

Multiple Ground Planes

Use two or more dedicated ground planes with vias at frequentintervals for effectiveness.(One connections per sq. inches)

Ground Flooding on signal layers

Ground flooding is the process where remaining open space(after interconnections) on a layer is flooded with copper. Care

should be taken that no islands of Cu are left floating.Vias usedfor connecting flooded regions to the ground plane should beatleast one per sq. inch

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Single Ground

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Shielding

Shield is a metallic partition used to control propagation ofelectric and magnetic field from one regions to other

Important : Shield acts both as a barrier to radiated interferenceand as a reference point for ground return currents.

Noise source

shield

Noexternal

field

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VENTILATION HOLES/SLOTS

Holes are better than slots

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VENTILATION HOLES/SLOTS

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Design criteria of Equipment and Systems

Input / Output Connections

Isolation transformers (with grounded shields can have fewhundred pF of capacitance)

Opto-isolators ( for digital ckts. Preferably have few pF straycapacitance)

Optical fibres ( offers high BW but cost can be criteria)

Relays ( on/off switching and low freq. Application )

Balancing techniques ( use of twisted pair/ cabling offering sameimpedance w.r.t ground)

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Design criteria of Equipment and Systems

Filtering

Should offer maximum mis-match between the input impedanceof the filter and the line carrying the disturbance so as to offermaximum insertion loss

The voltage/current ratings and the insulation resistance mustbe properly evaluated

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Power line filtering

Based on loss desired the filters to be designed taking into account input and

output impedances ( commercial only for 50e)

Value of series inductance is restricted by operating freq. Voltage drop while, Ycapacitors is limited by allowable leakage current(0.4ma typ.).

To achieve desired insertion loss multi stage filters may be required to be used.

Placement of filters is very very important for achieving desired performance

L

N

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Power line

filtering

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Transient Suppressor Devices

For EFT, ESD tests resistors, ferrite beads and capacitors usuallydont provide the necessary level of suppression.

The energy and speed is higher and faster than these passivecomponents can handle.

Different devices

Spark Gap, MOV, Tranzob

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General Topology of Transient ProtectionNetwork

Diverter generally handles high currents but do not offer precisecontrol of voltages ( Gas tubes and MOVs) and Clamp devices (Tranzorb) have lower impedance than the diverters but havelower energy handling capabilities, however offers fast clamping

Z

D D C

Z

EQUIPMENT

D ; DIVERTER ,Z : IMPEDANCEC : CLAMP

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Surge protective devices

Transient suppressor diodes

Fast switching speed

Suitable for low voltages typically upto 400v

Offer large capacitance ( 500- 2000 pF)

Are basically diodes

Suitable to be used close to the circuit to be protected

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Surge protective devices Varistors

Slower than avalanche diodes

Higher voltages relatively typically upto 2kV

Offer large capacitance (100-4000pF) hence not suitable for HFapplications

Are basically Non-linear resistive elements based on Zinc oxide

Popularly used in power circuits

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Gas arrestors / Spark gaps

Very slow speed

Highest voltages typically upto 10kV ( min around 90V)

Are small sealed spark gaps containing rare gases like

neon/argon. Very low capacitance (1-3pF)

Have relatively smaller life

Used in protection schemes requiring high power handlingcapability specifically during lightening or power faults

Preferred placements at cable entry points

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Principles of Decoupling

Need for decoupling ?

Decoupling capacitor should act as local charge reservoirto satisfy the sudden current demands of a high speeddigital IC as it changes states

Decoupling capacitor ideally is expected to be low passfilter so as to meet emissions related requirements

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Principles of Decoupling

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Decoupler as charge reservoir

During state transitions, most of logic ICs have a period of timeof few nano secs or smaller , where both output transistors areON and hence forcing very high current demand which withassociated series inductance can cause a very high voltagedrop and with fast rise/fall time pulsed requirements it also leads

to emissions

Using decoupler as charge reservoir facilitates local high currentrequirements with least inductance and hence facilitating inmaintaining voltage stability

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Decoupler as filter

ESL ESRC

Practically decoupling capacitors have series eqvt. Ckt. asshown above. Due to this they have resonant freq. Where they

offer least impedance and below which effect is capacitive andabove which it is inductive.( add also lead/trace inductance)

For filtering purpose it is expected to offer minimum impedanceand hence resonant freq. Becomes an important parameter for

its selection. Also above resonant freq, since it effect is inductiveit also forms a voltage divider with the power bus impedancewhich most of the time as such is not too significant

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Selection of Right value of Capacitor

The decoupling capacitor ideally should be selected based on

Minimum value which is set based on transient currentdemand of the IC

The maximum value is influenced by the desire to filternoise at the power freq.

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Some inputs for decoupling capacitors

Decoupling capacitor of unequal value should not be used inclose proximity in parallel because due to unequal value theyform a parallel resonant ckt. which reduces noise rejection atsuch freq. Of formation which overall detoriates the performancewhich could have been achieved by single capacitor

Decoupling capacitor of same value can be used in parallelsince it reduces overall inductance(ESL) and hence increasingself resonant freq.

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Some Thumb rules

Always locate the decoupling capacitor as physically close aspossible to the IC being decoupled

Use a separate decoupling capacitor for each of IC package andits respective pin/s

Never parallel two or more dissimilar values of decouplingcapacitors, unless they are separated by more than 1 inch

Choose decoupling capacitors with extremely low ESL and ESRvalues. For e.g ESR of high quality decoupler should remainbelow 0.1ohm through 100MHz.

Always provide vias to the ground and power planes

immediately adjacent to the ends of the decoupler (I.e. avoiduse of traces)

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Antenna due to poor PCB Layout

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Circuit boards layering

The assignment of specific traces to specific layers in a printedcircuit board is an important part of overall task to suppressemissions.

Multi-layer boards should have following considerations for high

speed traces (Pulse repetition time less than 500nS) :

All high speed traces should be buried between two solid copper layersthat are at ground potential for RF purposes. (Power plane can also beconsidered at ground potential as it has large no of decouplingcapacitors w.r.t ground plane)

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Grounding hole vias

All flooded region of grounded copper should be viaed to theground plane/s as frequently as practical. As a guideline, thereshould be no region of flooded grounded copper that is morethan one inch from the via to the ground plane.

The grounding vias for large holes like used for fixing screws

that fasten to the main board ground should be surrounded byminimum four vias surrounding the main hole so that theimpedance is reduced

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Routing of high speed digital traces

1 Only slow ( < 2 MHz ) traces should be routed on the two surface layers

2 Ground and or power planes should be used to separate layers dedicated to slowspeed traces from those carrying high speed traces

High speed traces

Top surface of PCB

Lower surface of PCB

Ground and/orpower planes

Other layers

Other layers

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PCB design few guidelines

Minimise loop areas ( power and ground traces may be keptcloser together)

Signal lines should be kept closed to ground, logically a groundline should run next to signal line, ground plane can be keptopposite to PCB signal plane, unused areas to be filled with

ground plane,

Bypass capacitors appropriately should be made use of

Keep line length as short as possible

Power and signal should be fed from the centre of the PCB tothe extent possible to reduce length of tracks

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Role play : PCB Designer

High speed traces routed on surface layers and not between groundand or power planes of the board

Slow speed traces routed partially on surface layers and partially onburied layers, resulting in coupling of high frequencies to slow speedtraces

Connecting decoupling or port filtration capacitors via traces rather than

direct connections to ground and power planes Improper positioning of decoupling capacitors and or port filtration

components

Improper layer assignments

No signal layer flooding

Floating islands of copper

Using insufficient vias around mounting holes Allowing slitting of a ground plane by a large multi-pin connector

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Designing for EMI Compliance_1