Digital Integrated Circuits for Communication

Digital Integrated Circuits for CommunicationClass 04Sequential CMOS and NMOS Logic CircuitsSequential logic circuits contain one or more combinational logic blocks along with memory in a feedback loop with the logicThe next state of the machine depends on the present state and the inputsThe output depends on the present state of the machine and perhaps also on the inputsMealy machine: output depends only on the state of the machineMoore machine: the output depends on both the present state and the inputs

Logic Circuit Classification: Sequential Circuit TypesSequential circuits (also called regenerative circuits) fall into three types:BistableMonostableAstableBistable circuits have two stable operating points and will remain in either state unless perturbed to the opposite stateMemory cells, latches, flip-flops, and registersMonostable circuits have only one stable operating point, and even if they are temporarily perturbed to the opposite state, they will return in time to their stable operating pointAstable circuits have no stable operating point and oscillate between several statesRing oscillator

Memory Cell: Two-Inverter Basic Bistable ElementA memory cell is comprised of two inverters connected back-to-back, i.e. output of one to input of the other and vice-versa.The memory cell (or latch) has two stable states where the dc voltage transfer curves cross at the VOH and VOL points, but also exhibits an unstable state.In actual physical circuits the memory cell will never stay at the unstable point, since any small electrical noise in the circuit will trigger it to one side or the otherIn numerical simulation (the circuit may actually remain in the unstable state (assuming no noise source)The CMOS SRAM cell at the left will either be in state 0 with V01 at GND and V02 at VDD or in state 1 with V01 at VDD and V02 at GND.

CMOS SR Latch: NOR Gate VersionThe NOR-based SR Latch contains the basic memory cell (back-to-back inverters) built into two NOR gates to allow setting the state of the latch.If Set goes high, M1 is turned on forcing Q low which, in turn, pulls Q highS=1 Q = 1If Reset goes high, M4 is turned on, Q is pulled low, and Q is then pulled highR=1 Q = 1If both Set and Reset are low, both M1 and M4 are off, and the latch holds its existing state indefinitelyIf both Set and Reset go high, both Q and Q are pulled low, giving an indefinite state. Therefore, R=S=1 is not allowedThe gate-level symbol and truth table for the NOR-based SR latch are given at leftTo estimate Set time, add time to discharge Q + time to charge Q (pessimistic result)

CMOS SR Latch: NAND Gate VersionA CMOS SR latch built with two 2-input NAND gates is shown at leftThe basic memory cell comprised of two back-to-back CMOS inverters is seenThe circuit responds to active low S and R inputsIf S goes to 0 (while R = 1), Q goes high, pulling Q low and the latch enters Set stateS=0 Q = 1 (if R = 1)If R goes to 0 (while S = 1), Q goes high, pulling Q low and the latch is ResetR=0 Q = 1 (if S = 1)Hold state requires both S and R to be highS = R = 0 if not allowed, as it would result in an indeterminate state

Clocked SR Latch: NOR VersionShown at left is the NOR-based SR latch with a clock added.The latch is responsive to inputs S and R only when CLK is highWhen CLK is low, the latch retains its current stateTiming diagram shows the level-sensitive nature of the clocked SR latch.Note four times where Q changes state:When S goes high during positive CLKOn leading CLK edge after changes in S & R during CLK low timeA positive glitch in S while CLK is highWhen R goes high during positive CLK

Clocked CMOS SR Latch: ImplementationCMOS implementation of clocked NOR-based SR latch shown at left with logic symbol circuit belowOnly 12 transistors requiredWhen CLK is low, two series legs in N tree are open and two parallel transistors in P tree are ON, thus retaining state in the memory cellWhen CLK is high, the circuit becomes simply a NOR-based CMOS latch which will respond to inputs S and R

Clocked CMOS JK Latch: NAND VersionThe SR latch has a problem in that when both S and R are high, its state becomes indeterminateThe JK latch shown at left eliminates this problem by using feedback from output to input, such all states in the truth table are allowableIf J = K = 0, the latch will hold its present stateIf J = 1 and K = 0, the latch will set on the next positive-going clock edge, i.e. Q = 1, Q = 0If J = 0 and K = 1, the latch will reset on the next positive-going clock edge, i.e. Q = 1 and Q = 0If J = K = 1, the latch will toggle on the next positive-going clock edgeNote that in order to prevent the JK Latch above from oscillating continuously during the clock active time, the clock width must be kept smaller than the switching delay time of the latch. Otherwise, several oscillations may occur before the clock goes low again. In practice this may be difficult to achieve.

JK Master-Slave Flip-FlopA Flip-Flop is defined as two latches connected serially and activated with opposite phase clocksFirst latch is the Master; Second latch is the SlaveEliminates transparency, i.e. a change occurring in the primary inputs is never reflected directly to the outputs, since opposite phase clocks are used to activate the M and S latches.A JK master-slave flip-flop (NOR-based version) is shown below:The feedback paths occur from Q and Q slave outputs to the master inputs gatesdoes not exhibit any tendency to oscillate when J = K = 1 no matter how long the clock period, since opposite clock phases activate the master and slave latches separately.The NOR-based version can be done with four CMOS gates, requiring 28 transistorsCan be susceptible to ones catching, i.e. a positive glitch in either the J or K input while the CLK is high, which can change the state of the master latch (and the slave latch on next edge)

CMOS D-Latch ImplementationA D-latch is implemented, at the gate level, by simply utilizing a NOR-based S-R latch, connecting D to input S, and connecting D to input R with an inverter.When CLK goes high, D is transmitted to output Q (and D to Q)When CLK goes low, the latch retains its previous stateThe D latch is normally implemented with transmission gate (TG) switches, as shown at the leftThe input TG is activated with CLK while the latch feedback loop TG is activated with CLKInput D is accepted when CLK is highWhen CLK goes low, the input is open-circuited and the latch is set with the prior data D

CMOS D-Latch Schematic View and TimingA schematic view of the D-Latch can be obtained using simple switches in place of the TGsWhen CLK = 1, the input switch is closed allowing new input data into the latchWhen CLK = 0, the input switch is opened and the feedback loop switch is closed, setting the latchTiming diagram:In order to guarantee adequate time to get correct data at the first inverter input before the input switch opens, the data must be valid for a given time (Tsetup) prior to the CLK going low. In order to guarantee adequate time to set the latch with correct data, the data must remain valid for a time (Thold) after the CLK goes low.Violations of Tsetup and Thold can cause metastability problems and chaotic transient behavior.

Alternate CMOS D-Latch ImplementationAn alternate (preferred) version of the CMOS D-Latch (shown at left) is implemented with two tri-state inverters and a normal CMOS inverter.Functionally it is similar to the previous chart D-LatchWhen CLK is high, the first tri-state inverter sends the inverted input through to the second inverter, while the second tri-state is in its high Z state.Output Q is following input DWhen CLK is low, the first tri-state goes into its high Z state, while the second tri-state inverter closes the feedback loop, holding the data Q and Q in the latch.

D Register Implementation in CMOSCMOS implementation of the popular positive edge-triggered D register is shown Comprised of four transmission gates and five invertersOperationClock = 0: Master latch is connected to input to receive new D dataSlave latch is holding previous data on output and is isolated from inputClock = 1:Master latch stops sampling input, latches up the D data at the positive clock edge, and sends it through to the output Q

CMOS Static Latches with Single Phase ClockVarious types of D latch circuit with single phase clocks(a) shows the use of a weak inverter to allow removal of feedback loop X-gate but retain static latch function(b) D latch ckt with input inverter buffer(c) implementation of (b) utilizing tri-state buffer/inverter circuits with clocks at center of tri-stateAlternate schematic of (c) indicating layout convenience due to common tie point at output of tri-state buffers Clock skew problems can be solved on-chip by using buffering in clock netsInverter buffers to generate neg clkTransmission gate buffers for true clk

Construction of D Register (Flip-Flop) in CMOSTwo level-sensitive latches are combined to form a positive edge-triggered register, as is used to build a D register(a) shows negative level sensitive latch (valid when clock is negative)(b) shows positive level sensitive latch (valid when clock is positive)(c) shows positive edge-triggered D register (also called a Flip-Flop) comprised of a negative latch feeding a positive latchFirst latch is the MasterSecond latch is the SlaveD register timing:Output Q valid at Tq (clock-to-Q) delay after clock edgeData must be valid Ts (setup time) prior to clock edge and Th (hold time) after clock edge

CMOS D Flip-Flop: Falling Edge-TriggeredShown below is a D Flip-Flop, constructed by cascading two D-Latch circuits from the previous chartMaster latch is positive level sensitive (receives data when CLK is high)Slave latch is negative level sensitive (receives data Qm when CLK is low)The circuit is negative-edge triggeredThe master latch receives input D until the CLK falls from high to low, at which point it sets that data in the master latch and sends it through to the output Qs

Clocked SR Latch: NAND VersionNAND version of clocked SR latch with active high clock is shownCircuit is implemented with four NAND gates, not with an AOI or OAI16 transistors requiredThe latch is responsive to S or R only if CLK is highWhen CLK is low, the latch retains its present state

Timing Definitions19tCLKtDtc2qtholdtsutQDATASTABLEDATASTABLERegisterCLKDQPositive Feedback: Bi-Stability20

Vo1Vi25Vo1Vi25Vo1Vi1ACBVo2Vi1=Vo2Vo1Vi2Vi2=Vo1Writing into a Static Latch21

DCLKCLKDConverting into a MUXForcing the state(can implement as NMOS-only)Use the clock as a decoupling signal, that distinguishes between the transparent and opaque statesMux-Based Latches22Negative latch(transparent when CLK= 0)Positive latch(transparent when CLK= 1)CLK10DQ0CLK1DQ

Mux-Based Latch23

Mux-Based Latch24

NMOS onlyNon-overlapping clocksMaster-Slave (Edge-Triggered) Register25

Two opposite latches trigger on edgeAlso called master-slave latch pair Master-Slave Register26

Multiplexer-based latch pairReduced Clock Load Master-Slave Register

27Avoiding Clock Overlap28CLKCLKAB(a) Schematic diagram(b) Overlapping clock pairsXDQCLKCLKCLKCLKNeed to use non-overlapping clocks f1 and f2Must be careful about limiting the non-overlapping periodCross-Coupled Pairs29

NOR-based set-resetCross-Coupled NAND30

Cross-coupled NANDsAdded clockThis is not used in datapaths any more,but is a basic building memory cellStorage Mechanisms31DCLKCLKQDynamic (charge-based)

Static32Pulse-Triggered LatchesAn Alternative ApproachMaster-Slave LatchesDClkQDClkQClkDataDClkQClkDataPulse-Triggered LatchL1L2LWays to design an edge-triggered sequential cell:33Other Latches/Registers: C2MOS

Keepers can be added to make circuit pseudo-staticClocked CMOS