EE 308 Spring 2006

Disassembly of an HC12 Program

• It is sometimes useful to be able to convert HC12 op codes into mnemonics.

• For example, consider the hex code:

ADDR DATA

---- ------------------------------------------------------

2000 C6 05 FE 10 00 E6 01 18 06 B7 E5 04 35 EE 3F

• To determine the instructions, use Tables A.2 through A.7 of the S12CPUV2 ReferenceManual.

– If the first byte of the instruction is anything other than $18, use Sheet 1 ofTable A.2 (Page 395). From this table, determine the number of bytes of theinstruction and the addressing mode. For example, $C6 is a two-byte instruction,the mnemonic is LDAB, and it uses the IMM addressing mode. Thus, the two bytesC6 05 is the op code for the instruction LDAB #$05.

– The op code FE is LDX using the EXT addressing mode, and has 3 bytes total, withthe last two bytes being the extended address. Thus, FE 10 00 is the instructionLDX $1000.

– Indexed addressing mode is fairly complicated to disassemble. You need to useTable A.3 to determine the operand. For example, the op code $E6 indicates LDABindexed, and may use two to four bytes (one to three bytes in addition to the opcode). The postbyte 01 indicates that the operand is 0,1, which is 5-bit constantoffest, which takes only one additional byte. All 5-bit constant offset, pre and postincrement and decrement, and register offset instructions use one additional byte.All 9-bit constant offset instructions use two additional bytes, with the secondbyte holding 8 bits of the 9 bit offset. (The 9th bit is a direction bit, which is heldin the first postbyte.) All 16-bit constant offset instructions use three postbytes,withe the 2nd and 3rd holding the 16-bit unsigned offset.

– If the first byte is $18, use Sheet 2 of Table A.2 (Page 396). For example, 18 06

is a two byte instruction, the mnemonic is ABA, and it uses the INH addressingmode, so there is no operand. Thus, the two bytes 18 06 is the op code for theinstruction ABA.

– Transfer (TFR) and exchange (EXG) instructions all have the op code $B7 withone post-byte. Use Table A.5 to determine whether it is TFR or an EXG, and todetermine which registers are being used. If the most significant bit of the postbyteis 0, the instruction is a transfer instruction. B7 E5 is the code for the instructionEXG Y,X.

– Loop instructions (Decrement and Branch, Increment and Branch, and Test andBranch) all have the op code $04. To determine which instruction the op code$04 implies, and whether the branch is positive (forward) or negative (backward),use Table A.6. For example, in the sequence 04 35 EE, the 04 indicates a loopinstruction. The 35 indicates it is a DBNE X instruction (decrement register X andbranch if result is not equal to zero), and the direction is backward (negative).The EE indicates a branch of -1810 bytes (take the 2’s complement of EE.

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EE 308 Spring 2006

• Use up all the bytes for one instruction, then go on to the next instruction.

ADDR DATA

---- ------------------------------------------------------

2000 C6 05 FE 10 00 E6 01 18 06 B7 E5 04 35 EE 3F

---- ------------------------------------------------------

2000 C6 05 => LDAB #$05 two-byte LDAB, IMM addressing mode

2002 FE 10 00 => LDX $1000 three-byte LDX, EXT addressing mode

2005 E6 01 => LDAB 1,X two to four-byte LDAB, IDX addressing

mode. Operand 01 => 1,X, a 5b constant

offset which uses only one postbyte

2007 18 06 => ABA two-byte ABA, INH addressing mode

2009 B7 E5 => EXG Y,X two-byte exchange/transfer instruction

MSB of post-byte = 1 => exchange

From Table A.5, E5 => (Y <=> X)

200b 04 35 EE => DBNE X,(-18) three-byte loop instruction

Postbyte 35 indicates DBNE X, negative

2’s complement of 0xEE is -18 decimal

200e 3F => SWI one-byte SWI, INH addressing mode

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Table A-2. CPU12 Opcode Map (Sheet 1 of 2)

00 †5

BGNDIH 1

10 1

ANDCCIM 2

20 3

BRARL 2

30 3

PULXIH 1

40 1

NEGAIH 1

50 1

NEGBIH 1

60 3-6

NEGID 2-4

70 4

NEGEX 3

80 1

SUBAIM 2

90 3

SUBADI 2

A0 3-6

SUBAID 2-4

B0 3

SUBAEX 3

C0 1

SUBBIM 2

D0 3

SUBBDI 2

E0 3-6

SUBBID 2-4

F0 3

SUBBEX 3

01 5

MEMIH 1

11 11

EDIVIH 1

21 1

BRNRL 2

31 3

PULYIH 1

41 1

COMAIH 1

51 1

COMBIH 1

61 3-6

COMID 2-4

71 4

COMEX 3

81 1

CMPAIM 2

91 3

CMPADI 2

A1 3-6

CMPAID 2-4

B1 3

CMPAEX 3

C1 1

CMPBIM 2

D1 3

CMPBDI 2

E1 3-6

CMPBID 2-4

F1 3

CMPBEX 3

02 1

INYIH 1

12 ‡1

MULIH 1

22 3/1

BHIRL 2

32 3

PULAIH 1

42 1

INCAIH 1

52 1

INCBIH 1

62 3-6

INCID 2-4

72 4

INCEX 3

82 1

SBCAIM 2

92 3

SBCADI 2

A2 3-6

SBCAID 2-4

B2 3

SBCAEX 3

C2 1

SBCBIM 2

D2 3

SBCBDI 2

E2 3-6

SBCBID 2-4

F2 3

SBCBEX 3

03 1

DEYIH 1

13 3

EMULIH 1

23 3/1

BLSRL 2

33 3

PULBIH 1

43 1

DECAIH 1

53 1

DECBIH 1

63 3-6

DECID 2-4

73 4

DECEX 3

83 2

SUBDIM 3

93 3

SUBDDI 2

A3 3-6

SUBDID 2-4

B3 3

SUBDEX 3

C3 2

ADDDIM 3

D3 3

ADDDDI 2

E3 3-6

ADDDID 2-4

F3 3

ADDDEX 3

04 3

loop*

RL 3

14 1

ORCCIM 2

24 3/1

BCCRL 2

34 2

PSHXIH 1

44 1

LSRAIH 1

54 1

LSRBIH 1

64 3-6

LSRID 2-4

74 4

LSREX 3

84 1

ANDAIM 2

94 3

ANDADI 2

A4 3-6

ANDAID 2-4

B4 3

ANDAEX 3

C4 1

ANDBIM 2

D4 3

ANDBDI 2

E4 3-6

ANDBID 2-4

F4 3

ANDBEX 3

05 3-6

JMPID 2-4

15 4-7

JSRID 2-4

25 3/1

BCSRL 2

35 2

PSHYIH 1

45 1

ROLAIH 1

55 1

ROLBIH 1

65 3-6

ROLID 2-4

75 4

ROLEX 3

85 1

BITAIM 2

95 3

BITADI 2

A5 3-6

BITAID 2-4

B5 3

BITAEX 3

C5 1

BITBIM 2

D5 3

BITBDI 2

E5 3-6

BITBID 2-4

F5 3

BITBEX 3

06 3

JMPEX 3

16 4

JSREX 3

26 3/1

BNERL 2

36 2

PSHAIH 1

46 1

RORAIH 1

56 1

RORBIH 1

66 3-6

RORID 2-4

76 4

ROREX 3

86 1

LDAAIM 2

96 3

LDAADI 2

A6 3-6

LDAAID 2-4

B6 3

LDAAEX 3

C6 1

LDABIM 2

D6 3

LDABDI 2

E6 3-6

LDABID 2-4

F6 3

LDABEX 3

07 4

BSRRL 2

17 4

JSRDI 2

27 3/1

BEQRL 2

37 2

PSHBIH 1

47 1

ASRAIH 1

57 1

ASRBIH 1

67 3-6

ASRID 2-4

77 4

ASREX 3

87 1

CLRAIH 1

97 1

TSTAIH 1

A7 1

NOPIH 1

B7 1

TFR/EXGIH 2

C7 1

CLRBIH 1

D7 1

TSTBIH 1

E7 3-6

TSTID 2-4

F7 3

TSTEX 3

08 1

INXIH 1

18 -

Page 2- -

28 3/1

BVCRL 2

38 3

PULCIH 1

48 1

ASLAIH 1

58 1

ASLBIH 1

68 3-6

ASLID 2-4

78 4

ASLEX 3

88 1

EORAIM 2

98 3

EORADI 2

A8 3-6

EORAID 2-4

B8 3

EORAEX 3

C8 1

EORBIM 2

D8 3

EORBDI 2

E8 3-6

EORBID 2-4

F8 3

EORBEX 3

09 1

DEXIH 1

19 2

LEAYID 2-4

29 3/1

BVSRL 2

39 2

PSHCIH 1

49 1

LSRDIH 1

59 1

ASLDIH 1

69 ‡2-4

CLRID 2-4

79 3

CLREX 3

89 1

ADCAIM 2

99 3

ADCADI 2

A9 3-6

ADCAID 2-4

B9 3

ADCAEX 3

C9 1

ADCBIM 2

D9 3

ADCBDI 2

E9 3-6

ADCBID 2-4

F9 3

ADCBEX 3

0A ‡7

RTCIH 1

1A 2

LEAXID 2-4

2A 3/1

BPLRL 2

3A 3

PULDIH 1

4A ‡7

CALLEX 4

5A 2

STAADI 2

6A ‡2-4

STAAID 2-4

7A 3

STAAEX 3

8A 1

ORAAIM 2

9A 3

ORAADI 2

AA 3-6

ORAAID 2-4

BA 3

ORAAEX 3

CA 1

ORABIM 2

DA 3

ORABDI 2

EA 3-6

ORABID 2-4

FA 3

ORABEX 3

0B †8

RTIIH 1

1B 2

LEASID 2-4

2B 3/1

BMIRL 2

3B 2

PSHDIH 1

4B ‡7-10

CALLID 2-5

5B 2

STABDI 2

6B ‡2-4

STABID 2-4

7B 3

STABEX 3

8B 1

ADDAIM 2

9B 3

ADDADI 2

AB 3-6

ADDAID 2-4

BB 3

ADDAEX 3

CB 1

ADDBIM 2

DB 3

ADDBDI 2

EB 3-6

ADDBID 2-4

FB 3

ADDBEX 3

0C 4-6

BSETID 3-5

1C 4

BSETEX 4

2C 3/1

BGERL 2

3C ‡+5

wavrSP 1

4C 4

BSETDI 3

5C 2

STDDI 2

6C ‡2-4

STDID 2-4

7C 3

STDEX 3

8C 2

CPDIM 3

9C 3

CPDDI 2

AC 3-6

CPDID 2-4

BC 3

CPDEX 3

CC 2

LDDIM 3

DC 3

LDDDI 2

EC 3-6

LDDID 2-4

FC 3

LDDEX 3

0D 4-6

BCLRID 3-5

1D 4

BCLREX 4

2D 3/1

BLTRL 2

3D 5

RTSIH 1

4D 4

BCLRDI 3

5D 2

STYDI 2

6D ‡2-4

STYID 2-4

7D 3

STYEX 3

8D 2

CPYIM 3

9D 3

CPYDI 2

AD 3-6

CPYID 2-4

BD 3

CPYEX 3

CD 2

LDYIM 3

DD 3

LDYDI 2

ED 3-6

LDYID 2-4

FD 3

LDYEX 3

0E ‡4-6

BRSETID 4-6

1E 5

BRSETEX 5

2E 3/1

BGTRL 2

3E ‡†7

WAIIH 1

4E 4

BRSETDI 4

5E 2

STXDI 2

6E ‡2-4

STXID 2-4

7E 3

STXEX 3

8E 2

CPXIM 3

9E 3

CPXDI 2

AE 3-6

CPXID 2-4

BE 3

CPXEX 3

CE 2

LDXIM 3

DE 3

LDXDI 2

EE 3-6

LDXID 2-4

FE 3

LDXEX 3

0F ‡4-6

BRCLRID 4-6

1F 5

BRCLREX 5

2F 3/1

BLERL 2

3F 9

SWIIH 1

4F 4

BRCLRDI 4

5F 2

STSDI 2

6F ‡2-4

STSID 2-4

7F 3

STSEX 3

8F 2

CPSIM 3

9F 3

CPSDI 2

AF 3-6

CPSID 2-4

BF 3

CPSEX 3

CF 2

LDSIM 3

DF 3

LDSDI 2

EF 3-6

LDSID 2-4

FF 3

LDSEX 3

00 5

BGNDIH I

Number of HCS12 cycles (‡ indicates HC12 different)

Key to Table A-2

Number of bytes

OpcodeMnemonic

Address Mode

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* The opcode $04 (on sheet 1 of 2) corresponds to one of the loop primitive instructions DBEQ, DBNE, IBEQ, IBNE, TBEQ, or TBNE.

† Refer to instruction summary for more information.

‡ Refer to instruction summary for different HC12 cycle count.

Page 2: When the CPU encounters a page 2 opcode ($18 on page 1 of the opcode map), it treats the next byte of object code as a page 2 instruction opcode.

00 4MOVW

IM-ID 5

10 12IDIV

IH 2

20 4LBRA

RL 4

30 10TRAP

IH 2

40 10TRAP

IH 2

50 10TRAP

IH 2

60 10TRAP

IH 2

70 10TRAP

IH 2

80 10TRAP

IH 2

90 10TRAP

IH 2

A0 10TRAP

IH 2

B0 10TRAP

IH 2

C0 10TRAP

IH 2

D0 10TRAP

IH 2

E0 10TRAP

IH 2

F0 10TRAP

IH 2

01 5MOVW

EX-ID 5

11 12FDIV

IH 2

21 3LBRN

RL 4

31 10TRAP

IH 2

41 10TRAP

IH 2

51 10TRAP

IH 2

61 10TRAP

IH 2

71 10TRAP

IH 2

81 10TRAP

IH 2

91 10TRAP

IH 2

A1 10TRAP

IH 2

B1 10TRAP

IH 2

C1 10TRAP

IH 2

D1 10TRAP

IH 2

E1 10TRAP

IH 2

F1 10TRAP

IH 2

02 5MOVW

ID-ID 4

12 13EMACSSP 4

22 4/3LBHI

RL 4

32 10TRAP

IH 2

42 10TRAP

IH 2

52 10TRAP

IH 2

62 10TRAP

IH 2

72 10TRAP

IH 2

82 10TRAP

IH 2

92 10TRAP

IH 2

A2 10TRAP

IH 2

B2 10TRAP

IH 2

C2 10TRAP

IH 2

D2 10TRAP

IH 2

E2 10TRAP

IH 2

F2 10TRAP

IH 2

03 5MOVW

IM-EX 6

13 3EMULSIH 2

23 4/3LBLS

RL 4

33 10TRAP

IH 2

43 10TRAP

IH 2

53 10TRAP

IH 2

63 10TRAP

IH 2

73 10TRAP

IH 2

83 10TRAP

IH 2

93 10TRAP

IH 2

A3 10TRAP

IH 2

B3 10TRAP

IH 2

C3 10TRAP

IH 2

D3 10TRAP

IH 2

E3 10TRAP

IH 2

F3 10TRAP

IH 2

04 6MOVW

EX-EX 6

14 12EDIVS

IH 2

24 4/3LBCC

RL 4

34 10TRAP

IH 2

44 10TRAP

IH 2

54 10TRAP

IH 2

64 10TRAP

IH 2

74 10TRAP

IH 2

84 10TRAP

IH 2

94 10TRAP

IH 2

A4 10TRAP

IH 2

B4 10TRAP

IH 2

C4 10TRAP

IH 2

D4 10TRAP

IH 2

E4 10TRAP

IH 2

F4 10TRAP

IH 2

05 5MOVW

ID-EX 5

15 12IDIVS

IH 2

25 4/3LBCS

RL 4

35 10TRAP

IH 2

45 10TRAP

IH 2

55 10TRAP

IH 2

65 10TRAP

IH 2

75 10TRAP

IH 2

85 10TRAP

IH 2

95 10TRAP

IH 2

A5 10TRAP

IH 2

B5 10TRAP

IH 2

C5 10TRAP

IH 2

D5 10TRAP

IH 2

E5 10TRAP

IH 2

F5 10TRAP

IH 2

06 2ABA

IH 2

16 2SBA

IH 2

26 4/3LBNE

RL 4

36 10TRAP

IH 2

46 10TRAP

IH 2

56 10TRAP

IH 2

66 10TRAP

IH 2

76 10TRAP

IH 2

86 10TRAP

IH 2

96 10TRAP

IH 2

A6 10TRAP

IH 2

B6 10TRAP

IH 2

C6 10TRAP

IH 2

D6 10TRAP

IH 2

E6 10TRAP

IH 2

F6 10TRAP

IH 2

07 3DAA

IH 2

17 2CBA

IH 2

27 4/3LBEQ

RL 4

37 10TRAP

IH 2

47 10TRAP

IH 2

57 10TRAP

IH 2

67 10TRAP

IH 2

77 10TRAP

IH 2

87 10TRAP

IH 2

97 10TRAP

IH 2

A7 10TRAP

IH 2

B7 10TRAP

IH 2

C7 10TRAP

IH 2

D7 10TRAP

IH 2

E7 10TRAP

IH 2

F7 10TRAP

IH 2

08 4MOVB

IM-ID 4

18 4-7MAXA

ID 3-5

28 4/3LBVC

RL 4

38 10TRAP

IH 2

48 10TRAP

IH 2

58 10TRAP

IH 2

68 10TRAP

IH 2

78 10TRAP

IH 2

88 10TRAP

IH 2

98 10TRAP

IH 2

A8 10TRAP

IH 2

B8 10TRAP

IH 2

C8 10TRAP

IH 2

D8 10TRAP

IH 2

E8 10TRAP

IH 2

F8 10TRAP

IH 2

09 5MOVB

EX-ID 5

19 4-7MINA

ID 3-5

29 4/3LBVS

RL 4

39 10TRAP

IH 2

49 10TRAP

IH 2

59 10TRAP

IH 2

69 10TRAP

IH 2

79 10TRAP

IH 2

89 10TRAP

IH 2

99 10TRAP

IH 2

A9 10TRAP

IH 2

B9 10TRAP

IH 2

C9 10TRAP

IH 2

D9 10TRAP

IH 2

E9 10TRAP

IH 2

F9 10TRAP

IH 2

0A 5MOVB

ID-ID 4

1A 4-7EMAXDID 3-5

2A 4/3LBPL

RL 4

3A †3nREV

SP 2

4A 10TRAP

IH 2

5A 10TRAP

IH 2

6A 10TRAP

IH 2

7A 10TRAP

IH 2

8A 10TRAP

IH 2

9A 10TRAP

IH 2

AA 10TRAP

IH 2

BA 10TRAP

IH 2

CA 10TRAP

IH 2

DA 10TRAP

IH 2

EA 10TRAP

IH 2

FA 10TRAP

IH 2

0B 4MOVB

IM-EX 5

1B 4-7EMIND

ID 3-5

2B 4/3LBMI

RL 4

3B †5n/3nREVW

SP 2

4B 10TRAP

IH 2

5B 10TRAP

IH 2

6B 10TRAP

IH 2

7B 10TRAP

IH 2

8B 10TRAP

IH 2

9B 10TRAP

IH 2

AB 10TRAP

IH 2

BB 10TRAP

IH 2

CB 10TRAP

IH 2

DB 10TRAP

IH 2

EB 10TRAP

IH 2

FB 10TRAP

IH 2

0C 6MOVB

EX-EX 6

1C 4-7MAXM

ID 3-5

2C 4/3LBGE

RL 4

3C ‡†7BWAV

SP 2

4C 10TRAP

IH 2

5C 10TRAP

IH 2

6C 10TRAP

IH 2

7C 10TRAP

IH 2

8C 10TRAP

IH 2

9C 10TRAP

IH 2

AC 10TRAP

IH 2

BC 10TRAP

IH 2

CC 10TRAP

IH 2

DC 10TRAP

IH 2

EC 10TRAP

IH 2

FC 10TRAP

IH 2

0D 5MOVB

ID-EX 5

1D D4-7MINM

ID 3-5

2D 4/3LBLT

RL 4

3D ‡6TBL

ID 3

4D 10TRAP

IH 2

5D 10TRAP

IH 2

6D 10TRAP

IH 2

7D 10TRAP

IH 2

8D 10TRAP

IH 2

9D 10TRAP

IH 2

AD 10TRAP

IH 2

BD 10TRAP

IH 2

CD 10TRAP

IH 2

DD 10TRAP

IH 2

ED 10TRAP

IH 2

FD 10TRAP

IH 2

0E 2TAB

IH 2

1E 4-7EMAXMID 3-5

2E 4/3LBGT

RL 4

3E ‡8STOP

IH 2

4E 10TRAP

IH 2

5E 10TRAP

IH 2

6E 10TRAP

IH 2

7E 10TRAP

IH 2

8E 10TRAP

IH 2

9E 10TRAP

IH 2

AE 10TRAP

IH 2

BE 10TRAP

IH 2

CE 10TRAP

IH 2

DE 10TRAP

IH 2

EE 10TRAP

IH 2

FE 10TRAP

IH 2

0F 2TBA

IH 2

1F 4-7EMINM

ID 3-5

2F 4/3LBLE

RL 4

3F 10ETBL

ID 3

4F 10TRAP

IH 2

5F 10TRAP

IH 2

6F 10TRAP

IH 2

7F 10TRAP

IH 2

8F 10TRAP

IH 2

9F 10TRAP

IH 2

AF 10TRAP

IH 2

BF 10TRAP

IH 2

CF 10TRAP

IH 2

DF 10TRAP

IH 2

EF 10TRAP

IH 2

FF 10TRAP

IH 2

Table A-2. CPU12 Opcode Map (Sheet 2 of 2)

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Table A-3. Indexed Addressing Mode Postbyte Encoding (xb)

000,X

5b const

10–16,X

5b const

201,+X

pre-inc

301,X+

post-inc

400,Y

5b const

50–16,Y

5b const

601,+Y

pre-inc

701,Y+

post-inc

800,SP

5b const

90–16,SP

5b const

A01,+SP

pre-inc

B01,SP+

post-inc

C00,PC

5b const

D0–16,PC

5b const

E0n,X

9b const

F0n,SP

9b const

011,X

5b const

11–15,X

5b const

212,+X

pre-inc

312,X+

post-inc

411,Y

5b const

51–15,Y

5b const

612,+Y

pre-inc

712,Y+

post-inc

811,SP

5b const

91–15,SP

5b const

A12,+SP

pre-inc

B12,SP+

post-inc

C11,PC

5b const

D1–15,PC

5b const

E1–n,X

9b const

F1–n,SP

9b const

022,X

5b const

12–14,X

5b const

223,+X

pre-inc

323,X+

post-inc

422,Y

5b const

52–14,Y

5b const

623,+Y

pre-inc

723,Y+

post-inc

822,SP

5b const

92–14,SP

5b const

A23,+SP

pre-inc

B23,SP+

post-inc

C22,PC

5b const

D2–14,PC

5b const

E2n,X

16b const

F2n,SP

16b const

033,X

5b const

13–13,X

5b const

234,+X

pre-inc

334,X+

post-inc

433,Y

5b const

53–13,Y

5b const

634,+Y

pre-inc

734,Y+

post-inc

833,SP

5b const

93–13,SP

5b const

A34,+SP

pre-inc

B34,SP+

post-inc

C33,PC

5b const

D3–13,PC

5b const

E3[n,X]

16b indr

F3[n,SP]

16b indr

044,X

5b const

14–12,X

5b const

245,+X

pre-inc

345,X+

post-inc

444,Y

5b const

54–12,Y

5b const

645,+Y

pre-inc

745,Y+

post-inc

844,SP

5b const

94–12,SP

5b const

A45,+SP

pre-inc

B45,SP+

post-inc

C44,PC

5b const

D4–12,PC

5b const

E4A,X

A offset

F4A,SP

A offset

055,X

5b const

15–11,X

5b const

256,+X

pre-inc

356,X+

post-inc

455,Y

5b const

55–11,Y

5b const

656,+Y

pre-inc

756,Y+

post-inc

855,SP

5b const

95–11,SP

5b const

A56,+SP

pre-inc

B56,SP+

post-inc

C55,PC

5b const

D5–11,PC

5b const

E5B,X

B offset

F5B,SP

B offset

066,X

5b const

16–10,X

5b const

267,+X

pre-inc

367,X+

post-inc

466,Y

5b const

56–10,Y

5b const

667,+Y

pre-inc

767,Y+

post-inc

866,SP

5b const

96–10,SP

5b const

A67,+SP

pre-inc

B67,SP+

post-inc

C66,PC

5b const

D6–10,PC

5b const

E6D,X

D offset

F6D,SP

D offset

077,X

5b const

17–9,X

5b const

278,+X

pre-inc

378,X+

post-inc

477,Y

5b const

57–9,Y

5b const

678,+Y

pre-inc

778,Y+

post-inc

877,SP

5b const

97–9,SP

5b const

A78,+SP

pre-inc

B78,SP+

post-inc

C77,PC

5b const

D7–9,PC

5b const

E7[D,X]

D indirect

F7[D,SP]

D indirect

088,X

5b const

18–8,X

5b const

288,–X

pre-dec

388,X–

post-dec

488,Y

5b const

58–8,Y

5b const

688,–Y

pre-dec

788,Y–

post-dec

888,SP

5b const

98–8,SP

5b const

A88,–SP

pre-dec

B88,SP–

post-dec

C88,PC

5b const

D8–8,PC

5b const

E8n,Y

9b const

F8n,PC

9b const

099,X

5b const

19–7,X

5b const

297,–X

pre-dec

397,X–

post-dec

499,Y

5b const

59–7,Y

5b const

697,–Y

pre-dec

797,Y–

post-dec

899,SP

5b const

99–7,SP

5b const

A97,–SP

pre-dec

B97,SP–

post-dec

C99,PC

5b const

D9–7,PC

5b const

E9–n,Y

9b const

F9–n,PC

9b const

0A10,X

5b const

1A–6,X

5b const

2A6,–X

pre-dec

3A6,X–

post-dec

4A10,Y

5b const

5A–6,Y

5b const

6A6,–Y

pre-dec

7A6,Y–

post-dec

8A10,SP

5b const

9A–6,SP

5b const

AA6,–SP

pre-dec

BA6,SP–

post-dec

CA10,PC

5b const

DA–6,PC

5b const

EAn,Y

16b const

FAn,PC

16b const

0B11,X

5b const

1B–5,X

5b const

2B5,–X

pre-dec

3B5,X–

post-dec

4B11,Y

5b const

5B–5,Y

5b const

6B5,–Y

pre-dec

7B5,Y–

post-dec

8B11,SP

5b const

9B–5,SP

5b const

AB5,–SP

pre-dec

BB5,SP–

post-dec

CB11,PC

5b const

DB–5,PC

5b const

EB[n,Y]

16b indr

FB[n,PC]

16b indr

0C12,X

5b const

1C–4,X

5b const

2C4,–X

pre-dec

3C4,X–

post-dec

4C12,Y

5b const

5C–4,Y

5b const

6C4,–Y

pre-dec

7C4,Y–

post-dec

8C12,SP

5b const

9C–4,SP

5b const

AC4,–SP

pre-dec

BC4,SP–

post-dec

CC12,PC

5b const

DC–4,PC

5b const

ECA,Y

A offset

FCA,PC

A offset

0D13,X

5b const

1D–3,X

5b const

2D3,–X

pre-dec

3D3,X–

post-dec

4D13,Y

5b const

5D–3,Y

5b const

6D3,–Y

pre-dec

7D3,Y–

post-dec

8D13,SP

5b const

9D–3,SP

5b const

AD3,–SP

pre-dec

BD3,SP–

post-dec

CD13,PC

5b const

DD–3,PC

5b const

EDB,Y

B offset

FDB,PC

B offset

0E14,X

5b const

1E–2,X

5b const

2E2,–X

pre-dec

3E2,X–

post-dec

4E14,Y

5b const

5E–2,Y

5b const

6E2,–Y

pre-dec

7E2,Y–

post-dec

8E14,SP

5b const

9E–2,SP

5b const

AE2,–SP

pre-dec

BE2,SP–

post-dec

CE14,PC

5b const

DE–2,PC

5b const

EED,Y

D offset

FED,PC

D offset

0F15,X

5b const

1F–1,X

5b const

2F1,–X

pre-dec

3F1,X–

post-dec

4F15,Y

5b const

5F–1,Y

5b const

6F1,–Y

pre-dec

7F1,Y–

post-dec

8F15,SP

5b const

9F–1,SP

5b const

AF1,–SP

pre-dec

BF1,SP–

post-dec

CF15,PC

5b const

DF–1,PC

5b const

EF[D,Y]

D indirect

FF[D,PC]

D indirect

postbyte (hex)

B0

#,REGtype

type offset used

source code syntax

Key to Table A-3

5

EE 308 Spring 2006

S1

2C

PU

V2

Re

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99

Table A-5. Transfer and Exchange Postbyte Encoding

TRANSFERS

⇓ LS MS⇒ 0 1 2 3 4 5 6 7

0 A ⇒ A B ⇒ A CCR ⇒ A TMP3L ⇒ A B ⇒ A XL ⇒ A YL ⇒ A SPL ⇒ A

1 A ⇒ B B ⇒ B CCR ⇒ B TMP3L ⇒ B B ⇒ B XL ⇒ B YL ⇒ B SPL ⇒ B

2 A ⇒ CCR B ⇒ CCR CCR ⇒ CCR TMP3L ⇒ CCR B ⇒ CCR XL ⇒ CCR YL ⇒ CCR SPL ⇒ CCR

3 sex:A ⇒ TMP2 sex:B ⇒ TMP2 sex:CCR ⇒ TMP2 TMP3 ⇒ TMP2 D ⇒ TMP2 X ⇒ TMP2 Y ⇒ TMP2 SP ⇒ TMP2

4sex:A ⇒ D

SEX A,D

sex:B ⇒ D

SEX B,D

sex:CCR ⇒ D

SEX CCR,DTMP3 ⇒ D D ⇒ D X ⇒ D Y ⇒ D SP ⇒ D

5sex:A ⇒ X

SEX A,X

sex:B ⇒ X

SEX B,X

sex:CCR ⇒ X

SEX CCR,XTMP3 ⇒ X D ⇒ X X ⇒ X Y ⇒ X SP ⇒ X

6sex:A ⇒ Y

SEX A,Y

sex:B ⇒ Y

SEX B,Y

sex:CCR ⇒ Y

SEX CCR,YTMP3 ⇒ Y D ⇒ Y X ⇒ Y Y ⇒ Y SP ⇒ Y

7sex:A ⇒ SP

SEX A,SP

sex:B ⇒ SP

SEX B,SP

sex:CCR ⇒ SP

SEX CCR,SPTMP3 ⇒ SP D ⇒ SP X ⇒ SP Y ⇒ SP SP ⇒ SP

EXCHANGES

⇓ LS MS⇒ 8 9 A B C D E F

0 A ⇔ A B ⇔ A CCR ⇔ ATMP3L ⇒ A

$00:A ⇒ TMP3

B ⇒ A

A ⇒ B

XL ⇒ A

$00:A ⇒ X

YL ⇒ A

$00:A ⇒ Y

SPL ⇒ A

$00:A ⇒ SP

1 A ⇔ B B ⇔ B CCR ⇔ BTMP3L ⇒ B

$FF:B ⇒ TMP3

B ⇒ B

$FF ⇒ A

XL ⇒ B

$FF:B ⇒ X

YL ⇒ B

$FF:B ⇒ Y

SPL ⇒ B

$FF:B ⇒ SP

2 A ⇔ CCR B ⇔ CCR CCR ⇔ CCRTMP3L ⇒ CCR

$FF:CCR ⇒ TMP3

B ⇒ CCR

$FF:CCR ⇒ D

XL ⇒ CCR

$FF:CCR ⇒ X

YL ⇒ CCR

$FF:CCR ⇒ Y

SPL ⇒ CCR

$FF:CCR ⇒ SP

3$00:A ⇒ TMP2

TMP2L ⇒ A

$00:B ⇒ TMP2

TMP2L ⇒ B

$00:CCR ⇒ TMP2

TMP2L ⇒ CCRTMP3 ⇔ TMP2 D ⇔ TMP2 X ⇔ TMP2 Y ⇔ TMP2 SP ⇔ TMP2

4 $00:A ⇒ D $00:B ⇒ D$00:CCR ⇒ D

B ⇒ CCRTMP3 ⇔ D D ⇔ D X ⇔ D Y ⇔ D SP ⇔ D

5$00:A ⇒ X

XL ⇒ A

$00:B ⇒ X

XL ⇒ B

$00:CCR ⇒ X

XL ⇒ CCRTMP3 ⇔ X D ⇔ X X ⇔ X Y ⇔ X SP ⇔ X

6$00:A ⇒ Y

YL ⇒ A

$00:B ⇒ Y

YL ⇒ B

$00:CCR ⇒ Y

YL ⇒ CCRTMP3 ⇔ Y D ⇔ Y X ⇔ Y Y ⇔ Y SP ⇔ Y

7$00:A ⇒ SP

SPL ⇒ A

$00:B ⇒ SP

SPL ⇒ B

$00:CCR ⇒ SP

SPL ⇒ CCRTMP3 ⇔ SP D ⇔ SP X ⇔ SP Y ⇔ SP SP ⇔ SP

TMP2 and TMP3 registers are for factory use only.

6

EE 308 Spring 2006

S12CPUV2 Reference Manual, Rev. 4.0

400 Freescale Semiconductor

Table A-6. Loop Primitive Postbyte Encoding (lb)

00 ADBEQ

(+)

10 ADBEQ

(–)

20 ADBNE

(+)

30 ADBNE

(–)

40 ATBEQ

(+)

50 ATBEQ

(–)

60 ATBNE

(+)

70 ATBNE

(–)

80 AIBEQ

(+)

90 AIBEQ

(–)

A0 AIBNE

(+)

B0 AIBNE

(–)

01 BDBEQ

(+)

11 BDBEQ

(–)

21 BDBNE

(+)

31 BDBNE

(–)

41 BTBEQ

(+)

51 BTBEQ

(–)

61 BTBNE

(+)

71 BTBNE

(–)

81 BIBEQ

(+)

91 BIBEQ

(–)

A1 BIBNE

(+)

B1 BIBNE

(–)

02—

12—

22—

32—

42—

52—

62—

72—

82—

92—

A2—

B2—

03—

13—

23—

33—

43—

53—

63—

73—

83—

93—

A3—

B3—

04 DDBEQ

(+)

14 DDBEQ

(–)

24 DDBNE

(+)

34 DDBNE

(–)

44 DTBEQ

(+)

54 DTBEQ

(–)

64 DTBNE

(+)

74 DTBNE

(–)

84 DIBEQ

(+)

94 DIBEQ

(–)

A4 DIBNE

(+)

B4 DIBNE

(–)

05 XDBEQ

(+)

15 XDBEQ

(–)

25 XDBNE

(+)

35 XDBNE

(–)

45 XTBEQ

(+)

55 XTBEQ

(–)

65 XTBNE

(+)

75 XTBNE

(–)

85 XIBEQ

(+)

95 XIBEQ

(–)

A5 XIBNE

(+)

B5 XIBNE

(–)

06 YDBEQ

(+)

16 YDBEQ

(–)

26 YDBNE

(+)

36 YDBNE

(–)

46 YTBEQ

(+)

56 YTBEQ

(–)

66 YTBNE

(+)

76 YTBNE

(–)

86 YIBEQ

(+)

96 YIBEQ

(–)

A6 YIBNE

(+)

B6 YIBNE

(–)

07 SPDBEQ

(+)

17 SPDBEQ

(–)

27 SPDBNE

(+)

37 SPDBNE

(–)

47 SPTBEQ

(+)

57 SPTBEQ

(–)

67 SPTBNE

(+)

77 SPTBNE

(–)

87 SPIBEQ

(+)

97 SPIBEQ

(–)

A7 SPIBNE

(+)

B7 SPIBNE

(–)

postbyte (hex)

B0 A_BEQ

(–)

counter used

sign of 9-bit relative branch offset(lower eight bits are an extension bytefollowing postbyte)

branch condition

Key to Table A-6

(bit 3 is don’t care)

Table A-7. Branch/Complementary Branch

Branch Complementary Branch

Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment

r>m BGT 2E Z + (N ⊕ V) = 0 r≤m BLE 2F Signed

r≥m BGE 2C N ⊕ V = 0 r<m BLT 2D Signed

r=m BEQ 27 Z = 1 r≠m BNE 26 Signed

r≤m BLE 2F Z + (N ⊕ V) = 1 r>m BGT 2E Signed

r<m BLT 2D N ⊕ V = 1 r≥m BGE 2C Signed

r>m BHI 22 C + Z = 0 r≤m BLS 23 Unsigned

r≥m BHS/BCC 24 C = 0 r<m BLO/BCS 25 Unsigned

r=m BEQ 27 Z = 1 r≠m BNE 26 Unsigned

r≤m BLS 23 C + Z = 1 r>m BHI 22 Unsigned

r<m BLO/BCS 25 C = 1 r≥m BHS/BCC 24 Unsigned

Carry BCS 25 C = 1 No Carry BCC 24 Simple

Negative BMI 2B N = 1 Plus BPL 2A Simple

Overflow BVS 29 V = 1 No Overflow BVC 28 Simple

r=0 BEQ 27 Z = 1 r≠0 BNE 26 Simple

Always BRA 20 — Never BRN 21 Unconditional

For 16-bit offset long branches precede opcode with a $18 page prebyte.

7

EE 308 Spring 2006

Binary, Hex and Decimal Numbers (4-bit representation)

Hex

0123456789ABCDEF

Decimal

0 1 2 3 4 5 6 7 8 9101112131415

Binary

0000000100100011010001010110011110001001101010111100110111101111

8

EE 308 Spring 2006

What does a number represent?

(Signed 8−bit number)

intends for the code.

0x72

’r’ (ASCII)

INC (HC12 instruction)

2.26V (Input from A/D converter)

11410

10

Some possible codes:

Set temperature in room to 69 F

Set cruise control speed to 120 mph

(Unsigned 8−bit number)

+114

Binary numbers are a code, and represent what the programmer

9

EE 308 Spring 2006

Binary to Unsigned Decimal:

1111011 2

1 x 2 + 1 x 2 + 1 x 25 4

+ 1 x 2 + 0 x 2 + 1 x 2 + 1 x 26 2 1 03

1 x 64 + 1 x 32 + 1 x 16 + 1 x 8 + 0 x 4 + 1 x 2 + 1 x 1

12310

Convert Binary to Unsigned Decimal

Hex to Unsigned Decimal

33494

8 x 16 + 2 x 16 + 13 x 16 + 6 x 16

82D6 16

2 1 03

8 x 4096 + 2 x 256 + 13 x 16 + 6 x 1

10

Convert Hex to Unsigned Decimal

10

EE 308 Spring 2006

Unsigned Decimal to Hex

721 = 2D1

Q

721/16

45/16

2/16

45

2

0

1

13

2

1

D

2

10 16

DivisionR

Decimal Hex

Convert Unsigned Decimal to Hex

11

EE 308 Spring 2006

If most significant bit is 0 (most significant hex digit 0−7), number is positive.Get decimal equivalent by converting number to decimal, and using + sign.

Example for 8−bit number:

If most significant bit is 1 (most significant hex digit 8−F), number is negative.Get decimal equivalent by taking 2’s complement of number, converting to decimal,and using − sign.

Example for 8−bit number:

Signed Number Representation in 2’s Complement Form:

16 − ( 5 x 16 + 13 x 16 )

− ( 5 x 16 + 13 x 1 )

− 93

3A −> + ( 3 x 16 + 10 x 16 )

+ ( 3 x 16 + 10 x 1 )

+ 58

16

A3 −> − ( 5D )

1

10

0

1010

161 0

10

10

10

12

EE 308 Spring 2006

One’s Complement Table Makes It Simple To Find 2’s Complements

0

1

2

3

4

5

6

7 8

D

E

F

9

A

B

C

One’s Complement Table

To take two’s complement, add one to one’s complement.

Take two’s complement of :D0C3

2F3C + 1 = 2F3D

13

EE 308 Spring 2006

Addition and Subtraction of Hexadecimal Numbers.Setting the C (Carry), V (Overflow), N (Negative) and Z (Zero) bits

How the C, V, N and Z bits of the CCR are changed

Condition Code Register Bits N, Z, V, C

N bit is set if result of operation in negative (MSB = 1)

Z bit is set if result of operation is zero (All bits = 0)

V bit is set if operation produced an overflow

C bit is set if operation produced a carry (borrow on subtraction)

Note: Not all instructions change these bits of the CCR

14

EE 308 Spring 2006

Addition of Hexadecimal Numbers

ADDITION:

C bit set when result does not fit in word

V bit set when P + P = N N + N = P

7A+52

CC

+52 2A

7C

+8A AC

36

+72 AC

1E

N bit set when MSB of result is 1

Z bit set when result is 0

C: 0 C: 1

V: 0

C: 0

V: 1

C: 1

V: 1 V: 0

N: 1 N: 0 N: 1

Z: 0 Z: 0 Z: 0

N: 0

Z: 0

15

EE 308 Spring 2006

Subtraction of Hexadecimal Numbers

SUBTRACTION:

C bit set on borrow (when the magnitude of the subtrahend

V bit set when N − P = P P − N = N

is greater than the minuend)

7A−5C

1E

−5C 8A

2E

5C−8A

D2

2C−72

BA

C: 0

V: 0

C: 1

V: 0

C: 0

V: 1V: 1

C: 1

N: 0 N: 0 N: 1 N: 1

Z: 0Z: 0Z: 0Z: 0

N bit set when MSB is 1

Z bit set when result is 0

16